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/******************************************************************************

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 *

     3

 *  $Id$

     4

 *

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 *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it

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 *  and/or modify it under the terms of the GNU General Public License

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 *  as published by the Free Software Foundation; either version 2 of the

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 *  License, or (at your option) any later version.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be

    15

 *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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 *  GNU General Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License

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 *  along with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

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 *  The right to use EtherCAT Technology is granted and comes free of

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 *  charge under condition of compatibility of product made by

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 *  Licensee. People intending to distribute/sell products based on the

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 *  code, have to sign an agreement to guarantee that products using

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 *  software based on IgH EtherCAT master stay compatible with the actual

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 *  EtherCAT specification (which are released themselves as an open

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 *  standard) as the (only) precondition to have the right to use EtherCAT

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 *  Technology, IP and trade marks.

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 *

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 *****************************************************************************/

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    34

/**

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   \file

    36

   EtherCAT driver for RTL8139-compatible NICs.

    37

*/

    38

    39

/*****************************************************************************/

    40

    41

/*

    42

  Former documentation:

    43

    44

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    45

    46

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

    48

    49

	Much code comes from Donald Becker's rtl8139.c driver,

    50

	versions 1.13 and older.  This driver was originally based

    51

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    52

    53

	-----<snip>-----

    54

    55

        	Written 1997-2001 by Donald Becker.

    56

		This software may be used and distributed according to the

    57

		terms of the GNU General Public License (GPL), incorporated

    58

		herein by reference.  Drivers based on or derived from this

    59

		code fall under the GPL and must retain the authorship,

    60

		copyright and license notice.  This file is not a complete

    61

		program and may only be used when the entire operating

    62

		system is licensed under the GPL.

    63

    64

		This driver is for boards based on the RTL8129 and RTL8139

    65

		PCI ethernet chips.

    66

    67

		The author may be reached as becker@scyld.com, or C/O Scyld

    68

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    69

		MD 21403

    70

    71

		Support and updates available at

    72

		http://www.scyld.com/network/rtl8139.html

    73

    74

		Twister-tuning table provided by Kinston

    75

		<shangh@realtek.com.tw>.

    76

    77

	-----<snip>-----

    78

    79

	This software may be used and distributed according to the terms

    80

	of the GNU General Public License, incorporated herein by reference.

    81

    82

	Contributors:

    83

    84

		Donald Becker - he wrote the original driver, kudos to him!

    85

		(but please don't e-mail him for support, this isn't his driver)

    86

    87

		Tigran Aivazian - bug fixes, skbuff free cleanup

    88

    89

		Martin Mares - suggestions for PCI cleanup

    90

    91

		David S. Miller - PCI DMA and softnet updates

    92

    93

		Ernst Gill - fixes ported from BSD driver

    94

    95

		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

    97

    98

		Gerard Sharp - bug fix, testing and feedback

    99

   100

		David Ford - Rx ring wrap fix

   101

   102

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

   103

		to find and fix a crucial bug on older chipsets.

   104

   105

		Donald Becker/Chris Butterworth/Marcus Westergren -

   106

		Noticed various Rx packet size-related buglets.

   107

   108

		Santiago Garcia Mantinan - testing and feedback

   109

   110

		Jens David - 2.2.x kernel backports

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   112

		Martin Dennett - incredibly helpful insight on undocumented

   113

		features of the 8139 chips

   114

   115

		Jean-Jacques Michel - bug fix

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   117

		Tobias Ringström - Rx interrupt status checking suggestion

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   119

		Andrew Morton - Clear blocked signals, avoid

   120

		buffer overrun setting current->comm.

   121

   122

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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   124

		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

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   128

		"rtl8139-diag -mmmaaavvveefN" output

   129

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   130

   131

*/

   132

   133

#define DRV_NAME	"ec_8139too"

   134

#define DRV_VERSION	"0.9.27"

   135

   137

#include <linux/config.h>

   138

#include <linux/module.h>

   139

#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

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#include <linux/init.h>

   143

#include <linux/ioport.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

   146

#include <linux/rtnetlink.h>

   147

#include <linux/delay.h>

   148

#include <linux/ethtool.h>

   149

#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <asm/io.h>

   153

#include <asm/uaccess.h>

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#include <asm/irq.h>

   155

   156

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   157

   158

#include "ecdev.h"

   159

   160

#define LIT(X) #X

   161

#define STR(X) LIT(X)

   162

   163

#define COMPILE_INFO "Revision " STR(EC_REV) \

   164

                     ", compiled by " STR(EC_USER) \

   165

                     " at " __DATE__ " " __TIME__

   166

   167

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   168

   169

#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   170

#define PFX DRV_NAME ": "

   171

   172

/* Default Message level */

   173

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

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                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

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   177

   178

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   179

#ifdef CONFIG_8139TOO_PIO

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#define USE_IO_OPS 1

   181

#endif

   182

   183

/* define to 1, 2 or 3 to enable copious debugging info */

   184

#define RTL8139_DEBUG 0

   185

   186

/* define to 1 to disable lightweight runtime debugging checks */

   187

#undef RTL8139_NDEBUG

   188

   189

   190

#if RTL8139_DEBUG

   191

/* note: prints function name for you */

   192

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

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#else

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#  define DPRINTK(fmt, args...)

   195

#endif

   196

   197

#ifdef RTL8139_NDEBUG

   198

#  define assert(expr) do {} while (0)

   199

#else

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#  define assert(expr) \

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        if(unlikely(!(expr))) {				        \

   202

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

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        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

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        }

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#endif

   206

   207

   208

/* A few user-configurable values. */

   209

/* media options */

   210

#define MAX_UNITS 8

   211

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   212

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   213

   214

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   215

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   216

static int multicast_filter_limit = 32;

   217

   218

/* bitmapped message enable number */

   219

static int debug = -1;

   220

   221

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   222

   223

static int ec_device_index = -1;

   224

static int ec_device_master_index = 0;

   225

static ec_device_t *rtl_ec_dev;

   226

struct net_device *rtl_ec_net_dev = NULL;

   227

   228

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   229

   230

/*

   231

 * Receive ring size 

   232

 * Warning: 64K ring has hardware issues and may lock up.

   233

 */

   234

#if defined(CONFIG_SH_DREAMCAST)

   235

#define RX_BUF_IDX	1	/* 16K ring */

   236

#else

   237

#define RX_BUF_IDX	2	/* 32K ring */

   238

#endif

   239

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   240

#define RX_BUF_PAD	16

   241

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   242

   243

#if RX_BUF_LEN == 65536

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#define RX_BUF_TOT_LEN	RX_BUF_LEN

   245

#else

   246

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   247

#endif

   248

   249

/* Number of Tx descriptor registers. */

   250

#define NUM_TX_DESC	4

   251

   252

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   253

#define MAX_ETH_FRAME_SIZE	1536

   254

   255

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   256

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   257

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   258

   259

/* PCI Tuning Parameters

   260

   Threshold is bytes transferred to chip before transmission starts. */

   261

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   262

   263

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   264

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   265

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   266

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   267

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   268

   269

/* Operational parameters that usually are not changed. */

   270

/* Time in jiffies before concluding the transmitter is hung. */

   271

#define TX_TIMEOUT  (6*HZ)

   272

   273

   274

enum {

   275

	HAS_MII_XCVR = 0x010000,

   276

	HAS_CHIP_XCVR = 0x020000,

   277

	HAS_LNK_CHNG = 0x040000,

   278

};

   279

   280

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   281

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   282

#define RTL_MIN_IO_SIZE 0x80

   283

#define RTL8139B_IO_SIZE 256

   284

   285

#define RTL8129_CAPS	HAS_MII_XCVR

   286

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   287

   288

typedef enum {

   289

	RTL8139 = 0,

   290

	RTL8129,

   291

} board_t;

   292

   293

   294

/* indexed by board_t, above */

   295

static struct {

   296

	const char *name;

   297

	u32 hw_flags;

   298

} board_info[] __devinitdata = {

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	{ "RealTek RTL8139", RTL8139_CAPS },

   300

	{ "RealTek RTL8129", RTL8129_CAPS },

   301

};

   302

   303

   304

static struct pci_device_id rtl8139_pci_tbl[] = {

   305

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   306

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   308

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   309

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   310

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   311

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   312

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   313

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   314

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   315

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   316

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   317

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   318

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   319

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   320

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   321

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   322

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   323

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 

   324

   325

#ifdef CONFIG_SH_SECUREEDGE5410

   326

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

   329

#ifdef CONFIG_8139TOO_8129

   330

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   331

#endif

   332

   333

	/* some crazy cards report invalid vendor ids like

   334

	 * 0x0001 here.  The other ids are valid and constant,

   335

	 * so we simply don't match on the main vendor id.

   336

	 */

   337

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   338

	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   339

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   340

   341

	{0,}

   342

};

   343

   344

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   345

   346

//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   347

   348

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   349

   350

static struct {

   351

	const char str[ETH_GSTRING_LEN];

   352

} ethtool_stats_keys[] = {

   353

	{ "early_rx" },

   354

	{ "tx_buf_mapped" },

   355

	{ "tx_timeouts" },

   356

	{ "rx_lost_in_ring" },

   357

};

   358

   359

/* The rest of these values should never change. */

   360

   361

/* Symbolic offsets to registers. */

   362

enum RTL8139_registers {

   363

	MAC0 = 0,		/* Ethernet hardware address. */

   364

	MAR0 = 8,		/* Multicast filter. */

   365

	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   366

	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   367

	RxBuf = 0x30,

   368

	ChipCmd = 0x37,

   369

	RxBufPtr = 0x38,

   370

	RxBufAddr = 0x3A,

   371

	IntrMask = 0x3C,

   372

	IntrStatus = 0x3E,

   373

	TxConfig = 0x40,

   374

	RxConfig = 0x44,

   375

	Timer = 0x48,		/* A general-purpose counter. */

   376

	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   377

	Cfg9346 = 0x50,

   378

	Config0 = 0x51,

   379

	Config1 = 0x52,

   380

	FlashReg = 0x54,

   381

	MediaStatus = 0x58,

   382

	Config3 = 0x59,

   383

	Config4 = 0x5A,		/* absent on RTL-8139A */

   384

	HltClk = 0x5B,

   385

	MultiIntr = 0x5C,

   386

	TxSummary = 0x60,

   387

	BasicModeCtrl = 0x62,

   388

	BasicModeStatus = 0x64,

   389

	NWayAdvert = 0x66,

   390

	NWayLPAR = 0x68,

   391

	NWayExpansion = 0x6A,

   392

	/* Undocumented registers, but required for proper operation. */

   393

	FIFOTMS = 0x70,		/* FIFO Control and test. */

   394

	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   395

	PARA78 = 0x78,

   396

	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   397

	Config5 = 0xD8,		/* absent on RTL-8139A */

   398

};

   399

   400

enum ClearBitMasks {

   401

	MultiIntrClear = 0xF000,

   402

	ChipCmdClear = 0xE2,

   403

	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   404

};

   405

   406

enum ChipCmdBits {

   407

	CmdReset = 0x10,

   408

	CmdRxEnb = 0x08,

   409

	CmdTxEnb = 0x04,

   410

	RxBufEmpty = 0x01,

   411

};

   412

   413

/* Interrupt register bits, using my own meaningful names. */

   414

enum IntrStatusBits {

   415

	PCIErr = 0x8000,

   416

	PCSTimeout = 0x4000,

   417

	RxFIFOOver = 0x40,

   418

	RxUnderrun = 0x20,

   419

	RxOverflow = 0x10,

   420

	TxErr = 0x08,

   421

	TxOK = 0x04,

   422

	RxErr = 0x02,

   423

	RxOK = 0x01,

   424

   425

	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   426

};

   427

   428

enum TxStatusBits {

   429

	TxHostOwns = 0x2000,

   430

	TxUnderrun = 0x4000,

   431

	TxStatOK = 0x8000,

   432

	TxOutOfWindow = 0x20000000,

   433

	TxAborted = 0x40000000,

   434

	TxCarrierLost = 0x80000000,

   435

};

   436

enum RxStatusBits {

   437

	RxMulticast = 0x8000,

   438

	RxPhysical = 0x4000,

   439

	RxBroadcast = 0x2000,

   440

	RxBadSymbol = 0x0020,

   441

	RxRunt = 0x0010,

   442

	RxTooLong = 0x0008,

   443

	RxCRCErr = 0x0004,

   444

	RxBadAlign = 0x0002,

   445

	RxStatusOK = 0x0001,

   446

};

   447

   448

/* Bits in RxConfig. */

   449

enum rx_mode_bits {

   450

	AcceptErr = 0x20,

   451

	AcceptRunt = 0x10,

   452

	AcceptBroadcast = 0x08,

   453

	AcceptMulticast = 0x04,

   454

	AcceptMyPhys = 0x02,

   455

	AcceptAllPhys = 0x01,

   456

};

   457

   458

/* Bits in TxConfig. */

   459

enum tx_config_bits {

   460

   461

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   462

        TxIFGShift = 24,

   463

        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   464

        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   465

        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   466

        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   467

   468

	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   469

	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   470

	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   471

	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   472

	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   473

   474

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   475

};

   476

   477

/* Bits in Config1 */

   478

enum Config1Bits {

   479

	Cfg1_PM_Enable = 0x01,

   480

	Cfg1_VPD_Enable = 0x02,

   481

	Cfg1_PIO = 0x04,

   482

	Cfg1_MMIO = 0x08,

   483

	LWAKE = 0x10,		/* not on 8139, 8139A */

   484

	Cfg1_Driver_Load = 0x20,

   485

	Cfg1_LED0 = 0x40,

   486

	Cfg1_LED1 = 0x80,

   487

	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   488

	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   489

};

   490

   491

/* Bits in Config3 */

   492

enum Config3Bits {

   493

	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   494

	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   495

	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   496

	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   497

	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   498

	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   499

	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   500

	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   501

};

   502

   503

/* Bits in Config4 */

   504

enum Config4Bits {

   505

	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   506

};

   507

   508

/* Bits in Config5 */

   509

enum Config5Bits {

   510

	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   511

	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   512

	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   513

	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   514

	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   515

	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   516

	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   517

};

   518

   519

enum RxConfigBits {

   520

	/* rx fifo threshold */

   521

	RxCfgFIFOShift = 13,

   522

	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   523

   524

	/* Max DMA burst */