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/******************************************************************************

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 *

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 *  $Id$

     4

 *

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 *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it

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 *  and/or modify it under the terms of the GNU General Public License

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 *  as published by the Free Software Foundation; version 2 of the License.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be

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 *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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 *  GNU General Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License

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 *  along with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

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 *****************************************************************************/

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    24

/**

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   \file

    26

   EtherCAT driver for RTL8139-compatible NICs.

    27

*/

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/*****************************************************************************/

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    31

/*

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  Former documentation:

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    34

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    35

    36

	Maintained by Jeff Garzik <jgarzik@pobox.com>

    37

	Copyright 2000-2002 Jeff Garzik

    38

    39

	Much code comes from Donald Becker's rtl8139.c driver,

    40

	versions 1.13 and older.  This driver was originally based

    41

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    42

    43

	-----<snip>-----

    44

    45

        	Written 1997-2001 by Donald Becker.

    46

		This software may be used and distributed according to the

    47

		terms of the GNU General Public License (GPL), incorporated

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		herein by reference.  Drivers based on or derived from this

    49

		code fall under the GPL and must retain the authorship,

    50

		copyright and license notice.  This file is not a complete

    51

		program and may only be used when the entire operating

    52

		system is licensed under the GPL.

    53

    54

		This driver is for boards based on the RTL8129 and RTL8139

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		PCI ethernet chips.

    56

    57

		The author may be reached as becker@scyld.com, or C/O Scyld

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		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    59

		MD 21403

    60

    61

		Support and updates available at

    62

		http://www.scyld.com/network/rtl8139.html

    63

    64

		Twister-tuning table provided by Kinston

    65

		<shangh@realtek.com.tw>.

    66

    67

	-----<snip>-----

    68

    69

	This software may be used and distributed according to the terms

    70

	of the GNU General Public License, incorporated herein by reference.

    71

    72

	Contributors:

    73

    74

		Donald Becker - he wrote the original driver, kudos to him!

    75

		(but please don't e-mail him for support, this isn't his driver)

    76

    77

		Tigran Aivazian - bug fixes, skbuff free cleanup

    78

    79

		Martin Mares - suggestions for PCI cleanup

    80

    81

		David S. Miller - PCI DMA and softnet updates

    82

    83

		Ernst Gill - fixes ported from BSD driver

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    85

		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

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		Gerard Sharp - bug fix, testing and feedback

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    90

		David Ford - Rx ring wrap fix

    91

    92

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    93

		to find and fix a crucial bug on older chipsets.

    94

    95

		Donald Becker/Chris Butterworth/Marcus Westergren -

    96

		Noticed various Rx packet size-related buglets.

    97

    98

		Santiago Garcia Mantinan - testing and feedback

    99

   100

		Jens David - 2.2.x kernel backports

   101

   102

		Martin Dennett - incredibly helpful insight on undocumented

   103

		features of the 8139 chips

   104

   105

		Jean-Jacques Michel - bug fix

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   107

		Tobias Ringström - Rx interrupt status checking suggestion

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   109

		Andrew Morton - Clear blocked signals, avoid

   110

		buffer overrun setting current->comm.

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   112

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

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   118

		"rtl8139-diag -mmmaaavvveefN" output

   119

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   120

   121

*/

   122

   123

#define DRV_NAME	"ec_8139too"

   124

#define DRV_VERSION	"0.9.27"

   125

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#include <linux/config.h>

   127

#include <linux/module.h>

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#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

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#include <linux/init.h>

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#include <linux/ioport.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/rtnetlink.h>

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#include <linux/delay.h>

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#include <linux/ethtool.h>

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#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

   141

#include <asm/io.h>

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#include <asm/uaccess.h>

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#include <asm/irq.h>

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   145

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

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   147

#include "ecdev.h"

   148

   149

#define LIT(X) #X

   150

#define STR(X) LIT(X)

   151

   152

#define COMPILE_INFO "Revision " STR(EC_REV) \

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                     ", compiled by " STR(EC_USER) \

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                     " at " __DATE__ " " __TIME__

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/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   157

   158

#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   159

#define PFX DRV_NAME ": "

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   161

/* Default Message level */

   162

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   163

                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   165

   166

   167

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

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#ifdef CONFIG_8139TOO_PIO

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#define USE_IO_OPS 1

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#endif

   171

   172

/* define to 1, 2 or 3 to enable copious debugging info */

   173

#define RTL8139_DEBUG 0

   174

   175

/* define to 1 to disable lightweight runtime debugging checks */

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#undef RTL8139_NDEBUG

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   178

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#if RTL8139_DEBUG

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/* note: prints function name for you */

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#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

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#else

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#  define DPRINTK(fmt, args...)

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#endif

   185

   186

#ifdef RTL8139_NDEBUG

   187

#  define assert(expr) do {} while (0)

   188

#else

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#  define assert(expr) \

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        if(unlikely(!(expr))) {				        \

   191

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

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        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

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        }

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#endif

   195

   196

   197

/* A few user-configurable values. */

   198

/* media options */

   199

#define MAX_UNITS 8

   200

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   201

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   202

   203

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

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   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

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static int multicast_filter_limit = 32;

   206

   207

/* bitmapped message enable number */

   208

static int debug = -1;

   209

   210

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   211

   212

static int ec_device_index = -1;

   213

static int ec_device_master_index = 0;

   214

static ec_device_t *rtl_ec_dev;

   215

struct net_device *rtl_ec_net_dev = NULL;

   216

   217

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   218

   219

/*

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 * Receive ring size 

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 * Warning: 64K ring has hardware issues and may lock up.

   222

 */

   223

#if defined(CONFIG_SH_DREAMCAST)

   224

#define RX_BUF_IDX	1	/* 16K ring */

   225

#else

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#define RX_BUF_IDX	2	/* 32K ring */

   227

#endif

   228

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   229

#define RX_BUF_PAD	16

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#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   231

   232

#if RX_BUF_LEN == 65536

   233

#define RX_BUF_TOT_LEN	RX_BUF_LEN

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#else

   235

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   236

#endif

   237

   238

/* Number of Tx descriptor registers. */

   239

#define NUM_TX_DESC	4

   240

   241

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   242

#define MAX_ETH_FRAME_SIZE	1536

   243

   244

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   245

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   246

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   247

   248

/* PCI Tuning Parameters

   249

   Threshold is bytes transferred to chip before transmission starts. */

   250

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   251

   252

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   253

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   254

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   255

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   256

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   257

   258

/* Operational parameters that usually are not changed. */

   259

/* Time in jiffies before concluding the transmitter is hung. */

   260

#define TX_TIMEOUT  (6*HZ)

   261

   262

   263

enum {

   264

	HAS_MII_XCVR = 0x010000,

   265

	HAS_CHIP_XCVR = 0x020000,

   266

	HAS_LNK_CHNG = 0x040000,

   267

};

   268

   269

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   270

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   271

#define RTL_MIN_IO_SIZE 0x80

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#define RTL8139B_IO_SIZE 256

   273

   274

#define RTL8129_CAPS	HAS_MII_XCVR

   275

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   276

   277

typedef enum {

   278

	RTL8139 = 0,

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	RTL8129,

   280

} board_t;

   281

   282

   283

/* indexed by board_t, above */

   284

static struct {

   285

	const char *name;

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	u32 hw_flags;

   287

} board_info[] __devinitdata = {

   288

	{ "RealTek RTL8139", RTL8139_CAPS },

   289

	{ "RealTek RTL8129", RTL8129_CAPS },

   290

};

   291

   292

   293

static struct pci_device_id rtl8139_pci_tbl[] = {

   294

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   302

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   305

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   308

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   310

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   311

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   312

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 

   313

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#ifdef CONFIG_SH_SECUREEDGE5410

   315

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   316

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

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#ifdef CONFIG_8139TOO_8129

   319

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   320

#endif

   321

   322

	/* some crazy cards report invalid vendor ids like

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	 * 0x0001 here.  The other ids are valid and constant,

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	 * so we simply don't match on the main vendor id.

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	 */

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	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   328

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   329

   330

	{0,}

   331

};

   338

   339

static struct {

   340

	const char str[ETH_GSTRING_LEN];

   341

} ethtool_stats_keys[] = {

   342

	{ "early_rx" },

   343

	{ "tx_buf_mapped" },

   344

	{ "tx_timeouts" },

   345

	{ "rx_lost_in_ring" },

   346

};

   347

   348

/* The rest of these values should never change. */

   349

   350

/* Symbolic offsets to registers. */

   351

enum RTL8139_registers {

   352

	MAC0 = 0,		/* Ethernet hardware address. */

   353

	MAR0 = 8,		/* Multicast filter. */

   354

	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   355

	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   356

	RxBuf = 0x30,

   357

	ChipCmd = 0x37,

   358

	RxBufPtr = 0x38,

   359

	RxBufAddr = 0x3A,

   360

	IntrMask = 0x3C,

   361

	IntrStatus = 0x3E,

   362

	TxConfig = 0x40,

   363

	RxConfig = 0x44,

   364

	Timer = 0x48,		/* A general-purpose counter. */

   365

	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   366

	Cfg9346 = 0x50,

   367

	Config0 = 0x51,

   368

	Config1 = 0x52,

   369

	FlashReg = 0x54,

   370

	MediaStatus = 0x58,

   371

	Config3 = 0x59,

   372

	Config4 = 0x5A,		/* absent on RTL-8139A */

   373

	HltClk = 0x5B,

   374

	MultiIntr = 0x5C,

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	TxSummary = 0x60,

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	BasicModeCtrl = 0x62,

   377

	BasicModeStatus = 0x64,

   378

	NWayAdvert = 0x66,

   379

	NWayLPAR = 0x68,

   380

	NWayExpansion = 0x6A,

   381

	/* Undocumented registers, but required for proper operation. */

   382

	FIFOTMS = 0x70,		/* FIFO Control and test. */

   383

	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   384

	PARA78 = 0x78,

   385

	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   386

	Config5 = 0xD8,		/* absent on RTL-8139A */

   387

};

   388

   389

enum ClearBitMasks {

   390

	MultiIntrClear = 0xF000,

   391

	ChipCmdClear = 0xE2,

   392

	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   393

};

   394

   395

enum ChipCmdBits {

   396

	CmdReset = 0x10,

   397

	CmdRxEnb = 0x08,

   398

	CmdTxEnb = 0x04,

   399

	RxBufEmpty = 0x01,

   400

};

   401

   402

/* Interrupt register bits, using my own meaningful names. */

   403

enum IntrStatusBits {

   404

	PCIErr = 0x8000,

   405

	PCSTimeout = 0x4000,

   406

	RxFIFOOver = 0x40,

   407

	RxUnderrun = 0x20,

   408

	RxOverflow = 0x10,

   409

	TxErr = 0x08,

   410

	TxOK = 0x04,

   411

	RxErr = 0x02,

   412

	RxOK = 0x01,

   413

   414

	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   415

};

   416

   417

enum TxStatusBits {

   418

	TxHostOwns = 0x2000,

   419

	TxUnderrun = 0x4000,

   420

	TxStatOK = 0x8000,

   421

	TxOutOfWindow = 0x20000000,

   422

	TxAborted = 0x40000000,

   423

	TxCarrierLost = 0x80000000,

   424

};

   425

enum RxStatusBits {

   426

	RxMulticast = 0x8000,

   427

	RxPhysical = 0x4000,

   428

	RxBroadcast = 0x2000,

   429

	RxBadSymbol = 0x0020,

   430

	RxRunt = 0x0010,

   431

	RxTooLong = 0x0008,

   432

	RxCRCErr = 0x0004,

   433

	RxBadAlign = 0x0002,

   434

	RxStatusOK = 0x0001,

   435

};

   436

   437

/* Bits in RxConfig. */

   438

enum rx_mode_bits {

   439

	AcceptErr = 0x20,

   440

	AcceptRunt = 0x10,

   441

	AcceptBroadcast = 0x08,

   442

	AcceptMulticast = 0x04,

   443

	AcceptMyPhys = 0x02,

   444

	AcceptAllPhys = 0x01,

   445

};

   446

   447

/* Bits in TxConfig. */

   448

enum tx_config_bits {

   449

   450

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   451

        TxIFGShift = 24,

   452

        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   453

        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   454

        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   455

        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   456

   457

	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   458

	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   459

	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   460

	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   461

	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   462

   463

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   464

};

   465

   466

/* Bits in Config1 */

   467

enum Config1Bits {

   468

	Cfg1_PM_Enable = 0x01,

   469

	Cfg1_VPD_Enable = 0x02,

   470

	Cfg1_PIO = 0x04,

   471

	Cfg1_MMIO = 0x08,

   472

	LWAKE = 0x10,		/* not on 8139, 8139A */

   473

	Cfg1_Driver_Load = 0x20,

   474

	Cfg1_LED0 = 0x40,

   475

	Cfg1_LED1 = 0x80,

   476

	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   477

	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   478

};

   479

   480

/* Bits in Config3 */

   481

enum Config3Bits {

   482

	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   483

	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   484

	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   485

	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   486

	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   487

	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   488

	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   489

	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   490

};

   491

   492

/* Bits in Config4 */

   493

enum Config4Bits {

   494

	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   495

};

   496

   497

/* Bits in Config5 */

   498

enum Config5Bits {

   499

	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   500

	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   501

	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   502

	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   503

	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   504

	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   505

	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   506

};

   507

   508

enum RxConfigBits {

   509

	/* rx fifo threshold */

   510

	RxCfgFIFOShift = 13,

   511

	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   512

   513

	/* Max DMA burst */

   514

	RxCfgDMAShift = 8,

   515

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   516

   517

	/* rx ring buffer length */

   518

	RxCfgRcv8K = 0,

   519

	RxCfgRcv16K = (1 << 11),

   520

	RxCfgRcv32K = (1 << 12),

   521

	RxCfgRcv64K = (1 << 11) | (1 << 12),

   522

   523

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   524

	RxNoWrap = (1 << 7),

   525

};