1

/******************************************************************************

     2

 *

     3

 *  drv_8139too.c

     4

 *

     5

 *  EtherCAT-Treiber für RTL8139-kompatible Netzwerkkarten.

     6

 *

     7

 *  Autoren: Wilhelm Hagemeister, Florian Pose

     8

 *

     9

 *  $Date: 2005-11-18 11:30:01 +0100 (Fre, 18 Nov 2005) $

    10

 *  $Author: fp $

    11

 *

    12

 *  (C) Copyright IgH 2005

    13

 *  Ingenieurgemeinschaft IgH

    14

 *  Heinz-Bäcker Str. 34

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 *  D-45356 Essen

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 *  Tel.: +49 201/61 99 31

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 *  Fax.: +49 201/61 98 36

    18

 *  E-mail: sp@igh-essen.com

    19

 *

    20

 ******************************************************************************/

    21

    22

/*

    23

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    24

    25

	Maintained by Jeff Garzik <jgarzik@pobox.com>

    26

	Copyright 2000-2002 Jeff Garzik

    27

    28

	Much code comes from Donald Becker's rtl8139.c driver,

    29

	versions 1.13 and older.  This driver was originally based

    30

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    31

    32

	-----<snip>-----

    33

    34

        	Written 1997-2001 by Donald Becker.

    35

		This software may be used and distributed according to the

    36

		terms of the GNU General Public License (GPL), incorporated

    37

		herein by reference.  Drivers based on or derived from this

    38

		code fall under the GPL and must retain the authorship,

    39

		copyright and license notice.  This file is not a complete

    40

		program and may only be used when the entire operating

    41

		system is licensed under the GPL.

    42

    43

		This driver is for boards based on the RTL8129 and RTL8139

    44

		PCI ethernet chips.

    45

    46

		The author may be reached as becker@scyld.com, or C/O Scyld

    47

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    48

		MD 21403

    49

    50

		Support and updates available at

    51

		http://www.scyld.com/network/rtl8139.html

    52

    53

		Twister-tuning table provided by Kinston

    54

		<shangh@realtek.com.tw>.

    55

    56

	-----<snip>-----

    57

    58

	This software may be used and distributed according to the terms

    59

	of the GNU General Public License, incorporated herein by reference.

    60

    61

	Contributors:

    62

    63

		Donald Becker - he wrote the original driver, kudos to him!

    64

		(but please don't e-mail him for support, this isn't his driver)

    65

    66

		Tigran Aivazian - bug fixes, skbuff free cleanup

    67

    68

		Martin Mares - suggestions for PCI cleanup

    69

    70

		David S. Miller - PCI DMA and softnet updates

    71

    72

		Ernst Gill - fixes ported from BSD driver

    73

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		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

    76

    77

		Gerard Sharp - bug fix, testing and feedback

    78

    79

		David Ford - Rx ring wrap fix

    80

    81

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    82

		to find and fix a crucial bug on older chipsets.

    83

    84

		Donald Becker/Chris Butterworth/Marcus Westergren -

    85

		Noticed various Rx packet size-related buglets.

    86

    87

		Santiago Garcia Mantinan - testing and feedback

    88

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		Jens David - 2.2.x kernel backports

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		Martin Dennett - incredibly helpful insight on undocumented

    92

		features of the 8139 chips

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		Jean-Jacques Michel - bug fix

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		Tobias Ringström - Rx interrupt status checking suggestion

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		Andrew Morton - Clear blocked signals, avoid

    99

		buffer overrun setting current->comm.

   100

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		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   102

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		Robert Kuebel - Save kernel thread from dying on any signal.

   104

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	Submitting bug reports:

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		"rtl8139-diag -mmmaaavvveefN" output

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		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   109

   110

*/

   111

   113

#define DRV_VERSION	"0.9.27"

   114

   115

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#include <linux/config.h>

   117

#include <linux/module.h>

   118

#include <linux/kernel.h>

   119

#include <linux/compiler.h>

   120

#include <linux/pci.h>

   121

#include <linux/init.h>

   122

#include <linux/ioport.h>

   123

#include <linux/netdevice.h>

   124

#include <linux/etherdevice.h>

   125

#include <linux/rtnetlink.h>

   126

#include <linux/delay.h>

   127

#include <linux/ethtool.h>

   128

#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

   131

#include <asm/io.h>

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#include <asm/uaccess.h>

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#include <asm/irq.h>

   134

   135

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   136

   137

#include "ec_device.h"

   138

//#include "ec_dbg.h"

   139

   140

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   141

   142

#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   143

#define PFX DRV_NAME ": "

   144

   145

/* Default Message level */

   146

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

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                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   149

   150

   151

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   152

#ifdef CONFIG_8139TOO_PIO

   153

#define USE_IO_OPS 1

   154

#endif

   155

   156

/* define to 1, 2 or 3 to enable copious debugging info */

   157

#define RTL8139_DEBUG 0

   158

   159

/* define to 1 to disable lightweight runtime debugging checks */

   160

#undef RTL8139_NDEBUG

   161

   162

   163

#if RTL8139_DEBUG

   164

/* note: prints function name for you */

   165

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   166

#else

   167

#  define DPRINTK(fmt, args...)

   168

#endif

   169

   170

#ifdef RTL8139_NDEBUG

   171

#  define assert(expr) do {} while (0)

   172

#else

   173

#  define assert(expr) \

   174

        if(unlikely(!(expr))) {				        \

   175

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   176

        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   177

        }

   178

#endif

   179

   180

   181

/* A few user-configurable values. */

   182

/* media options */

   183

#define MAX_UNITS 8

   184

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   185

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   186

   187

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   188

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   189

static int multicast_filter_limit = 32;

   190

   191

/* bitmapped message enable number */

   192

static int debug = -1;

   193

   194

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   195

   196

// Device index for EtherCAT device selection

   197

static int ec_device_index = -1;

   198

   199

//#define ECAT_DEBUG

   200

   201

EtherCAT_device_t rtl_ecat_dev;

   202

   205

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   206

   207

/*

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 * Receive ring size 

   209

 * Warning: 64K ring has hardware issues and may lock up.

   210

 */

   211

#if defined(CONFIG_SH_DREAMCAST)

   212

#define RX_BUF_IDX	1	/* 16K ring */

   213

#else

   214

#define RX_BUF_IDX	2	/* 32K ring */

   215

#endif

   216

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   217

#define RX_BUF_PAD	16

   218

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   219

   220

#if RX_BUF_LEN == 65536

   221

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   222

#else

   223

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   224

#endif

   225

   226

/* Number of Tx descriptor registers. */

   227

#define NUM_TX_DESC	4

   228

   229

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   230

#define MAX_ETH_FRAME_SIZE	1536

   231

   232

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   233

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   234

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   235

   236

/* PCI Tuning Parameters

   237

   Threshold is bytes transferred to chip before transmission starts. */

   238

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   239

   240

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   241

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   242

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   243

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   244

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   245

   246

/* Operational parameters that usually are not changed. */

   247

/* Time in jiffies before concluding the transmitter is hung. */

   248

#define TX_TIMEOUT  (6*HZ)

   249

   250

   251

enum {

   252

	HAS_MII_XCVR = 0x010000,

   253

	HAS_CHIP_XCVR = 0x020000,

   254

	HAS_LNK_CHNG = 0x040000,

   255

};

   256

   257

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   258

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   259

#define RTL_MIN_IO_SIZE 0x80

   260

#define RTL8139B_IO_SIZE 256

   261

   262

#define RTL8129_CAPS	HAS_MII_XCVR

   263

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   264

   265

typedef enum {

   266

	RTL8139 = 0,

   267

	RTL8129,

   268

} board_t;

   269

   270

   271

/* indexed by board_t, above */

   272

static struct {

   273

	const char *name;

   274

	u32 hw_flags;

   275

} board_info[] __devinitdata = {

   276

	{ "RealTek RTL8139", RTL8139_CAPS },

   277

	{ "RealTek RTL8129", RTL8129_CAPS },

   278

};

   279

   280

   281

static struct pci_device_id rtl8139_pci_tbl[] = {

   282

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   283

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   285

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 

   301

   302

#ifdef CONFIG_SH_SECUREEDGE5410

   303

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

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#ifdef CONFIG_8139TOO_8129

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   308

#endif

   309

   310

	/* some crazy cards report invalid vendor ids like

   311

	 * 0x0001 here.  The other ids are valid and constant,

   312

	 * so we simply don't match on the main vendor id.

   313

	 */

   314

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   315

	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   316

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   317

   318

	{0,}

   319

};

   320

MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   321

   322

static struct {

   323

	const char str[ETH_GSTRING_LEN];

   324

} ethtool_stats_keys[] = {

   325

	{ "early_rx" },

   326

	{ "tx_buf_mapped" },

   327

	{ "tx_timeouts" },

   328

	{ "rx_lost_in_ring" },

   329

};

   330

   331

/* The rest of these values should never change. */

   332

   333

/* Symbolic offsets to registers. */

   334

enum RTL8139_registers {

   335

	MAC0 = 0,		/* Ethernet hardware address. */

   336

	MAR0 = 8,		/* Multicast filter. */

   337

	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   338

	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   339

	RxBuf = 0x30,

   340

	ChipCmd = 0x37,

   341

	RxBufPtr = 0x38,

   342

	RxBufAddr = 0x3A,

   343

	IntrMask = 0x3C,

   344

	IntrStatus = 0x3E,

   345

	TxConfig = 0x40,

   346

	RxConfig = 0x44,

   347

	Timer = 0x48,		/* A general-purpose counter. */

   348

	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   349

	Cfg9346 = 0x50,

   350

	Config0 = 0x51,

   351

	Config1 = 0x52,

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	FlashReg = 0x54,

   353

	MediaStatus = 0x58,

   354

	Config3 = 0x59,

   355

	Config4 = 0x5A,		/* absent on RTL-8139A */

   356

	HltClk = 0x5B,

   357

	MultiIntr = 0x5C,

   358

	TxSummary = 0x60,

   359

	BasicModeCtrl = 0x62,

   360

	BasicModeStatus = 0x64,

   361

	NWayAdvert = 0x66,

   362

	NWayLPAR = 0x68,

   363

	NWayExpansion = 0x6A,

   364

	/* Undocumented registers, but required for proper operation. */

   365

	FIFOTMS = 0x70,		/* FIFO Control and test. */

   366

	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   367

	PARA78 = 0x78,

   368

	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   369

	Config5 = 0xD8,		/* absent on RTL-8139A */

   370

};

   371

   372

enum ClearBitMasks {

   373

	MultiIntrClear = 0xF000,

   374

	ChipCmdClear = 0xE2,

   375

	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   376

};

   377

   378

enum ChipCmdBits {

   379

	CmdReset = 0x10,

   380

	CmdRxEnb = 0x08,

   381

	CmdTxEnb = 0x04,

   382

	RxBufEmpty = 0x01,

   383

};

   384

   385

/* Interrupt register bits, using my own meaningful names. */

   386

enum IntrStatusBits {

   387

	PCIErr = 0x8000,

   388

	PCSTimeout = 0x4000,

   389

	RxFIFOOver = 0x40,

   390

	RxUnderrun = 0x20,

   391

	RxOverflow = 0x10,

   392

	TxErr = 0x08,

   393

	TxOK = 0x04,

   394

	RxErr = 0x02,

   395

	RxOK = 0x01,

   396

   397

	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   398

};

   399

   400

enum TxStatusBits {

   401

	TxHostOwns = 0x2000,

   402

	TxUnderrun = 0x4000,

   403

	TxStatOK = 0x8000,

   404

	TxOutOfWindow = 0x20000000,

   405

	TxAborted = 0x40000000,

   406

	TxCarrierLost = 0x80000000,

   407

};

   408

enum RxStatusBits {

   409

	RxMulticast = 0x8000,

   410

	RxPhysical = 0x4000,

   411

	RxBroadcast = 0x2000,

   412

	RxBadSymbol = 0x0020,

   413

	RxRunt = 0x0010,

   414

	RxTooLong = 0x0008,

   415

	RxCRCErr = 0x0004,

   416

	RxBadAlign = 0x0002,

   417

	RxStatusOK = 0x0001,

   418

};

   419

   420

/* Bits in RxConfig. */

   421

enum rx_mode_bits {

   422

	AcceptErr = 0x20,

   423

	AcceptRunt = 0x10,

   424

	AcceptBroadcast = 0x08,

   425

	AcceptMulticast = 0x04,

   426

	AcceptMyPhys = 0x02,

   427

	AcceptAllPhys = 0x01,

   428

};

   429

   430

/* Bits in TxConfig. */

   431

enum tx_config_bits {

   432

   433

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   434

        TxIFGShift = 24,

   435

        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   436

        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   437

        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   438

        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   439

   440

	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   441

	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   442

	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   443

	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   444

	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   445

   446

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   447

};

   448

   449

/* Bits in Config1 */

   450

enum Config1Bits {

   451

	Cfg1_PM_Enable = 0x01,

   452

	Cfg1_VPD_Enable = 0x02,

   453

	Cfg1_PIO = 0x04,

   454

	Cfg1_MMIO = 0x08,

   455

	LWAKE = 0x10,		/* not on 8139, 8139A */

   456

	Cfg1_Driver_Load = 0x20,

   457

	Cfg1_LED0 = 0x40,

   458

	Cfg1_LED1 = 0x80,

   459

	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   460

	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   461

};

   462

   463

/* Bits in Config3 */

   464

enum Config3Bits {

   465

	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   466

	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   467

	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   468

	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   469

	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   470

	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   471

	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   472

	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   473

};

   474

   475

/* Bits in Config4 */

   476

enum Config4Bits {

   477

	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   478

};

   479

   480

/* Bits in Config5 */

   481

enum Config5Bits {

   482

	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   483

	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   484

	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   485

	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   486

	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   487

	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   488

	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   489

};

   490

   491

enum RxConfigBits {

   492

	/* rx fifo threshold */

   493

	RxCfgFIFOShift = 13,

   494

	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   495

   496

	/* Max DMA burst */

   497

	RxCfgDMAShift = 8,

   498

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   499

   500

	/* rx ring buffer length */

   501

	RxCfgRcv8K = 0,

   502

	RxCfgRcv16K = (1 << 11),

   503

	RxCfgRcv32K = (1 << 12),

   504

	RxCfgRcv64K = (1 << 11) | (1 << 12),

   505

   506

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   507

	RxNoWrap = (1 << 7),

   508

};

   509

   510

/* Twister tuning parameters from RealTek.

   511

   Completely undocumented, but required to tune bad links on some boards. */

   512

enum CSCRBits {

   513

	CSCR_LinkOKBit = 0x0400,

   514

	CSCR_LinkChangeBit = 0x0800,

   515

	CSCR_LinkStatusBits = 0x0f000,

   516

	CSCR_LinkDownOffCmd = 0x003c0,

   517

	CSCR_LinkDownCmd = 0x0f3c0,

   518

};

   519

   520

enum Cfg9346Bits {

   521

	Cfg9346_Lock = 0x00,

   522

	Cfg9346_Unlock = 0xC0,

   523

};

   524

   525

typedef enum {

   526

	CH_8139 = 0,

   527

	CH_8139_K,

   528

	CH_8139A,

   529

	CH_8139A_G,