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/******************************************************************************

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 *

     3

 *  $Id$

     4

 *

     5

 *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it

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 *  and/or modify it under the terms of the GNU General Public License

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 *  as published by the Free Software Foundation; either version 2 of the

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 *  License, or (at your option) any later version.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be

    15

 *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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 *  GNU General Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License

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 *  along with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

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 *  The right to use EtherCAT Technology is granted and comes free of

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 *  charge under condition of compatibility of product made by

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 *  Licensee. People intending to distribute/sell products based on the

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 *  code, have to sign an agreement to guarantee that products using

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 *  software based on IgH EtherCAT master stay compatible with the actual

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 *  EtherCAT specification (which are released themselves as an open

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 *  standard) as the (only) precondition to have the right to use EtherCAT

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 *  Technology, IP and trade marks.

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 *

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 *****************************************************************************/

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    34

/**

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   \file

    36

   EtherCAT driver for RTL8139-compatible NICs.

    37

*/

    38

    39

/*****************************************************************************/

    40

    41

/*

    42

  Former documentation:

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    44

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    45

    46

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

    48

    49

	Much code comes from Donald Becker's rtl8139.c driver,

    50

	versions 1.13 and older.  This driver was originally based

    51

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    52

    53

	-----<snip>-----

    54

    55

        	Written 1997-2001 by Donald Becker.

    56

		This software may be used and distributed according to the

    57

		terms of the GNU General Public License (GPL), incorporated

    58

		herein by reference.  Drivers based on or derived from this

    59

		code fall under the GPL and must retain the authorship,

    60

		copyright and license notice.  This file is not a complete

    61

		program and may only be used when the entire operating

    62

		system is licensed under the GPL.

    63

    64

		This driver is for boards based on the RTL8129 and RTL8139

    65

		PCI ethernet chips.

    66

    67

		The author may be reached as becker@scyld.com, or C/O Scyld

    68

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    69

		MD 21403

    70

    71

		Support and updates available at

    72

		http://www.scyld.com/network/rtl8139.html

    73

    74

		Twister-tuning table provided by Kinston

    75

		<shangh@realtek.com.tw>.

    76

    77

	-----<snip>-----

    78

    79

	This software may be used and distributed according to the terms

    80

	of the GNU General Public License, incorporated herein by reference.

    81

    82

	Contributors:

    83

    84

		Donald Becker - he wrote the original driver, kudos to him!

    85

		(but please don't e-mail him for support, this isn't his driver)

    86

    87

		Tigran Aivazian - bug fixes, skbuff free cleanup

    88

    89

		Martin Mares - suggestions for PCI cleanup

    90

    91

		David S. Miller - PCI DMA and softnet updates

    92

    93

		Ernst Gill - fixes ported from BSD driver

    94

    95

		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

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    98

		Gerard Sharp - bug fix, testing and feedback

    99

   100

		David Ford - Rx ring wrap fix

   101

   102

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

   103

		to find and fix a crucial bug on older chipsets.

   104

   105

		Donald Becker/Chris Butterworth/Marcus Westergren -

   106

		Noticed various Rx packet size-related buglets.

   107

   108

		Santiago Garcia Mantinan - testing and feedback

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   110

		Jens David - 2.2.x kernel backports

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   112

		Martin Dennett - incredibly helpful insight on undocumented

   113

		features of the 8139 chips

   114

   115

		Jean-Jacques Michel - bug fix

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   117

		Tobias Ringström - Rx interrupt status checking suggestion

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   119

		Andrew Morton - Clear blocked signals, avoid

   120

		buffer overrun setting current->comm.

   121

   122

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   123

   124

		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

   127

   128

		"rtl8139-diag -mmmaaavvveefN" output

   129

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   130

   131

*/

   132

   133

#define DRV_NAME	"ec_8139too"

   134

#define DRV_VERSION	"0.9.27"

   135

   136

   137

#include <linux/config.h>

   138

#include <linux/module.h>

   139

#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

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#include <linux/init.h>

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#include <linux/ioport.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

   146

#include <linux/rtnetlink.h>

   147

#include <linux/delay.h>

   148

#include <linux/ethtool.h>

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#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <asm/io.h>

   153

#include <asm/uaccess.h>

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#include <asm/irq.h>

   155

   156

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   157

   158

#include "ecdev.h"

   159

#include "../master/globals.h"

   160

   161

#define LIT(X) #X

   162

#define STR(X) LIT(X)

   163

   164

#define RTL8139_DRIVER_NAME DRV_NAME \

   165

                            " EtherCAT-capable Fast Ethernet driver " \

   166

                            DRV_VERSION ", master " EC_MASTER_VERSION

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   168

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   169

   170

#define PFX DRV_NAME ": "

   171

   172

/* Default Message level */

   173

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

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                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

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   177

   178

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   179

#ifdef CONFIG_8139TOO_PIO

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#define USE_IO_OPS 1

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#endif

   182

   183

/* define to 1, 2 or 3 to enable copious debugging info */

   184

#define RTL8139_DEBUG 0

   185

   186

/* define to 1 to disable lightweight runtime debugging checks */

   187

#undef RTL8139_NDEBUG

   188

   189

   190

#if RTL8139_DEBUG

   191

/* note: prints function name for you */

   192

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

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#else

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#  define DPRINTK(fmt, args...)

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#endif

   196

   197

#ifdef RTL8139_NDEBUG

   198

#  define assert(expr) do {} while (0)

   199

#else

   200

#  define assert(expr) \

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        if(unlikely(!(expr))) {				        \

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        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

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        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

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        }

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#endif

   206

   207

   208

/* A few user-configurable values. */

   209

/* media options */

   210

#define MAX_UNITS 8

   211

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   212

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   213

   214

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   215

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   216

static int multicast_filter_limit = 32;

   217

   218

/* bitmapped message enable number */

   219

static int debug = -1;

   220

   221

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   222

   223

static int ec_device_index = -1;

   224

static int ec_device_master_index = 0;

   225

static ec_device_t *rtl_ec_dev;

   226

struct net_device *rtl_ec_net_dev = NULL;

   227

   228

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   229

   230

/*

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 * Receive ring size 

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 * Warning: 64K ring has hardware issues and may lock up.

   233

 */

   234

#if defined(CONFIG_SH_DREAMCAST)

   235

#define RX_BUF_IDX	1	/* 16K ring */

   236

#else

   237

#define RX_BUF_IDX	2	/* 32K ring */

   238

#endif

   239

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   240

#define RX_BUF_PAD	16

   241

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   242

   243

#if RX_BUF_LEN == 65536

   244

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   245

#else

   246

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   247

#endif

   248

   249

/* Number of Tx descriptor registers. */

   250

#define NUM_TX_DESC	4

   251

   252

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   253

#define MAX_ETH_FRAME_SIZE	1536

   254

   255

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   256

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   257

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   258

   259

/* PCI Tuning Parameters

   260

   Threshold is bytes transferred to chip before transmission starts. */

   261

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   262

   263

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   264

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   265

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   266

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   267

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   268

   269

/* Operational parameters that usually are not changed. */

   270

/* Time in jiffies before concluding the transmitter is hung. */

   271

#define TX_TIMEOUT  (6*HZ)

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   273

   274

enum {

   275

	HAS_MII_XCVR = 0x010000,

   276

	HAS_CHIP_XCVR = 0x020000,

   277

	HAS_LNK_CHNG = 0x040000,

   278

};

   279

   280

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   281

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   282

#define RTL_MIN_IO_SIZE 0x80

   283

#define RTL8139B_IO_SIZE 256

   284

   285

#define RTL8129_CAPS	HAS_MII_XCVR

   286

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   287

   288

typedef enum {

   289

	RTL8139 = 0,

   290

	RTL8129,

   291

} board_t;

   292

   293

   294

/* indexed by board_t, above */

   295

static struct {

   296

	const char *name;

   297

	u32 hw_flags;

   298

} board_info[] __devinitdata = {

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	{ "RealTek RTL8139", RTL8139_CAPS },

   300

	{ "RealTek RTL8129", RTL8129_CAPS },

   301

};

   302

   303

   304

static struct pci_device_id rtl8139_pci_tbl[] = {

   305

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   306

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   308

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   309

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   310

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   311

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   312

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   313

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   314

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   315

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   316

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   317

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   318

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   319

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   320

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   321

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   322

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   323

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 

   324

   325

#ifdef CONFIG_SH_SECUREEDGE5410

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	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

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#ifdef CONFIG_8139TOO_8129

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   331

#endif

   332

   333

	/* some crazy cards report invalid vendor ids like

   334

	 * 0x0001 here.  The other ids are valid and constant,

   335

	 * so we simply don't match on the main vendor id.

   336

	 */

   337

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   338

	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   339

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   340

   341

	{0,}

   342

};

   343

   344

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   345

   346

/* prevent driver from being loaded automatically */

   347

//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   348

   349

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   350

   351

static struct {

   352

	const char str[ETH_GSTRING_LEN];

   353

} ethtool_stats_keys[] = {

   354

	{ "early_rx" },

   355

	{ "tx_buf_mapped" },

   356

	{ "tx_timeouts" },

   357

	{ "rx_lost_in_ring" },

   358

};

   359

   360

/* The rest of these values should never change. */

   361

   362

/* Symbolic offsets to registers. */

   363

enum RTL8139_registers {

   364

	MAC0 = 0,		/* Ethernet hardware address. */

   365

	MAR0 = 8,		/* Multicast filter. */

   366

	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   367

	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   368

	RxBuf = 0x30,

   369

	ChipCmd = 0x37,

   370

	RxBufPtr = 0x38,

   371

	RxBufAddr = 0x3A,

   372

	IntrMask = 0x3C,

   373

	IntrStatus = 0x3E,

   374

	TxConfig = 0x40,

   375

	RxConfig = 0x44,

   376

	Timer = 0x48,		/* A general-purpose counter. */

   377

	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   378

	Cfg9346 = 0x50,

   379

	Config0 = 0x51,

   380

	Config1 = 0x52,

   381

	FlashReg = 0x54,

   382

	MediaStatus = 0x58,

   383

	Config3 = 0x59,

   384

	Config4 = 0x5A,		/* absent on RTL-8139A */

   385

	HltClk = 0x5B,

   386

	MultiIntr = 0x5C,

   387

	TxSummary = 0x60,

   388

	BasicModeCtrl = 0x62,

   389

	BasicModeStatus = 0x64,

   390

	NWayAdvert = 0x66,

   391

	NWayLPAR = 0x68,

   392

	NWayExpansion = 0x6A,

   393

	/* Undocumented registers, but required for proper operation. */

   394

	FIFOTMS = 0x70,		/* FIFO Control and test. */

   395

	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   396

	PARA78 = 0x78,

   397

	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   398

	Config5 = 0xD8,		/* absent on RTL-8139A */

   399

};

   400

   401

enum ClearBitMasks {

   402

	MultiIntrClear = 0xF000,

   403

	ChipCmdClear = 0xE2,

   404

	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   405

};

   406

   407

enum ChipCmdBits {

   408

	CmdReset = 0x10,

   409

	CmdRxEnb = 0x08,

   410

	CmdTxEnb = 0x04,

   411

	RxBufEmpty = 0x01,

   412

};

   413

   414

/* Interrupt register bits, using my own meaningful names. */

   415

enum IntrStatusBits {

   416

	PCIErr = 0x8000,

   417

	PCSTimeout = 0x4000,

   418

	RxFIFOOver = 0x40,

   419

	RxUnderrun = 0x20,

   420

	RxOverflow = 0x10,

   421

	TxErr = 0x08,

   422

	TxOK = 0x04,

   423

	RxErr = 0x02,

   424

	RxOK = 0x01,

   425

   426

	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   427

};

   428

   429

enum TxStatusBits {

   430

	TxHostOwns = 0x2000,

   431

	TxUnderrun = 0x4000,

   432

	TxStatOK = 0x8000,

   433

	TxOutOfWindow = 0x20000000,

   434

	TxAborted = 0x40000000,

   435

	TxCarrierLost = 0x80000000,

   436

};

   437

enum RxStatusBits {

   438

	RxMulticast = 0x8000,

   439

	RxPhysical = 0x4000,

   440

	RxBroadcast = 0x2000,

   441

	RxBadSymbol = 0x0020,

   442

	RxRunt = 0x0010,

   443

	RxTooLong = 0x0008,

   444

	RxCRCErr = 0x0004,

   445

	RxBadAlign = 0x0002,

   446

	RxStatusOK = 0x0001,

   447

};

   448

   449

/* Bits in RxConfig. */

   450

enum rx_mode_bits {

   451

	AcceptErr = 0x20,

   452

	AcceptRunt = 0x10,

   453

	AcceptBroadcast = 0x08,

   454

	AcceptMulticast = 0x04,

   455

	AcceptMyPhys = 0x02,

   456

	AcceptAllPhys = 0x01,

   457

};

   458

   459

/* Bits in TxConfig. */

   460

enum tx_config_bits {

   461

   462

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   463

        TxIFGShift = 24,

   464

        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   465

        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   466

        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   467

        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   468

   469

	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   470

	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   471

	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   472

	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   473

	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   474

   475

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   476

};

   477

   478

/* Bits in Config1 */

   479

enum Config1Bits {

   480

	Cfg1_PM_Enable = 0x01,

   481

	Cfg1_VPD_Enable = 0x02,

   482

	Cfg1_PIO = 0x04,

   483

	Cfg1_MMIO = 0x08,

   484

	LWAKE = 0x10,		/* not on 8139, 8139A */

   485

	Cfg1_Driver_Load = 0x20,

   486

	Cfg1_LED0 = 0x40,

   487

	Cfg1_LED1 = 0x80,

   488

	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   489

	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   490

};

   491

   492

/* Bits in Config3 */

   493

enum Config3Bits {

   494

	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   495

	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   496

	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   497

	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   498

	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   499

	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   500

	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   501

	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   502

};

   503

   504

/* Bits in Config4 */

   505

enum Config4Bits {

   506

	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   507

};

   508

   509

/* Bits in Config5 */

   510

enum Config5Bits {

   511

	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   512

	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   513

	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   514

	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   515

	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   516

	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   517

	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   518

};

   519

   520

enum RxConfigBits {

   521

	/* rx fifo threshold */

   522

	RxCfgFIFOShift = 13,

   523

	RxCfgFIFONone = (7 << RxCfgFIFOShift),