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/******************************************************************************

     2

 *

     3

 *  $Id$

     4

 *

     5

 *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it

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 *  and/or modify it under the terms of the GNU General Public License

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 *  as published by the Free Software Foundation; either version 2 of the

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 *  License, or (at your option) any later version.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be

    15

 *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

    16

 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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 *  GNU General Public License for more details.

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 *

    19

 *  You should have received a copy of the GNU General Public License

    20

 *  along with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

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 *  The right to use EtherCAT Technology is granted and comes free of

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 *  charge under condition of compatibility of product made by

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 *  Licensee. People intending to distribute/sell products based on the

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 *  code, have to sign an agreement to guarantee that products using

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 *  software based on IgH EtherCAT master stay compatible with the actual

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 *  EtherCAT specification (which are released themselves as an open

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 *  standard) as the (only) precondition to have the right to use EtherCAT

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 *  Technology, IP and trade marks.

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 *

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 *****************************************************************************/

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    34

/**

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   \file

    36

   EtherCAT driver for RTL8139-compatible NICs.

    37

*/

    38

    39

/*****************************************************************************/

    40

    41

/*

    42

  Former documentation:

    43

    44

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    45

    46

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

    48

    49

	Much code comes from Donald Becker's rtl8139.c driver,

    50

	versions 1.13 and older.  This driver was originally based

    51

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    52

    53

	-----<snip>-----

    54

    55

        	Written 1997-2001 by Donald Becker.

    56

		This software may be used and distributed according to the

    57

		terms of the GNU General Public License (GPL), incorporated

    58

		herein by reference.  Drivers based on or derived from this

    59

		code fall under the GPL and must retain the authorship,

    60

		copyright and license notice.  This file is not a complete

    61

		program and may only be used when the entire operating

    62

		system is licensed under the GPL.

    63

    64

		This driver is for boards based on the RTL8129 and RTL8139

    65

		PCI ethernet chips.

    66

    67

		The author may be reached as becker@scyld.com, or C/O Scyld

    68

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    69

		MD 21403

    70

    71

		Support and updates available at

    72

		http://www.scyld.com/network/rtl8139.html

    73

    74

		Twister-tuning table provided by Kinston

    75

		<shangh@realtek.com.tw>.

    76

    77

	-----<snip>-----

    78

    79

	This software may be used and distributed according to the terms

    80

	of the GNU General Public License, incorporated herein by reference.

    81

    82

	Contributors:

    83

    84

		Donald Becker - he wrote the original driver, kudos to him!

    85

		(but please don't e-mail him for support, this isn't his driver)

    86

    87

		Tigran Aivazian - bug fixes, skbuff free cleanup

    88

    89

		Martin Mares - suggestions for PCI cleanup

    90

    91

		David S. Miller - PCI DMA and softnet updates

    92

    93

		Ernst Gill - fixes ported from BSD driver

    94

    95

		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

    97

    98

		Gerard Sharp - bug fix, testing and feedback

    99

   100

		David Ford - Rx ring wrap fix

   101

   102

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

   103

		to find and fix a crucial bug on older chipsets.

   104

   105

		Donald Becker/Chris Butterworth/Marcus Westergren -

   106

		Noticed various Rx packet size-related buglets.

   107

   108

		Santiago Garcia Mantinan - testing and feedback

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   110

		Jens David - 2.2.x kernel backports

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   112

		Martin Dennett - incredibly helpful insight on undocumented

   113

		features of the 8139 chips

   114

   115

		Jean-Jacques Michel - bug fix

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   117

		Tobias Ringström - Rx interrupt status checking suggestion

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   119

		Andrew Morton - Clear blocked signals, avoid

   120

		buffer overrun setting current->comm.

   121

   122

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   123

   124

		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

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   128

		"rtl8139-diag -mmmaaavvveefN" output

   129

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   130

   131

*/

   132

   133

#define DRV_NAME	"ec_8139too"

   134

#define DRV_VERSION	"0.9.27"

   135

   136

   137

#include <linux/config.h>

   138

#include <linux/module.h>

   139

#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

   142

#include <linux/init.h>

   143

#include <linux/ioport.h>

   144

#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

   146

#include <linux/rtnetlink.h>

   147

#include <linux/delay.h>

   148

#include <linux/ethtool.h>

   149

#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <asm/io.h>

   153

#include <asm/uaccess.h>

   154

#include <asm/irq.h>

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   156

#include "../globals.h"

   157

#include "ecdev.h"

   158

   159

#define RTL8139_DRIVER_NAME DRV_NAME \

   160

                            " EtherCAT-capable Fast Ethernet driver " \

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                            DRV_VERSION ", master " EC_MASTER_VERSION

   162

   163

#define PFX DRV_NAME ": "

   164

   165

/* Default Message level */

   166

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

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                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   169

   170

   171

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   172

#ifdef CONFIG_8139TOO_PIO

   173

#define USE_IO_OPS 1

   174

#endif

   175

   176

/* define to 1, 2 or 3 to enable copious debugging info */

   177

#define RTL8139_DEBUG 0

   178

   179

/* define to 1 to disable lightweight runtime debugging checks */

   180

#undef RTL8139_NDEBUG

   181

   182

   183

#if RTL8139_DEBUG

   184

/* note: prints function name for you */

   185

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   186

#else

   187

#  define DPRINTK(fmt, args...)

   188

#endif

   189

   190

#ifdef RTL8139_NDEBUG

   191

#  define assert(expr) do {} while (0)

   192

#else

   193

#  define assert(expr) \

   194

        if(unlikely(!(expr))) {				        \

   195

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   196

        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   197

        }

   198

#endif

   199

   200

   201

/* A few user-configurable values. */

   202

/* media options */

   203

#define MAX_UNITS 8

   204

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   205

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   206

   207

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   208

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   209

static int multicast_filter_limit = 32;

   210

   211

/* bitmapped message enable number */

   212

static int debug = -1;

   213

   214

/*

   215

 * Receive ring size 

   216

 * Warning: 64K ring has hardware issues and may lock up.

   217

 */

   218

#if defined(CONFIG_SH_DREAMCAST)

   219

#define RX_BUF_IDX	1	/* 16K ring */

   220

#else

   221

#define RX_BUF_IDX	2	/* 32K ring */

   222

#endif

   223

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   224

#define RX_BUF_PAD	16

   225

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   226

   227

#if RX_BUF_LEN == 65536

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#define RX_BUF_TOT_LEN	RX_BUF_LEN

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#else

   230

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   231

#endif

   232

   233

/* Number of Tx descriptor registers. */

   234

#define NUM_TX_DESC	4

   235

   236

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   237

#define MAX_ETH_FRAME_SIZE	1536

   238

   239

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   240

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   241

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   242

   243

/* PCI Tuning Parameters

   244

   Threshold is bytes transferred to chip before transmission starts. */

   245

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   246

   247

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   248

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   249

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   250

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   251

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   252

   253

/* Operational parameters that usually are not changed. */

   254

/* Time in jiffies before concluding the transmitter is hung. */

   255

#define TX_TIMEOUT  (6*HZ)

   256

   257

   258

enum {

   259

	HAS_MII_XCVR = 0x010000,

   260

	HAS_CHIP_XCVR = 0x020000,

   261

	HAS_LNK_CHNG = 0x040000,

   262

};

   263

   264

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   265

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   266

#define RTL_MIN_IO_SIZE 0x80

   267

#define RTL8139B_IO_SIZE 256

   268

   269

#define RTL8129_CAPS	HAS_MII_XCVR

   270

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   271

   272

typedef enum {

   273

	RTL8139 = 0,

   274

	RTL8129,

   275

} board_t;

   276

   277

   278

/* indexed by board_t, above */

   279

static struct {

   280

	const char *name;

   281

	u32 hw_flags;

   282

} board_info[] __devinitdata = {

   283

	{ "RealTek RTL8139", RTL8139_CAPS },

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	{ "RealTek RTL8129", RTL8129_CAPS },

   285

};

   286

   287

   288

static struct pci_device_id rtl8139_pci_tbl[] = {

   289

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   302

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   305

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   306

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 

   308

   309

#ifdef CONFIG_SH_SECUREEDGE5410

   310

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   311

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   312

#endif

   313

#ifdef CONFIG_8139TOO_8129

   314

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   315

#endif

   316

   317

	/* some crazy cards report invalid vendor ids like

   318

	 * 0x0001 here.  The other ids are valid and constant,

   319

	 * so we simply don't match on the main vendor id.

   320

	 */

   321

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   323

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   324

   325

	{0,}

   326

};

   327

   328

/* prevent driver from being loaded automatically */

   329

//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   330

   331

static struct {

   332

	const char str[ETH_GSTRING_LEN];

   333

} ethtool_stats_keys[] = {

   334

	{ "early_rx" },

   335

	{ "tx_buf_mapped" },

   336

	{ "tx_timeouts" },

   337

	{ "rx_lost_in_ring" },

   338

};

   339

   340

/* The rest of these values should never change. */

   341

   342

/* Symbolic offsets to registers. */

   343

enum RTL8139_registers {

   344

	MAC0 = 0,		/* Ethernet hardware address. */

   345

	MAR0 = 8,		/* Multicast filter. */

   346

	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   347

	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   348

	RxBuf = 0x30,

   349

	ChipCmd = 0x37,

   350

	RxBufPtr = 0x38,

   351

	RxBufAddr = 0x3A,

   352

	IntrMask = 0x3C,

   353

	IntrStatus = 0x3E,

   354

	TxConfig = 0x40,

   355

	RxConfig = 0x44,

   356

	Timer = 0x48,		/* A general-purpose counter. */

   357

	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   358

	Cfg9346 = 0x50,

   359

	Config0 = 0x51,

   360

	Config1 = 0x52,

   361

	FlashReg = 0x54,

   362

	MediaStatus = 0x58,

   363

	Config3 = 0x59,

   364

	Config4 = 0x5A,		/* absent on RTL-8139A */

   365

	HltClk = 0x5B,

   366

	MultiIntr = 0x5C,

   367

	TxSummary = 0x60,

   368

	BasicModeCtrl = 0x62,

   369

	BasicModeStatus = 0x64,

   370

	NWayAdvert = 0x66,

   371

	NWayLPAR = 0x68,

   372

	NWayExpansion = 0x6A,

   373

	/* Undocumented registers, but required for proper operation. */

   374

	FIFOTMS = 0x70,		/* FIFO Control and test. */

   375

	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   376

	PARA78 = 0x78,

   377

	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   378

	Config5 = 0xD8,		/* absent on RTL-8139A */

   379

};

   380

   381

enum ClearBitMasks {

   382

	MultiIntrClear = 0xF000,

   383

	ChipCmdClear = 0xE2,

   384

	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   385

};

   386

   387

enum ChipCmdBits {

   388

	CmdReset = 0x10,

   389

	CmdRxEnb = 0x08,

   390

	CmdTxEnb = 0x04,

   391

	RxBufEmpty = 0x01,

   392

};

   393

   394

/* Interrupt register bits, using my own meaningful names. */

   395

enum IntrStatusBits {

   396

	PCIErr = 0x8000,

   397

	PCSTimeout = 0x4000,

   398

	RxFIFOOver = 0x40,

   399

	RxUnderrun = 0x20,

   400

	RxOverflow = 0x10,

   401

	TxErr = 0x08,

   402

	TxOK = 0x04,

   403

	RxErr = 0x02,

   404

	RxOK = 0x01,

   405

   406

	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   407

};

   408

   409

enum TxStatusBits {

   410

	TxHostOwns = 0x2000,

   411

	TxUnderrun = 0x4000,

   412

	TxStatOK = 0x8000,

   413

	TxOutOfWindow = 0x20000000,

   414

	TxAborted = 0x40000000,

   415

	TxCarrierLost = 0x80000000,

   416

};

   417

enum RxStatusBits {

   418

	RxMulticast = 0x8000,

   419

	RxPhysical = 0x4000,

   420

	RxBroadcast = 0x2000,

   421

	RxBadSymbol = 0x0020,

   422

	RxRunt = 0x0010,

   423

	RxTooLong = 0x0008,

   424

	RxCRCErr = 0x0004,

   425

	RxBadAlign = 0x0002,

   426

	RxStatusOK = 0x0001,

   427

};

   428

   429

/* Bits in RxConfig. */

   430

enum rx_mode_bits {

   431

	AcceptErr = 0x20,

   432

	AcceptRunt = 0x10,

   433

	AcceptBroadcast = 0x08,

   434

	AcceptMulticast = 0x04,

   435

	AcceptMyPhys = 0x02,

   436

	AcceptAllPhys = 0x01,

   437

};

   438

   439

/* Bits in TxConfig. */

   440

enum tx_config_bits {

   441

   442

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   443

        TxIFGShift = 24,

   444

        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   445

        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   446

        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   447

        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   448

   449

	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   450

	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   451

	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   452

	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   453

	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   454

   455

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   456

};

   457

   458

/* Bits in Config1 */

   459

enum Config1Bits {

   460

	Cfg1_PM_Enable = 0x01,

   461

	Cfg1_VPD_Enable = 0x02,

   462

	Cfg1_PIO = 0x04,

   463

	Cfg1_MMIO = 0x08,

   464

	LWAKE = 0x10,		/* not on 8139, 8139A */

   465

	Cfg1_Driver_Load = 0x20,

   466

	Cfg1_LED0 = 0x40,

   467

	Cfg1_LED1 = 0x80,

   468

	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   469

	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   470

};

   471

   472

/* Bits in Config3 */

   473

enum Config3Bits {

   474

	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   475

	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   476

	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   477

	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   478

	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   479

	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   480

	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   481

	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   482

};

   483

   484

/* Bits in Config4 */

   485

enum Config4Bits {

   486

	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   487

};

   488

   489

/* Bits in Config5 */

   490

enum Config5Bits {

   491

	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   492

	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   493

	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   494

	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   495

	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   496

	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   497

	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   498

};

   499

   500

enum RxConfigBits {

   501

	/* rx fifo threshold */

   502

	RxCfgFIFOShift = 13,

   503

	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   504

   505

	/* Max DMA burst */

   506

	RxCfgDMAShift = 8,

   507

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   508

   509

	/* rx ring buffer length */

   510

	RxCfgRcv8K = 0,

   511

	RxCfgRcv16K = (1 << 11),

   512

	RxCfgRcv32K = (1 << 12),

   513

	RxCfgRcv64K = (1 << 11) | (1 << 12),

   514

   515

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   516

	RxNoWrap = (1 << 7),

   517

};

   518

   519

/* Twister tuning parameters from RealTek.

   520

   Completely undocumented, but required to tune bad links on some boards. */

   521

enum CSCRBits {

   522

	CSCR_LinkOKBit = 0x0400,

   523

	CSCR_LinkChangeBit = 0x0800,

   524

	CSCR_LinkStatusBits = 0x0f000,