859    Initializes a sync manager configuration page with EEPROM data.

   860    The referenced memory (\a data) must be at least EC_SYNC_SIZE bytes.

   861 */

   862 

   863 void ec_sync_config(const ec_sii_sync_t *sync, /**< sync manager */

   864                     const ec_slave_t *slave, /**< EtherCAT slave */

   865                     uint8_t *data /**> configuration memory */

   866                     )

   867 {

   868     size_t sync_size;

   869 

   870     sync_size = ec_slave_calc_sync_size(slave, sync);

   871 

   872     if (slave->master->debug_level) {

   873         EC_DBG("Slave %3i, SM %i: Addr 0x%04X, Size %3i, Ctrl 0x%02X, En %i\n",

   874                slave->ring_position, sync->index, sync->physical_start_address,

   875                sync_size, sync->control_register, sync->enable);

   876     }

   877 

   878     EC_WRITE_U16(data,     sync->physical_start_address);

   879     EC_WRITE_U16(data + 2, sync_size);

   880     EC_WRITE_U8 (data + 4, sync->control_register);

   881     EC_WRITE_U8 (data + 5, 0x00); // status byte (read only)

   882     EC_WRITE_U16(data + 6, sync->enable ? 0x0001 : 0x0000); // enable

   883 }

   884 

   885 /*****************************************************************************/

   886 

   887 /**

   888    Initializes an FMMU configuration page.

   889    The referenced memory (\a data) must be at least EC_FMMU_SIZE bytes.

   890 */

   891 

   892 void ec_fmmu_config(const ec_fmmu_t *fmmu, /**< FMMU */

   893                     const ec_slave_t *slave, /**< EtherCAT slave */

   894                     uint8_t *data /**> configuration memory */

   895                     )

   896 {

   897     size_t sync_size;

   898 

   899     sync_size = ec_slave_calc_sync_size(slave, fmmu->sync);

   900 

   901     if (slave->master->debug_level) {

   902         EC_DBG("Slave %3i, FMMU %2i:"

   903                " LogAddr 0x%08X, Size %3i, PhysAddr 0x%04X, Dir %s\n",

   904                slave->ring_position, fmmu->index, fmmu->logical_start_address,

   905                sync_size, fmmu->sync->physical_start_address,

   906                ((fmmu->sync->control_register & 0x04) ? "out" : "in"));

   907     }

   908 

   909     EC_WRITE_U32(data,      fmmu->logical_start_address);

   910     EC_WRITE_U16(data + 4,  sync_size); // size of fmmu

   911     EC_WRITE_U8 (data + 6,  0x00); // logical start bit

   912     EC_WRITE_U8 (data + 7,  0x07); // logical end bit

   913     EC_WRITE_U16(data + 8,  fmmu->sync->physical_start_address);

   914     EC_WRITE_U8 (data + 10, 0x00); // physical start bit

   915     EC_WRITE_U8 (data + 11, ((fmmu->sync->control_register & 0x04)

   916                              ? 0x02 : 0x01));

   917     EC_WRITE_U16(data + 12, 0x0001); // enable

   918     EC_WRITE_U16(data + 14, 0x0000); // reserved

   919 }

   920 

   921 /*****************************************************************************/

   922 

   923 /**