1

/******************************************************************************

     2

 *

     3

 *  $Id$

     4

 *

     5

 *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

     6

 *

     7

 *  This file is part of the IgH EtherCAT Master.

     8

 *

     9

 *  The IgH EtherCAT Master is free software; you can redistribute it

    10

 *  and/or modify it under the terms of the GNU General Public License

    11

 *  as published by the Free Software Foundation; either version 2 of the

    12

 *  License, or (at your option) any later version.

    13

 *

    14

 *  The IgH EtherCAT Master is distributed in the hope that it will be

    15

 *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

    16

 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17

 *  GNU General Public License for more details.

    18

 *

    19

 *  You should have received a copy of the GNU General Public License

    20

 *  along with the IgH EtherCAT Master; if not, write to the Free Software

    21

 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    22

 *

    23

 *  The right to use EtherCAT Technology is granted and comes free of

    24

 *  charge under condition of compatibility of product made by

    25

 *  Licensee. People intending to distribute/sell products based on the

    26

 *  code, have to sign an agreement to guarantee that products using

    27

 *  software based on IgH EtherCAT master stay compatible with the actual

    28

 *  EtherCAT specification (which are released themselves as an open

    29

 *  standard) as the (only) precondition to have the right to use EtherCAT

    30

 *  Technology, IP and trade marks.

    31

 *

    32

 *****************************************************************************/

    33

    34

/**

    35

   \file

    36

   EtherCAT finite state machines.

    37

*/

    38

    39

/*****************************************************************************/

    40

    41

#ifndef __EC_FSM_MASTER__

    42

#define __EC_FSM_MASTER__

    43

    44

#include "globals.h"

    45

#include "../include/ecrt.h"

    46

#include "datagram.h"

    47

#include "slave.h"

    48

#include "canopen.h"

    49

    50

#include "fsm_slave.h"

    51

#include "fsm_coe_map.h"

    52

    53

/*****************************************************************************/

    54

    55

/**

    56

 * EEPROM write request.

    57

 */

    58

    59

typedef struct

    60

{

    61

    struct list_head list; /**< list head */

    62

    ec_slave_t *slave; /**< EtherCAT slave */

    63

    off_t word_offset; /**< SII address in words */

    64

    size_t word_size; /**< data size in words */

    65

    const uint8_t *data; /**< pointer to the data */

    66

    ec_request_state_t state; /**< state of the request */

    67

}

    68

ec_eeprom_write_request_t;

    69

    70

/*****************************************************************************/

    71

    72

typedef struct ec_fsm_master ec_fsm_master_t; /**< \see ec_fsm_master */

    73

    74

/**

    75

   Finite state machine of an EtherCAT master.

    76

*/

    77

    78

struct ec_fsm_master

    79

{

    80

    ec_master_t *master; /**< master the FSM runs on */

    81

    ec_datagram_t *datagram; /**< datagram used in the state machine */

    82

    unsigned int retries; /**< retries on datagram timeout. */

    83

    84

    void (*state)(ec_fsm_master_t *); /**< master state function */

    85

    int idle; /**< state machine is in idle phase */

    86

    unsigned long scan_jiffies; /**< beginning of slave scanning */

    87

    unsigned int slaves_responding; /**< number of responding slaves */

    88

    unsigned int topology_change_pending; /**< bus topology changed */

    89

    ec_slave_state_t slave_states; /**< states of responding slaves */

    90

    unsigned int validate; /**< non-zero, if validation to do */

    91

    unsigned int tainted; /**< non-zero, if the current bus topology does

    92

                            not meet the initial conditions */

    93

    unsigned int config_error; /**< error during slave configuration */

    94

    ec_slave_t *slave; /**< current slave */

    95

    ec_eeprom_write_request_t *eeprom_request; /**< EEPROM write request */

    96

    off_t eeprom_index; /**< index to EEPROM write request data */

    97

    ec_sdo_request_t *sdo_request; /**< SDO request to process */

    98

    99

    ec_fsm_slave_t fsm_slave; /**< slave state machine */

   100

    ec_fsm_sii_t fsm_sii; /**< SII state machine */

   101

    ec_fsm_change_t fsm_change; /**< State change state machine */

   102

    ec_fsm_coe_t fsm_coe; /**< CoE state machine */

   103

    ec_fsm_coe_map_t fsm_coe_map; /**< CoE mapping state machine */

   104

};

   105

   106

/*****************************************************************************/

   107

   108

void ec_fsm_master_init(ec_fsm_master_t *, ec_master_t *, ec_datagram_t *);

   109

void ec_fsm_master_clear(ec_fsm_master_t *);

   110

   111

int ec_fsm_master_exec(ec_fsm_master_t *);

   112

int ec_fsm_master_running(const ec_fsm_master_t *);

   113

int ec_fsm_master_idle(const ec_fsm_master_t *);

   114

   115

/*****************************************************************************/

   116

   117

#endif