1

/**

     2

    Network Driver for Beckhoff CCAT communication controller

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    Copyright (C) 2014 - 2015  Beckhoff Automation GmbH

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    Author: Patrick Bruenn <p.bruenn@beckhoff.com>

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     6

    This program is free software; you can redistribute it and/or modify

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    it under the terms of the GNU General Public License as published by

     8

    the Free Software Foundation; either version 2 of the License, or

     9

    (at your option) any later version.

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    This program is distributed in the hope that it will be useful,

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    but WITHOUT ANY WARRANTY; without even the implied warranty of

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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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    GNU General Public License for more details.

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    16

    You should have received a copy of the GNU General Public License along

    17

    with this program; if not, write to the Free Software Foundation, Inc.,

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    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

    19

*/

    20

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#include <linux/etherdevice.h>

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#include <linux/kernel.h>

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#include <linux/module.h>

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#include <linux/netdevice.h>

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#include <linux/version.h>

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    27

#ifdef CONFIG_PCI

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#include <asm/dma.h>

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#else

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#define free_dma(X)

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#define request_dma(X, Y) ((int)(-EINVAL))

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#endif

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    34

#include "module.h"

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    36

/**

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 * EtherCAT frame to enable forwarding on EtherCAT Terminals

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 */

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static const u8 frameForwardEthernetFrames[] = {

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	0x01, 0x01, 0x05, 0x01, 0x00, 0x00,

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	0x00, 0x1b, 0x21, 0x36, 0x1b, 0xce,

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	0x88, 0xa4, 0x0e, 0x10,

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	0x08,

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	0x00,

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	0x00, 0x00,

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	0x00, 0x01,

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	0x02, 0x00,

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	0x00, 0x00,

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	0x00, 0x00,

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	0x00, 0x00

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};

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    53

#define FIFO_LENGTH 64

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#define POLL_TIME ktime_set(0, 50 * NSEC_PER_USEC)

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#define CCAT_ALIGNMENT ((size_t)(128 * 1024))

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#define CCAT_ALIGN_CHANNEL(x, c) ((typeof(x))(ALIGN((size_t)((x) + ((c) * CCAT_ALIGNMENT)), CCAT_ALIGNMENT)))

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    58

struct ccat_dma_frame_hdr {

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	__le32 reserved1;

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	__le32 rx_flags;

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#define CCAT_FRAME_RECEIVED 0x1

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	__le16 length;

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	__le16 reserved3;

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	__le32 tx_flags;

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#define CCAT_FRAME_SENT 0x1

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	__le64 timestamp;

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};

    68

    69

struct ccat_eim_frame_hdr {

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	__le16 length;

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	__le16 reserved3;

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	__le32 tx_flags;

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	__le64 timestamp;

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};

    75

    76

struct ccat_eth_frame {

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	u8 placeholder[0x800];

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};

    79

    80

struct ccat_dma_frame {

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	struct ccat_dma_frame_hdr hdr;

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	u8 data[sizeof(struct ccat_eth_frame) -

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		sizeof(struct ccat_dma_frame_hdr)];

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};

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struct ccat_eim_frame {

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	struct ccat_eim_frame_hdr hdr;

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	u8 data[sizeof(struct ccat_eth_frame) -

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		sizeof(struct ccat_eim_frame_hdr)];

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};

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#define MAX_PAYLOAD_SIZE \

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	(sizeof(struct ccat_eth_frame) - max(sizeof(struct ccat_dma_frame_hdr), sizeof(struct ccat_eim_frame_hdr)))

    94

    95

/**

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 * struct ccat_eth_register - CCAT register addresses in the PCI BAR

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 * @mii: address of the CCAT management interface register

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 * @mac: address of the CCAT media access control register

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 * @rx_mem: address of the CCAT register holding the RX DMA address

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 * @tx_mem: address of the CCAT register holding the TX DMA address

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 * @misc: address of a CCAT register holding miscellaneous information

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 */

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struct ccat_eth_register {

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	void __iomem *mii;

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	void __iomem *mac;

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	void __iomem *rx_mem;

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	void __iomem *tx_mem;

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	void __iomem *misc;

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};

   110

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/**

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 * struct ccat_dma_mem - CCAT DMA channel configuration

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 * @size: number of bytes in the associated DMA memory

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 * @phys: device-viewed address(physical) of the associated DMA memory

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 * @channel: CCAT DMA channel number

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 * @dev: valid struct device pointer

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 * @base: CPU-viewed address(virtual) of the associated DMA memory

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 */

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struct ccat_dma_mem {

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	size_t size;

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	dma_addr_t phys;

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	size_t channel;

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	struct device *dev;

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	void *base;

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};

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   127

/**

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 * struct ccat_dma/eim/mem

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 * @next: pointer to the next frame in fifo ring buffer

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 * @start: aligned CPU-viewed address(virtual) of the associated memory

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 */

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struct ccat_dma {

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	struct ccat_dma_frame *next;

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	void *start;

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};

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struct ccat_eim {

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	struct ccat_eim_frame __iomem *next;

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	void __iomem *start;

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};

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struct ccat_mem {

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	struct ccat_eth_frame *next;

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	void *start;

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};

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   147

/**

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 * struct ccat_eth_fifo - CCAT RX or TX fifo

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 * @ops: function pointer table for dma/eim and rx/tx specific fifo functions

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 * @reg: PCI register address of this fifo

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 * @rx_bytes: number of bytes processed -> reported with ndo_get_stats64()

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 * @rx_dropped: number of dropped frames -> reported with ndo_get_stats64()

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 * @mem/dma/eim: information about the associated memory

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 */

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struct ccat_eth_fifo {

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	const struct ccat_eth_fifo_operations *ops;

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	const struct ccat_eth_frame *end;

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	void __iomem *reg;

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	atomic64_t bytes;

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	atomic64_t dropped;

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	union {

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		struct ccat_mem mem;

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		struct ccat_dma dma;

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		struct ccat_eim eim;

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	};

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};

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/**

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 * struct ccat_eth_fifo_operations

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 * @ready: callback used to test the next frames ready bit

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 * @add: callback used to add a frame to this fifo

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 * @copy_to_skb: callback used to copy from rx fifos to skbs

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 * @skb: callback used to queue skbs into tx fifos

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 */

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struct ccat_eth_fifo_operations {

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	size_t(*ready) (struct ccat_eth_fifo *);

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	void (*add) (struct ccat_eth_fifo *);

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	union {

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		void (*copy_to_skb) (struct ccat_eth_fifo *, struct sk_buff *,

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				     size_t);

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		void (*skb) (struct ccat_eth_fifo *, struct sk_buff *);

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	} queue;

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};

   184

   185

/**

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 * same as: typedef struct _CCatInfoBlockOffs from CCatDefinitions.h

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 */

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struct ccat_mac_infoblock {

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	u32 reserved;

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	u32 mii;

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	u32 tx_fifo;

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	u32 mac;

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	u32 rx_mem;

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	u32 tx_mem;

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	u32 misc;

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};

   197

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/**

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 * struct ccat_eth_priv - CCAT Ethernet/EtherCAT Master function (netdev)

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 * @func: pointer to the parent struct ccat_function

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 * @netdev: the net_device structure used by the kernel networking stack

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 * @reg: register addresses in PCI config space of the Ethernet/EtherCAT Master function

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 * @rx_fifo: fifo used for RX descriptors

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 * @tx_fifo: fifo used for TX descriptors

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 * @poll_timer: interval timer used to poll CCAT for events like link changed, rx done, tx done

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 */

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struct ccat_eth_priv {

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	struct ccat_function *func;

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	struct net_device *netdev;

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	struct ccat_eth_register reg;

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	struct ccat_eth_fifo rx_fifo;

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	struct ccat_eth_fifo tx_fifo;

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	struct hrtimer poll_timer;

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	struct ccat_dma_mem dma_mem;

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	ec_device_t *ecdev;

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	void (*carrier_off) (struct net_device * netdev);

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	 bool(*carrier_ok) (const struct net_device * netdev);

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	void (*carrier_on) (struct net_device * netdev);

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	void (*kfree_skb_any) (struct sk_buff * skb);

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	void (*receive) (struct ccat_eth_priv *, size_t);

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	void (*start_queue) (struct net_device * netdev);

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	void (*stop_queue) (struct net_device * netdev);

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	void (*unregister) (struct net_device * netdev);

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};

   225

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struct ccat_mac_register {

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	/** MAC error register     @+0x0 */

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	u8 frame_len_err;

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	u8 rx_err;

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	u8 crc_err;

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	u8 link_lost_err;

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	u32 reserved1;

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	/** Buffer overflow errors @+0x8 */

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	u8 rx_mem_full;

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	u8 reserved2[7];

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	/** MAC frame counter      @+0x10 */

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	u32 tx_frames;

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	u32 rx_frames;

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	u64 reserved3;

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	/** MAC fifo level         @+0x20 */

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	u8 tx_fifo_level:7;

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	u8 reserved4:1;

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	u8 reserved5[7];

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	/** TX memory full error   @+0x28 */

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	u8 tx_mem_full;

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	u8 reserved6[7];

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	u64 reserved8[9];

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	/** Connection             @+0x78 */

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	u8 mii_connected;

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};

   251

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static void fifo_set_end(struct ccat_eth_fifo *const fifo, size_t size)

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{

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	fifo->end = fifo->mem.start + size - sizeof(struct ccat_eth_frame);

   255

}

   256

   257

static void ccat_dma_free(struct ccat_eth_priv *const priv)

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{

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	if (priv->dma_mem.base) {

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		const struct ccat_dma_mem tmp = priv->dma_mem;

   261

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		memset(&priv->dma_mem, 0, sizeof(priv->dma_mem));

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		dma_free_coherent(tmp.dev, tmp.size, tmp.base, tmp.phys);

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		free_dma(priv->func->info.tx_dma_chan);

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		free_dma(priv->func->info.rx_dma_chan);

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	}

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}

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/**

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 * ccat_dma_init() - Initialize CCAT and host memory for DMA transfer

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 * @dma object for management data which will be initialized

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 * @channel number of the DMA channel

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 * @ioaddr of the pci bar2 configspace used to calculate the address of the pci dma configuration

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 * @dev which should be configured for DMA

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 */

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static int ccat_dma_init(struct ccat_dma_mem *const dma, size_t channel,

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			 void __iomem * const bar2,

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			 struct ccat_eth_fifo *const fifo)

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{

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	void __iomem *const ioaddr = bar2 + 0x1000 + (sizeof(u64) * channel);

   281

	const dma_addr_t phys = CCAT_ALIGN_CHANNEL(dma->phys, channel);

   282

	const u32 phys_hi = (sizeof(phys) > sizeof(u32)) ? phys >> 32 : 0;

   283

	fifo->dma.start = CCAT_ALIGN_CHANNEL(dma->base, channel);

   284

   285

	fifo_set_end(fifo, CCAT_ALIGNMENT);

   286

	if (request_dma(channel, KBUILD_MODNAME)) {

   287

		pr_info("request dma channel %llu failed\n", (u64) channel);

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		return -EINVAL;

   289

	}

   290

   291

	/** bit 0 enables 64 bit mode on ccat */

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	iowrite32((u32) phys | ((phys_hi) > 0), ioaddr);

   293

	iowrite32(phys_hi, ioaddr + 4);

   294

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	pr_info

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	    ("DMA%llu mem initialized\n base:         0x%p\n start:        0x%p\n phys:         0x%09llx\n pci addr:     0x%01x%08x\n size:         %llu |%llx bytes.\n",

   297

	     (u64) channel, dma->base, fifo->dma.start, (u64) dma->phys,

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	     ioread32(ioaddr + 4), ioread32(ioaddr),

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	     (u64) dma->size, (u64) dma->size);

   300

	return 0;

   301

}

   302

   303

static void ecdev_kfree_skb_any(struct sk_buff *skb)

   304

{

   305

	/* never release a skb in EtherCAT mode */

   306

}

   307

   308

static bool ecdev_carrier_ok(const struct net_device *const netdev)

   309

{

   310

	struct ccat_eth_priv *const priv = netdev_priv(netdev);

   311

	return ecdev_get_link(priv->ecdev);

   312

}

   313

   314

static void ecdev_carrier_on(struct net_device *const netdev)

   315

{

   316

	struct ccat_eth_priv *const priv = netdev_priv(netdev);

   317

	ecdev_set_link(priv->ecdev, 1);

   318

}

   319

   320

static void ecdev_carrier_off(struct net_device *const netdev)

   321

{

   322

	struct ccat_eth_priv *const priv = netdev_priv(netdev);

   323

	ecdev_set_link(priv->ecdev, 0);

   324

}

   325

   326

static void ecdev_nop(struct net_device *const netdev)

   327

{

   328

	/* dummy called if nothing has to be done in EtherCAT operation mode */

   329

}

   330

   331

static void ecdev_receive_dma(struct ccat_eth_priv *const priv, size_t len)

   332

{

   333

	ecdev_receive(priv->ecdev, priv->rx_fifo.dma.next->data, len);

   334

}

   335

   336

static void ecdev_receive_eim(struct ccat_eth_priv *const priv, size_t len)

   337

{

   338

	ecdev_receive(priv->ecdev, priv->rx_fifo.eim.next->data, len);

   339

}

   340

   341

static void unregister_ecdev(struct net_device *const netdev)

   342

{

   343

	struct ccat_eth_priv *const priv = netdev_priv(netdev);

   344

	ecdev_close(priv->ecdev);

   345

	ecdev_withdraw(priv->ecdev);

   346

}

   347

   348

static inline size_t fifo_eim_tx_ready(struct ccat_eth_fifo *const fifo)

   349

{

   350

	struct ccat_eth_priv *const priv =

   351

	    container_of(fifo, struct ccat_eth_priv, tx_fifo);

   352

	static const size_t TX_FIFO_LEVEL_OFFSET = 0x20;

   353

	static const u8 TX_FIFO_LEVEL_MASK = 0x3F;

   354

	void __iomem *addr = priv->reg.mac + TX_FIFO_LEVEL_OFFSET;

   355

   356

	return !(ioread8(addr) & TX_FIFO_LEVEL_MASK);

   357

}

   358

   359

static inline size_t fifo_eim_rx_ready(struct ccat_eth_fifo *const fifo)

   360

{

   361

	static const size_t OVERHEAD = sizeof(struct ccat_eim_frame_hdr);

   362

	const size_t len = ioread16(&fifo->eim.next->hdr.length);

   363

   364

	return (len < OVERHEAD) ? 0 : len - OVERHEAD;

   365

}

   366

   367

static void ccat_eth_fifo_inc(struct ccat_eth_fifo *fifo)

   368

{

   369

	if (++fifo->mem.next > fifo->end)

   370

		fifo->mem.next = fifo->mem.start;

   371

}

   372

   373

static void fifo_eim_rx_add(struct ccat_eth_fifo *const fifo)

   374

{

   375

	struct ccat_eim_frame __iomem *frame = fifo->eim.next;

   376

	iowrite16(0, frame);

   377

	wmb();

   378

}

   379

   380

static void fifo_eim_tx_add(struct ccat_eth_fifo *const fifo)

   381

{

   382

}

   383

   384

#define memcpy_from_ccat(DEST, SRC, LEN) memcpy(DEST,(__force void*)(SRC), LEN)

   385

#define memcpy_to_ccat(DEST, SRC, LEN) memcpy((__force void*)(DEST),SRC, LEN)

   386

static void fifo_eim_copy_to_linear_skb(struct ccat_eth_fifo *const fifo,

   387

					struct sk_buff *skb, const size_t len)

   388

{

   389

	memcpy_from_ccat(skb->data, fifo->eim.next->data, len);

   390

}

   391

   392

static void fifo_eim_queue_skb(struct ccat_eth_fifo *const fifo,

   393

			       struct sk_buff *skb)

   394

{

   395

	struct ccat_eim_frame __iomem *frame = fifo->eim.next;

   396

	const u32 addr_and_length =

   397

	    (void __iomem *)frame - (void __iomem *)fifo->eim.start;

   398

   399

	const __le16 length = cpu_to_le16(skb->len);

   400

	memcpy_to_ccat(&frame->hdr.length, &length, sizeof(length));

   401

	memcpy_to_ccat(frame->data, skb->data, skb->len);

   402

	iowrite32(addr_and_length, fifo->reg);

   403

}

   404

   405

static void ccat_eth_fifo_hw_reset(struct ccat_eth_fifo *const fifo)

   406

{

   407

	if (fifo->reg) {

   408

		iowrite32(0, fifo->reg + 0x8);

   409

		wmb();

   410

	}

   411

}

   412

   413

static void ccat_eth_fifo_reset(struct ccat_eth_fifo *const fifo)

   414

{

   415

	ccat_eth_fifo_hw_reset(fifo);

   416

   417

	if (fifo->ops->add) {

   418

		fifo->mem.next = fifo->mem.start;

   419

		do {

   420

			fifo->ops->add(fifo);

   421

			ccat_eth_fifo_inc(fifo);

   422

		} while (fifo->mem.next != fifo->mem.start);

   423

	}

   424

}

   425

   426

static inline size_t fifo_dma_tx_ready(struct ccat_eth_fifo *const fifo)

   427

{

   428

	const struct ccat_dma_frame *frame = fifo->dma.next;

   429

	return le32_to_cpu(frame->hdr.tx_flags) & CCAT_FRAME_SENT;

   430

}

   431

   432

static inline size_t fifo_dma_rx_ready(struct ccat_eth_fifo *const fifo)

   433

{

   434

	static const size_t OVERHEAD =

   435

	    offsetof(struct ccat_dma_frame_hdr, rx_flags);

   436

	const struct ccat_dma_frame *const frame = fifo->dma.next;

   437

   438

	if (le32_to_cpu(frame->hdr.rx_flags) & CCAT_FRAME_RECEIVED) {

   439

		const size_t len = le16_to_cpu(frame->hdr.length);

   440

		return (len < OVERHEAD) ? 0 : len - OVERHEAD;

   441

	}

   442

	return 0;

   443

}

   444

   445

static void ccat_eth_rx_fifo_dma_add(struct ccat_eth_fifo *const fifo)

   446

{

   447

	struct ccat_dma_frame *const frame = fifo->dma.next;

   448

	const size_t offset = (void *)frame - fifo->dma.start;

   449

	const u32 addr_and_length = (1 << 31) | offset;

   450

   451

	frame->hdr.rx_flags = cpu_to_le32(0);

   452

	iowrite32(addr_and_length, fifo->reg);

   453

}

   454

   455

static void ccat_eth_tx_fifo_dma_add_free(struct ccat_eth_fifo *const fifo)

   456

{

   457

	/* mark frame as ready to use for tx */

   458

	fifo->dma.next->hdr.tx_flags = cpu_to_le32(CCAT_FRAME_SENT);

   459

}

   460

   461

static void fifo_dma_copy_to_linear_skb(struct ccat_eth_fifo *const fifo,

   462

					struct sk_buff *skb, const size_t len)

   463

{

   464

	skb_copy_to_linear_data(skb, fifo->dma.next->data, len);

   465

}

   466

   467

static void fifo_dma_queue_skb(struct ccat_eth_fifo *const fifo,

   468

			       struct sk_buff *skb)

   469

{

   470

	struct ccat_dma_frame *frame = fifo->dma.next;

   471

	u32 addr_and_length;

   472

   473

	frame->hdr.tx_flags = cpu_to_le32(0);

   474

	frame->hdr.length = cpu_to_le16(skb->len);

   475

   476

	memcpy(frame->data, skb->data, skb->len);

   477

   478

	/* Queue frame into CCAT TX-FIFO, CCAT ignores the first 8 bytes of the tx descriptor */

   479

	addr_and_length = offsetof(struct ccat_dma_frame_hdr, length);

   480

	addr_and_length += ((void *)frame - fifo->dma.start);

   481

	addr_and_length +=

   482

	    ((skb->len + sizeof(struct ccat_dma_frame_hdr)) / 8) << 24;

   483

	iowrite32(addr_and_length, fifo->reg);

   484

}

   485

   486

static const struct ccat_eth_fifo_operations dma_rx_fifo_ops = {

   487

	.add = ccat_eth_rx_fifo_dma_add,

   488

	.ready = fifo_dma_rx_ready,

   489

	.queue.copy_to_skb = fifo_dma_copy_to_linear_skb,

   490

};

   491

   492

static const struct ccat_eth_fifo_operations dma_tx_fifo_ops = {

   493