replace not working symlinks with real copies from the ccat main repository(git) stable-1.5
authorPatrick Bruenn <p.bruenn@beckhoff.com>
Fri, 04 Apr 2014 08:59:37 +0200
branchstable-1.5
changeset 2550 7e25950ea941
parent 2549 933a1b36b05f
child 2551 000da5069f1a
replace not working symlinks with real copies from the ccat main repository(git)
devices/ccat/CCatDefinitions.h
devices/ccat/COPYING
devices/ccat/module-3.4-ethercat.c
devices/ccat/module.h
devices/ccat/netdev-3.4-ethercat.c
devices/ccat/netdev.h
devices/ccat/print-3.4-ethercat.c
devices/ccat/print.h
devices/ccat/update-3.4-ethercat.c
devices/ccat/update.h
--- a/devices/ccat/CCatDefinitions.h	Fri Apr 04 08:32:09 2014 +0200
+++ b/devices/ccat/CCatDefinitions.h	Fri Apr 04 08:59:37 2014 +0200
@@ -1,1 +1,249 @@
-../../../ccat/CCatDefinitions.h
\ No newline at end of file
+/**
+    Network Driver for Beckhoff CCAT communication controller
+    Copyright (C) 2014  Beckhoff Automation GmbH
+    Author: Patrick Bruenn <p.bruenn@beckhoff.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+#ifndef _CCAT_DEFINITIONS_H_
+#define _CCAT_DEFINITIONS_H_
+
+#ifndef WINDOWS
+#include <linux/kernel.h>
+typedef uint8_t BYTE;
+typedef uint32_t ULONG;
+typedef uint16_t USHORT;
+typedef uint8_t UINT8;
+typedef uint16_t UINT16;
+typedef uint32_t UINT32;
+typedef uint64_t UINT64;
+
+#undef pr_fmt
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#endif
+
+typedef struct _ETHERNET_ADDRESS
+{
+	UINT8 b[6];
+}ETHERNET_ADDRESS;
+
+
+typedef uint64_t LIST_ENTRY;
+
+typedef enum CCatInfoTypes
+{
+	CCATINFO_NOTUSED				= 0,
+	CCATINFO_BLOCK					= 1,
+	CCATINFO_ETHERCAT_SLAVE		= 2,
+	CCATINFO_ETHERCAT_MASTER	= 3,
+	CCATINFO_ETHERNET_MAC		= 4,
+	CCATINFO_ETHERNET_SWITCH	= 5,
+	CCATINFO_SERCOS3				= 6,
+	CCATINFO_PROFIBUS				= 7,
+	CCATINFO_CAN_CONTROLLER		= 8,
+	CCATINFO_KBUS_MASTER			= 9,
+	CCATINFO_IP_LINK				= 10,
+	CCATINFO_SPI_MASTER			= 11,
+	CCATINFO_I2C_MASTER			= 12,
+	CCATINFO_GPIO					= 13,
+	CCATINFO_DRIVEIP				= 14,
+	CCATINFO_EPCS_PROM			= 15,
+	CCATINFO_SYSTIME				= 16,
+	CCATINFO_INTCTRL				= 17,
+	CCATINFO_EEPROM				= 18,
+	CCATINFO_DMA					= 19,
+	CCATINFO_ETHERCAT_MASTER_DMA	= 20,
+	CCATINFO_ETHERNET_MAC_DMA		= 21,
+	CCATINFO_SRAM					= 22,
+	CCATINFO_COPY_BLOCK			= 23,
+	CCATINFO_MAX
+} _CCatInfoTypes;
+
+typedef struct
+{
+	USHORT	eCCatInfoType;
+	USHORT	nRevision;
+	union
+	{
+		ULONG		nParam;
+		struct 
+		{
+			BYTE nMaxEntries;
+			BYTE compileDay;
+			BYTE compileMonth;
+			BYTE compileYear;
+		};
+		struct 
+		{
+			BYTE txDmaChn;
+			BYTE rxDmaChn;
+		};
+		struct
+		{
+			BYTE		nExternalDataSize	: 2;
+			BYTE		reserved1			: 6;
+			BYTE		nRamSize; //size = 2^ramSize
+			USHORT	reserved2;
+		};
+	};
+	ULONG		nAddr;
+	ULONG		nSize;
+} CCatInfoBlock, *PCCatInfoBlock;
+
+typedef struct _CCAT_HEADER_TAG
+{
+	UINT16	length; // not used in header // required for 64 Bit Alignment in CCAT
+	UINT8		port0				: 1;
+	UINT8		port1				: 1;					
+	UINT8		reserved1		: 6;
+	UINT8		tsEnable			: 1;
+	UINT8		reserved2		: 7;
+	UINT32	sent				: 1;
+	UINT32	reserved3		: 31;
+	UINT64   TimeStamp;	
+}CCAT_HEADER_TAG;
+
+typedef struct _CCatDmaTxFrame
+{
+	LIST_ENTRY			list;
+	CCAT_HEADER_TAG	head;
+	UINT8					data[0x800-sizeof(LIST_ENTRY)-sizeof(CCAT_HEADER_TAG)];
+}CCatDmaTxFrame;
+
+typedef struct _CCatRxDesc
+{
+	union
+	{
+		struct 
+		{
+			UINT32			nextDesc		: 24;
+			UINT32			reserved1	: 7;
+			UINT32			nextValid	: 1;
+			UINT32			received		: 1;
+			UINT32			reserved2	: 31;
+		};
+		UINT32			head[2];
+	};
+	union
+	{
+		struct
+		{
+			UINT16		length		: 12;
+			UINT16		reserved3	: 4;
+		};
+		UINT16 uLength;
+	};
+	UINT16		port;
+	UINT32		reserved4;
+	UINT64		timestamp;
+	UINT8			data[0x7e8];
+}CCatRxDesc;
+
+typedef struct _CCatMacRegs
+{
+	union
+	{
+		struct
+		{
+			UINT8			frameLenErrCnt;
+			UINT8			rxErrCnt;
+			UINT8			crcErrCnt;
+			UINT8			linkLostErrCnt;
+		};
+		UINT32 errCnt;
+	};
+	UINT32			reserved1;
+	UINT8				dropFrameErrCnt; // 0x08
+	UINT8				reserved2[7];	
+	UINT32			txFrameCnt;		  // 0x10
+	UINT32			rxFrameCnt;		  // 0x14
+	UINT32   reserved3[2];
+	UINT8    txFifoLevel  : 7;
+	UINT8    reserved4    : 1;
+	UINT8    reserved5[7];
+	UINT8    txErrMemFull;
+	UINT8    reserved6[7];
+	UINT32   reserved8[18];
+	UINT8    miiConnected;
+}CCatMacRegs;
+
+typedef struct _CCatMii
+{
+	USHORT		startMiCycle	: 1;
+	USHORT		reserved1		: 6;
+	USHORT		cmdErr			: 1;
+#define MII_CMD_READ 1
+#define MII_CMD_WRITE 2
+	USHORT		cmd				: 2;
+	USHORT		reserved2		: 6;
+	USHORT		phyAddr			: 5;
+	USHORT		reserved3		: 3;
+	USHORT		phyReg			: 5;
+	USHORT		reserved4		: 3;
+	USHORT		phyWriteData;
+	USHORT		phyReadData;
+	ETHERNET_ADDRESS	macAddr;
+	USHORT		macFilterEnabled		: 1;
+	USHORT		reserved6				: 7;
+	USHORT		linkStatus				: 1;
+	USHORT		reserved7				: 7;
+	ULONG       led0;
+	ULONG       led1;
+	ULONG       led2[2];
+	ULONG       systimeInsertion[4];
+	ULONG		interruptState[2];
+	ULONG		interruptMask[2];	
+}CCatMii;
+
+typedef struct _CCatDmaTxFifo
+{
+	UINT32   startAddr      : 24;
+	UINT32   numQuadWords   : 8;
+	UINT32   reserved1;
+	UINT8    fifoReset;
+	UINT8    reserved2[7];
+}CCatDmaTxFifo;
+
+typedef struct _CCatDmaRxActBuf
+{
+	union
+	{
+		struct 
+		{
+			UINT32			startAddr	: 24;
+			UINT32			reserved1	: 7;
+			UINT32			nextValid	: 1;
+			UINT32			lastAddr		: 24;
+			UINT32			reserved2	: 8;
+			UINT32			FifoLevel	: 24;
+			UINT32			bufferLevel	: 8;
+			UINT32			nextAddr;
+		};
+		UINT32			rxActBuf;
+	};
+}CCatDmaRxActBuf;
+
+typedef struct _CCatInfoBlockOffs
+{
+	UINT32			reserved;
+	UINT32			nMMIOffs;
+	UINT32			nTxFifoOffs;
+	UINT32			nMacRegOffs;
+	UINT32			nRxMemOffs;
+	UINT32			nTxMemOffs;
+	UINT32			nMiscOffs;
+} CCatInfoBlockOffs;
+#endif /* #ifndef _CCAT_DEFINITIONS_H_ */
+
--- a/devices/ccat/COPYING	Fri Apr 04 08:32:09 2014 +0200
+++ b/devices/ccat/COPYING	Fri Apr 04 08:59:37 2014 +0200
@@ -1,1 +1,339 @@
-../../../ccat/COPYING
\ No newline at end of file
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
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+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
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--- a/devices/ccat/module-3.4-ethercat.c	Fri Apr 04 08:32:09 2014 +0200
+++ b/devices/ccat/module-3.4-ethercat.c	Fri Apr 04 08:59:37 2014 +0200
@@ -1,1 +1,308 @@
-../../../ccat/module.c
\ No newline at end of file
+/**
+    Network Driver for Beckhoff CCAT communication controller
+    Copyright (C) 2014  Beckhoff Automation GmbH
+    Author: Patrick Bruenn <p.bruenn@beckhoff.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include <asm/dma.h>
+#include <linux/etherdevice.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include "module.h"
+#include "netdev.h"
+#include "update.h"
+
+MODULE_DESCRIPTION(DRV_DESCRIPTION);
+MODULE_AUTHOR("Patrick Bruenn <p.bruenn@beckhoff.com>");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
+static void ccat_bar_free(struct ccat_bar *bar)
+{
+	if (bar->ioaddr) {
+		const struct ccat_bar tmp = *bar;
+		memset(bar, 0, sizeof(*bar));
+		iounmap(tmp.ioaddr);
+		release_mem_region(tmp.start, tmp.len);
+	} else {
+		pr_warn("%s(): %p was already done.\n", __FUNCTION__, bar);
+	}
+}
+
+/**
+ * ccat_bar_init() - Initialize a CCAT pci bar
+ * @bar object which should be initialized
+ * @index 0 and 2 are valid for CCAT, meaning pci bar0 or pci bar2
+ * @pdev the pci device as which the CCAT was recognized before
+ *
+ * Reading PCI config space; request and map memory region.
+ */
+static int ccat_bar_init(struct ccat_bar *bar, size_t index,
+			 struct pci_dev *pdev)
+{
+	struct resource *res;
+	bar->start = pci_resource_start(pdev, index);
+	bar->end = pci_resource_end(pdev, index);
+	bar->len = pci_resource_len(pdev, index);
+	bar->flags = pci_resource_flags(pdev, index);
+	if (!(IORESOURCE_MEM & bar->flags)) {
+		pr_info("bar%llu is no mem_region -> abort.\n",
+			(uint64_t) index);
+		return -EIO;
+	}
+
+	res = request_mem_region(bar->start, bar->len, DRV_NAME);
+	if (!res) {
+		pr_info("allocate mem_region failed.\n");
+		return -EIO;
+	}
+	pr_debug("bar%llu at [%lx,%lx] len=%lu res: %p.\n", (uint64_t) index,
+		 bar->start, bar->end, bar->len, res);
+
+	bar->ioaddr = ioremap(bar->start, bar->len);
+	if (!bar->ioaddr) {
+		pr_info("bar%llu ioremap failed.\n", (uint64_t) index);
+		release_mem_region(bar->start, bar->len);
+		return -EIO;
+	}
+	pr_debug("bar%llu I/O mem mapped to %p.\n", (uint64_t) index,
+		 bar->ioaddr);
+	return 0;
+}
+
+void ccat_dma_free(struct ccat_dma *const dma)
+{
+	const struct ccat_dma tmp = *dma;
+	free_dma(dma->channel);
+	memset(dma, 0, sizeof(*dma));
+	dma_free_coherent(tmp.dev, tmp.size, tmp.virt, tmp.phys);
+}
+
+/**
+ * ccat_dma_init() - Initialize CCAT and host memory for DMA transfer
+ * @dma object for management data which will be initialized
+ * @channel number of the DMA channel
+ * @ioaddr of the pci bar2 configspace used to calculate the address of the pci dma configuration
+ * @dev which should be configured for DMA
+ */
+int ccat_dma_init(struct ccat_dma *const dma, size_t channel,
+		  void __iomem * const ioaddr, struct device *const dev)
+{
+	void *frame;
+	uint64_t addr;
+	uint32_t translateAddr;
+	uint32_t memTranslate;
+	uint32_t memSize;
+	uint32_t data = 0xffffffff;
+	uint32_t offset = (sizeof(uint64_t) * channel) + 0x1000;
+
+	dma->channel = channel;
+	dma->dev = dev;
+
+	/* calculate size and alignments */
+	iowrite32(data, ioaddr + offset);
+	wmb();
+	data = ioread32(ioaddr + offset);
+	memTranslate = data & 0xfffffffc;
+	memSize = (~memTranslate) + 1;
+	dma->size = 2 * memSize - PAGE_SIZE;
+	dma->virt = dma_zalloc_coherent(dev, dma->size, &dma->phys, GFP_KERNEL);
+	if (!dma->virt || !dma->phys) {
+		pr_info("init DMA%llu memory failed.\n", (uint64_t) channel);
+		return -1;
+	}
+
+	if (request_dma(channel, DRV_NAME)) {
+		pr_info("request dma channel %llu failed\n",
+			(uint64_t) channel);
+		ccat_dma_free(dma);
+		return -1;
+	}
+
+	translateAddr = (dma->phys + memSize - PAGE_SIZE) & memTranslate;
+	addr = translateAddr;
+	memcpy_toio(ioaddr + offset, &addr, sizeof(addr));
+	frame = dma->virt + translateAddr - dma->phys;
+	pr_debug
+	    ("DMA%llu mem initialized\n virt:         0x%p\n phys:         0x%llx\n translated:   0x%llx\n pci addr:     0x%08x%x\n memTranslate: 0x%x\n size:         %llu bytes.\n",
+	     (uint64_t) channel, dma->virt, (uint64_t) (dma->phys), addr,
+	     ioread32(ioaddr + offset + 4), ioread32(ioaddr + offset),
+	     memTranslate, (uint64_t) dma->size);
+	return 0;
+}
+
+/**
+ * Initialize all available CCAT functions.
+ *
+ * Return: count of failed functions
+ */
+static int ccat_functions_init(struct ccat_device *const ccatdev)
+{
+	/* read CCatInfoBlock.nMaxEntries from ccat */
+	const uint8_t num_func = ioread8(ccatdev->bar[0].ioaddr + 4);
+	void __iomem *addr = ccatdev->bar[0].ioaddr;
+	const void __iomem *end = addr + (sizeof(CCatInfoBlock) * num_func);
+	int status = 0;		//count init function failures
+
+	while (addr < end) {
+		const uint8_t type = ioread16(addr);
+		switch (type) {
+		case CCATINFO_NOTUSED:
+			break;
+		case CCATINFO_EPCS_PROM:
+			pr_info("Found: CCAT update(EPCS_PROM) -> init()\n");
+			ccatdev->update = ccat_update_init(ccatdev, addr);
+			status += (NULL == ccatdev->update);
+			break;
+		case CCATINFO_ETHERCAT_MASTER_DMA:
+			pr_info("Found: ETHERCAT_MASTER_DMA -> init()\n");
+			ccatdev->ethdev = ccat_eth_init(ccatdev, addr);
+			status += (NULL == ccatdev->ethdev);
+			break;
+		default:
+			pr_info("Found: 0x%04x not supported\n", type);
+			break;
+		}
+		addr += sizeof(CCatInfoBlock);
+	}
+	return status;
+}
+
+/**
+ * Destroy all previously initialized CCAT functions
+ */
+static void ccat_functions_remove(struct ccat_device *const ccatdev)
+{
+	if (!ccatdev->ethdev) {
+		pr_warn("%s(): 'ethdev' was not initialized.\n", __FUNCTION__);
+	} else {
+		struct ccat_eth_priv *const ethdev = ccatdev->ethdev;
+		ccatdev->ethdev = NULL;
+		ccat_eth_remove(ethdev);
+	}
+	if (!ccatdev->update) {
+		pr_warn("%s(): 'update' was not initialized.\n", __FUNCTION__);
+	} else {
+		struct ccat_update *const update = ccatdev->update;
+		ccatdev->update = NULL;
+		ccat_update_remove(update);
+	}
+}
+
+static int ccat_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	int status;
+	u8 revision;
+	struct ccat_device *ccatdev = kmalloc(sizeof(*ccatdev), GFP_KERNEL);
+	if (!ccatdev) {
+		pr_err("%s() out of memory.\n", __FUNCTION__);
+		return -ENOMEM;
+	}
+	memset(ccatdev, 0, sizeof(*ccatdev));
+	ccatdev->pdev = pdev;
+	pci_set_drvdata(pdev, ccatdev);
+
+	status = pci_enable_device_mem(pdev);
+	if (status) {
+		pr_info("enable %s failed: %d\n", pdev->dev.kobj.name, status);
+		return status;
+	}
+
+	status = pci_read_config_byte(pdev, PCI_REVISION_ID, &revision);
+	if (status) {
+		pr_warn("read CCAT pci revision failed with %d\n", status);
+		return status;
+	}
+
+	/* FIXME upgrade to a newer kernel to get support of dma_set_mask_and_coherent()
+	 * (!dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64))) {
+	 */
+	if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
+		pr_debug("64 bit DMA supported, pci rev: %u\n", revision);
+		/*} else if (!dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32))) { */
+	} else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
+		pr_debug("32 bit DMA supported, pci rev: %u\n", revision);
+	} else {
+		pr_warn("No suitable DMA available, pci rev: %u\n", revision);
+	}
+
+	if (ccat_bar_init(&ccatdev->bar[0], 0, pdev)) {
+		pr_warn("initialization of bar0 failed.\n");
+		return -EIO;
+	}
+
+	if (ccat_bar_init(&ccatdev->bar[2], 2, pdev)) {
+		pr_warn("initialization of bar2 failed.\n");
+		return -EIO;
+	}
+
+	pci_set_master(pdev);
+	if (ccat_functions_init(ccatdev)) {
+		pr_warn("some functions couldn't be initialized\n");
+	}
+	return 0;
+}
+
+static void ccat_remove(struct pci_dev *pdev)
+{
+	struct ccat_device *ccatdev = pci_get_drvdata(pdev);
+	if (ccatdev) {
+		ccat_functions_remove(ccatdev);
+		ccat_bar_free(&ccatdev->bar[2]);
+		ccat_bar_free(&ccatdev->bar[0]);
+		pci_disable_device(pdev);
+		pci_set_drvdata(pdev, NULL);
+		kfree(ccatdev);
+	}
+	pr_debug("%s() done.\n", __FUNCTION__);
+}
+
+#define PCI_DEVICE_ID_BECKHOFF_CCAT 0x5000
+#define PCI_VENDOR_ID_BECKHOFF 0x15EC
+
+static const struct pci_device_id pci_ids[] = {
+	{PCI_DEVICE(PCI_VENDOR_ID_BECKHOFF, PCI_DEVICE_ID_BECKHOFF_CCAT)},
+	{0,},
+};
+
+MODULE_DEVICE_TABLE(pci, pci_ids);
+
+static struct pci_driver pci_driver = {
+	.name = DRV_NAME,
+	.id_table = pci_ids,
+	.probe = ccat_probe,
+	.remove = ccat_remove,
+};
+
+static void ccat_exit_module(void)
+{
+	pci_unregister_driver(&pci_driver);
+}
+
+static int ccat_init_module(void)
+{
+	static const size_t offset = offsetof(struct ccat_eth_frame, data);
+	BUILD_BUG_ON(sizeof(struct ccat_eth_frame) != sizeof(CCatDmaTxFrame));
+	BUILD_BUG_ON(sizeof(struct ccat_eth_frame) != sizeof(CCatRxDesc));
+	BUILD_BUG_ON(offset != offsetof(CCatDmaTxFrame, data));
+	BUILD_BUG_ON(offset != offsetof(CCatRxDesc, data));
+	pr_info("%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
+	return pci_register_driver(&pci_driver);
+}
+
+module_exit(ccat_exit_module);
+module_init(ccat_init_module);
--- a/devices/ccat/module.h	Fri Apr 04 08:32:09 2014 +0200
+++ b/devices/ccat/module.h	Fri Apr 04 08:59:37 2014 +0200
@@ -1,1 +1,205 @@
-../../../ccat/module.h
\ No newline at end of file
+/**
+    Network Driver for Beckhoff CCAT communication controller
+    Copyright (C) 2014  Beckhoff Automation GmbH
+    Author: Patrick Bruenn <p.bruenn@beckhoff.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef _CCAT_H_
+#define _CCAT_H_
+
+#include <linux/cdev.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include "CCatDefinitions.h"
+#include "../ecdev.h"
+
+#define DRV_NAME         "ec_ccat"
+#define DRV_EXTRAVERSION "-ec"
+#define DRV_VERSION      "0.7" DRV_EXTRAVERSION
+#define DRV_DESCRIPTION  "Beckhoff CCAT Ethernet/EtherCAT Network Driver"
+
+/**
+ * struct ccat_bar - CCAT PCI Base Address Register(BAR) configuration
+ * @start: start address of this BAR
+ * @end: end address of this BAR
+ * @len: length of this BAR
+ * @flags: flags set on this BAR
+ * @ioaddr: ioremapped address of this bar
+ */
+struct ccat_bar {
+	unsigned long start;
+	unsigned long end;
+	unsigned long len;
+	unsigned long flags;
+	void __iomem *ioaddr;
+};
+
+/**
+ * struct ccat_dma - CCAT DMA channel configuration
+ * @phys: device-viewed address(physical) of the associated DMA memory
+ * @virt: CPU-viewed address(virtual) of the associated DMA memory
+ * @size: number of bytes in the associated DMA memory
+ * @channel: CCAT DMA channel number
+ * @dev: valid struct device pointer
+ */
+struct ccat_dma {
+	dma_addr_t phys;
+	void *virt;
+	size_t size;
+	size_t channel;
+	struct device *dev;
+};
+
+extern void ccat_dma_free(struct ccat_dma *const dma);
+extern int ccat_dma_init(struct ccat_dma *const dma, size_t channel,
+			 void __iomem * const ioaddr, struct device *const dev);
+
+/**
+ * struct ccat_eth_frame - Ethernet frame with DMA descriptor header in front
+ * @reservedn: is not used and should always be set to 0
+ * @received: used for reception, is set to 1 by the CCAT when data was written
+ * @length: number of bytes in the frame including the DMA header
+ * @sent: is set to 1 by the CCAT when data was transmitted
+ * @timestamp: a 64 bit EtherCAT timestamp
+ * @data: the bytes of the ethernet frame
+ */
+struct ccat_eth_frame {
+	uint32_t reserved1;
+	uint32_t received:1;
+	uint32_t reserved2:31;
+	uint16_t length;
+	uint16_t reserved3;
+	uint32_t sent:1;
+	uint32_t reserved4:31;
+	uint64_t timestamp;
+	uint8_t data[0x800 - 3 * sizeof(uint64_t)];
+};
+
+/**
+ * struct ccat_eth_register - CCAT register addresses in the PCI BAR
+ * @mii: address of the CCAT management interface register
+ * @tx_fifo: address of the CCAT TX DMA fifo register
+ * @rx_fifo: address of the CCAT RX DMA fifo register
+ * @mac: address of the CCAT media access control register
+ * @rx_mem: address of the CCAT register holding the RX DMA address
+ * @tx_mem: address of the CCAT register holding the TX DMA address
+ * @misc: address of a CCAT register holding miscellaneous information
+ */
+struct ccat_eth_register {
+	void __iomem *mii;
+	void __iomem *tx_fifo;
+	void __iomem *rx_fifo;
+	void __iomem *mac;
+	void __iomem *rx_mem;
+	void __iomem *tx_mem;
+	void __iomem *misc;
+};
+
+/**
+ * struct ccat_eth_dma_fifo - CCAT RX or TX DMA fifo
+ * @add: callback used to add a frame to this fifo
+ * @reg: PCI register address of this DMA fifo
+ * @dma: information about the associated DMA memory
+ */
+struct ccat_eth_dma_fifo {
+	void (*add) (struct ccat_eth_frame *, struct ccat_eth_dma_fifo *);
+	void __iomem *reg;
+	struct ccat_dma dma;
+};
+
+/**
+ * struct ccat_device - CCAT device representation
+ * @pdev: pointer to the pci object allocated by the kernel
+ * @ethdev: CCAT Ethernet/EtherCAT Master (with DMA) function, NULL if function is not available or failed to initialize
+ * @update: CCAT Update function, NULL if function is not available or failed to initialize
+ * @bar [0] and [2] holding information about PCI BARs 0 and 2.
+ *
+ * One instance of a ccat_device should represent a physical CCAT. Since
+ * a CCAT is implemented as FPGA the available functions can vary so
+ * the function object pointers can be NULL.
+ * Extra note: you will recognize that PCI BAR1 is not used and is a
+ * waste of memory, thats true but right now, its very easy to use it
+ * this way. So we might optimize it later.
+ */
+struct ccat_device {
+	struct pci_dev *pdev;
+	struct ccat_eth_priv *ethdev;
+	struct ccat_update *update;
+	struct ccat_bar bar[3];	//TODO optimize this
+};
+
+/**
+ * struct ccat_eth_priv - CCAT Ethernet/EtherCAT Master function (netdev)
+ * @ccatdev: pointer to the parent struct ccat_device
+ * @netdev: the net_device structure used by the kernel networking stack
+ * @poll_thread: is used to poll status registers like link state
+ * @rx_thread: thread which does housekeeping of RX DMA descriptors
+ * @tx_thread: thread which does housekeeping of TX DMA descriptors
+ * @next_tx_frame: pointer to the next TX DMA descriptor, which the tx_thread should check for availablity
+ * @info: holds a copy of the CCAT Ethernet/EtherCAT Master function information block (read from PCI config space)
+ * @reg: register addresses in PCI config space of the Ethernet/EtherCAT Master function
+ * @rx_fifo: DMA fifo used for RX DMA descriptors
+ * @tx_fifo: DMA fifo used for TX DMA descriptors
+ * @rx_bytes: number of bytes received -> reported with ndo_get_stats64()
+ * @rx_dropped: number of received frames, which were dropped -> reported with ndo_get_stats64()
+ * @tx_bytes: number of bytes send -> reported with ndo_get_stats64()
+ * @tx_dropped: number of frames requested to send, which were dropped -> reported with ndo_get_stats64()
+ */
+struct ccat_eth_priv {
+	const struct ccat_device *ccatdev;
+	struct net_device *netdev;
+	struct task_struct *poll_thread;
+	struct task_struct *rx_thread;
+	struct task_struct *tx_thread;
+	const struct ccat_eth_frame *next_tx_frame;	/* next frame the tx_thread should check for availability */
+	CCatInfoBlock info;
+	struct ccat_eth_register reg;
+	struct ccat_eth_dma_fifo rx_fifo;
+	struct ccat_eth_dma_fifo tx_fifo;
+	atomic64_t rx_bytes;
+	atomic64_t rx_dropped;
+	atomic64_t tx_bytes;
+	atomic64_t tx_dropped;
+	ec_device_t *ecdev;
+	void (*carrier_off) (struct net_device * const netdev);
+	void (*carrier_on) (struct net_device * const netdev);
+	void (*kfree_skb_any) (struct sk_buff * skb);
+	void (*start_queue) (struct net_device * const netdev);
+	void (*stop_queue) (struct net_device * const netdev);
+	void (*tx_fifo_full) (struct net_device * const dev,
+			      const struct ccat_eth_frame * const frame);
+	void (*unregister) (struct net_device * const netdev);
+};
+
+/**
+ * struct ccat_update - CCAT Update function (update)
+ * @ccatdev: pointer to the parent struct ccat_device
+ * @ioaddr: PCI base address of the CCAT Update function
+ * dev: device number for this update function
+ * cdev: character device used for the CCAT Update function
+ * class: pointer to a device class used when registering the CCAT Update device
+ * @info: holds a copy of the CCAT Update function information block (read from PCI config space)
+ */
+struct ccat_update {
+	struct kref refcount;
+	void __iomem *ioaddr;
+	dev_t dev;
+	struct cdev cdev;
+	struct class *class;
+	CCatInfoBlock info;
+};
+#endif /* #ifndef _CCAT_H_ */
--- a/devices/ccat/netdev-3.4-ethercat.c	Fri Apr 04 08:32:09 2014 +0200
+++ b/devices/ccat/netdev-3.4-ethercat.c	Fri Apr 04 08:59:37 2014 +0200
@@ -1,1 +1,588 @@
-../../../ccat/netdev.c
\ No newline at end of file
+/**
+    Network Driver for Beckhoff CCAT communication controller
+    Copyright (C) 2014  Beckhoff Automation GmbH
+    Author: Patrick Bruenn <p.bruenn@beckhoff.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include <linux/etherdevice.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/kfifo.h>
+#include <linux/kthread.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/spinlock.h>
+
+#include "module.h"
+#include "netdev.h"
+#include "print.h"
+
+/**
+ * EtherCAT frame to enable forwarding on EtherCAT Terminals
+ */
+static const UINT8 frameForwardEthernetFrames[] = {
+	0x01, 0x01, 0x05, 0x01, 0x00, 0x00,
+	0x00, 0x1b, 0x21, 0x36, 0x1b, 0xce,
+	0x88, 0xa4, 0x0e, 0x10,
+	0x08,
+	0x00,
+	0x00, 0x00,
+	0x00, 0x01,
+	0x02, 0x00,
+	0x00, 0x00,
+	0x00, 0x00,
+	0x00, 0x00
+};
+
+#define FIFO_LENGTH 64
+#define DMA_POLL_DELAY_RANGE_USECS 100, 100	/* time to sleep between rx/tx DMA polls */
+#define POLL_DELAY_RANGE_USECS 500, 1000	/* time to sleep between link state polls */
+
+static void ec_poll(struct net_device *dev);
+static int run_poll_thread(void *data);
+static int run_rx_thread(void *data);
+static int run_tx_thread(void *data);
+
+static struct rtnl_link_stats64 *ccat_eth_get_stats64(struct net_device *dev, struct rtnl_link_stats64
+						      *storage);
+static int ccat_eth_open(struct net_device *dev);
+static netdev_tx_t ccat_eth_start_xmit(struct sk_buff *skb,
+				       struct net_device *dev);
+static int ccat_eth_stop(struct net_device *dev);
+static void ccat_eth_xmit_raw(struct net_device *dev, const char *data,
+			      size_t len);
+
+static const struct net_device_ops ccat_eth_netdev_ops = {
+	.ndo_get_stats64 = ccat_eth_get_stats64,
+	.ndo_open = ccat_eth_open,
+	.ndo_start_xmit = ccat_eth_start_xmit,
+	.ndo_stop = ccat_eth_stop,
+};
+
+static void ecdev_kfree_skb_any(struct sk_buff *skb)
+{
+	/* never release a skb in EtherCAT mode */
+}
+
+static void ecdev_carrier_on(struct net_device *const netdev)
+{
+	struct ccat_eth_priv *const priv = netdev_priv(netdev);
+	ecdev_set_link(priv->ecdev, 1);
+}
+
+static void ecdev_carrier_off(struct net_device *const netdev)
+{
+	struct ccat_eth_priv *const priv = netdev_priv(netdev);
+	ecdev_set_link(priv->ecdev, 0);
+}
+
+static void ecdev_nop(struct net_device *const netdev)
+{
+	/* dummy called if nothing has to be done in EtherCAT operation mode */
+}
+
+static void ecdev_tx_fifo_full(struct net_device *const dev,
+			       const struct ccat_eth_frame *const frame)
+{
+	/* we are polled -> there is nothing we can do in EtherCAT mode */
+}
+
+static void unregister_ecdev(struct net_device *const netdev)
+{
+	struct ccat_eth_priv *const priv = netdev_priv(netdev);
+	ecdev_close(priv->ecdev);
+	ecdev_withdraw(priv->ecdev);
+}
+
+typedef void (*fifo_add_function) (struct ccat_eth_frame *,
+				   struct ccat_eth_dma_fifo *);
+
+static void ccat_eth_rx_fifo_add(struct ccat_eth_frame *frame,
+				 struct ccat_eth_dma_fifo *fifo)
+{
+	const size_t offset = ((void *)(frame) - fifo->dma.virt);
+	const uint32_t addr_and_length = (1 << 31) | offset;
+	frame->received = 0;
+	iowrite32(addr_and_length, fifo->reg);
+}
+
+static void ccat_eth_tx_fifo_add_free(struct ccat_eth_frame *frame,
+				      struct ccat_eth_dma_fifo *fifo)
+{
+	/* mark frame as ready to use for tx */
+	frame->sent = 1;
+}
+
+static void ccat_eth_tx_fifo_full(struct net_device *const dev,
+				  const struct ccat_eth_frame *const frame)
+{
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	netif_stop_queue(dev);
+	priv->next_tx_frame = frame;
+	wake_up_process(priv->tx_thread);
+}
+
+static void ccat_eth_dma_fifo_reset(struct ccat_eth_dma_fifo *fifo)
+{
+	struct ccat_eth_frame *frame = fifo->dma.virt;
+	const struct ccat_eth_frame *const end = frame + FIFO_LENGTH;
+
+	/* reset hw fifo */
+	iowrite32(0, fifo->reg + 0x8);
+	wmb();
+
+	if (fifo->add) {
+		while (frame < end) {
+			fifo->add(frame, fifo);
+			++frame;
+		}
+	}
+}
+
+static int ccat_eth_dma_fifo_init(struct ccat_eth_dma_fifo *fifo,
+				  void __iomem * const fifo_reg,
+				  fifo_add_function add, size_t channel,
+				  struct ccat_eth_priv *const priv)
+{
+	if (0 !=
+	    ccat_dma_init(&fifo->dma, channel, priv->ccatdev->bar[2].ioaddr,
+			  &priv->ccatdev->pdev->dev)) {
+		pr_info("init DMA%llu memory failed.\n", (uint64_t) channel);
+		return -1;
+	}
+	fifo->add = add;
+	fifo->reg = fifo_reg;
+	return 0;
+}
+
+/**
+ * Stop both (Rx/Tx) DMA fifo's and free related management structures
+ */
+static void ccat_eth_priv_free_dma(struct ccat_eth_priv *priv)
+{
+	/* reset hw fifo's */
+	iowrite32(0, priv->rx_fifo.reg + 0x8);
+	iowrite32(0, priv->tx_fifo.reg + 0x8);
+	wmb();
+
+	/* release dma */
+	ccat_dma_free(&priv->rx_fifo.dma);
+	ccat_dma_free(&priv->tx_fifo.dma);
+	pr_debug("DMA fifo's stopped.\n");
+}
+
+/**
+ * Initalizes both (Rx/Tx) DMA fifo's and related management structures
+ */
+static int ccat_eth_priv_init_dma(struct ccat_eth_priv *priv)
+{
+	if (ccat_eth_dma_fifo_init
+	    (&priv->rx_fifo, priv->reg.rx_fifo, ccat_eth_rx_fifo_add,
+	     priv->info.rxDmaChn, priv)) {
+		pr_warn("init Rx DMA fifo failed.\n");
+		return -1;
+	}
+
+	if (ccat_eth_dma_fifo_init
+	    (&priv->tx_fifo, priv->reg.tx_fifo, ccat_eth_tx_fifo_add_free,
+	     priv->info.txDmaChn, priv)) {
+		pr_warn("init Tx DMA fifo failed.\n");
+		ccat_dma_free(&priv->rx_fifo.dma);
+		return -1;
+	}
+
+	/* disable MAC filter */
+	iowrite8(0, priv->reg.mii + 0x8 + 6);
+	wmb();
+	return 0;
+}
+
+/**
+ * Initializes the CCat... members of the ccat_eth_priv structure.
+ * Call this function only if info and ioaddr are already initialized!
+ */
+static void ccat_eth_priv_init_mappings(struct ccat_eth_priv *priv)
+{
+	CCatInfoBlockOffs offsets;
+	void __iomem *const func_base =
+	    priv->ccatdev->bar[0].ioaddr + priv->info.nAddr;
+	memcpy_fromio(&offsets, func_base, sizeof(offsets));
+	priv->reg.mii = func_base + offsets.nMMIOffs;
+	priv->reg.tx_fifo = func_base + offsets.nTxFifoOffs;
+	priv->reg.rx_fifo = func_base + offsets.nTxFifoOffs + 0x10;
+	priv->reg.mac = func_base + offsets.nMacRegOffs;
+	priv->reg.rx_mem = func_base + offsets.nRxMemOffs;
+	priv->reg.tx_mem = func_base + offsets.nTxMemOffs;
+	priv->reg.misc = func_base + offsets.nMiscOffs;
+}
+
+/**
+ * Read link state from CCAT hardware
+ * @return 1 if link is up, 0 if not
+ */
+inline static size_t ccat_eth_priv_read_link_state(const struct ccat_eth_priv
+						   *const priv)
+{
+	return (1 << 24) == (ioread32(priv->reg.mii + 0x8 + 4) & (1 << 24));
+}
+
+static struct rtnl_link_stats64 *ccat_eth_get_stats64(struct net_device *dev, struct rtnl_link_stats64
+						      *storage)
+{
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	CCatMacRegs mac;
+	memcpy_fromio(&mac, priv->reg.mac, sizeof(mac));
+	storage->rx_packets = mac.rxFrameCnt;	/* total packets received       */
+	storage->tx_packets = mac.txFrameCnt;	/* total packets transmitted    */
+	storage->rx_bytes = atomic64_read(&priv->rx_bytes);	/* total bytes received         */
+	storage->tx_bytes = atomic64_read(&priv->tx_bytes);	/* total bytes transmitted      */
+	storage->rx_errors = mac.frameLenErrCnt + mac.dropFrameErrCnt + mac.crcErrCnt + mac.rxErrCnt;	/* bad packets received         */
+	//TODO __u64    tx_errors;              /* packet transmit problems     */
+	storage->rx_dropped = atomic64_read(&priv->rx_dropped);	/* no space in linux buffers    */
+	storage->tx_dropped = atomic64_read(&priv->tx_dropped);	/* no space available in linux  */
+	//TODO __u64    multicast;              /* multicast packets received   */
+	//TODO __u64    collisions;
+
+	/* detailed rx_errors: */
+	storage->rx_length_errors = mac.frameLenErrCnt;
+	storage->rx_over_errors = mac.dropFrameErrCnt;	/* receiver ring buff overflow  */
+	storage->rx_crc_errors = mac.crcErrCnt;	/* recved pkt with crc error    */
+	storage->rx_frame_errors = mac.rxErrCnt;	/* recv'd frame alignment error */
+	storage->rx_fifo_errors = mac.dropFrameErrCnt;	/* recv'r fifo overrun          */
+	//TODO __u64    rx_missed_errors;       /* receiver missed packet       */
+
+	/* detailed tx_errors */
+	//TODO __u64    tx_aborted_errors;
+	//TODO __u64    tx_carrier_errors;
+	//TODO __u64    tx_fifo_errors;
+	//TODO __u64    tx_heartbeat_errors;
+	//TODO __u64    tx_window_errors;
+
+	/* for cslip etc */
+	//TODO __u64    rx_compressed;
+	//TODO __u64    tx_compressed;
+	return storage;
+}
+
+struct ccat_eth_priv *ccat_eth_init(const struct ccat_device *const ccatdev,
+				    const void __iomem * const addr)
+{
+	struct ccat_eth_priv *priv;
+	struct net_device *const netdev = alloc_etherdev(sizeof(*priv));
+	priv = netdev_priv(netdev);
+	priv->netdev = netdev;
+	priv->ccatdev = ccatdev;
+
+	/* ccat register mappings */
+	memcpy_fromio(&priv->info, addr, sizeof(priv->info));
+	ccat_eth_priv_init_mappings(priv);
+	ccat_print_function_info(priv);
+
+	if (ccat_eth_priv_init_dma(priv)) {
+		pr_warn("%s(): DMA initialization failed.\n", __FUNCTION__);
+		free_netdev(netdev);
+		return NULL;
+	}
+
+	/* init netdev with MAC and stack callbacks */
+	memcpy_fromio(netdev->dev_addr, priv->reg.mii + 8, 6);
+	netdev->netdev_ops = &ccat_eth_netdev_ops;
+
+	/* use as EtherCAT device? */
+	priv->ecdev = ecdev_offer(netdev, ec_poll, THIS_MODULE);
+	if (priv->ecdev) {
+		priv->carrier_off = ecdev_carrier_off;
+		priv->carrier_on = ecdev_carrier_on;
+		priv->kfree_skb_any = ecdev_kfree_skb_any;
+		priv->start_queue = ecdev_nop;
+		priv->stop_queue = ecdev_nop;
+		priv->tx_fifo_full = ecdev_tx_fifo_full;
+		priv->unregister = unregister_ecdev;
+		if (ecdev_open(priv->ecdev)) {
+			pr_info("unable to register network device.\n");
+			ecdev_withdraw(priv->ecdev);
+			ccat_eth_priv_free_dma(priv);
+			free_netdev(netdev);
+			return NULL;
+		}
+		return priv;
+	}
+
+	/* EtherCAT disabled -> prepare normal ethernet mode */
+	priv->carrier_off = netif_carrier_off;
+	priv->carrier_on = netif_carrier_on;
+	priv->kfree_skb_any = dev_kfree_skb_any;
+	priv->start_queue = netif_start_queue;
+	priv->stop_queue = netif_stop_queue;
+	priv->tx_fifo_full = ccat_eth_tx_fifo_full;
+	priv->unregister = unregister_netdev;
+	if (register_netdev(netdev)) {
+		pr_info("unable to register network device.\n");
+		ccat_eth_priv_free_dma(priv);
+		free_netdev(netdev);
+		return NULL;
+	}
+	pr_info("registered %s as network device.\n", netdev->name);
+	priv->rx_thread = kthread_run(run_rx_thread, netdev, "%s_rx", DRV_NAME);
+	priv->tx_thread = kthread_run(run_tx_thread, netdev, "%s_tx", DRV_NAME);
+	return priv;
+}
+
+void ccat_eth_remove(struct ccat_eth_priv *const priv)
+{
+	if (priv->rx_thread) {
+		kthread_stop(priv->rx_thread);
+	}
+	if (priv->tx_thread) {
+		kthread_stop(priv->tx_thread);
+	}
+	priv->unregister(priv->netdev);
+	ccat_eth_priv_free_dma(priv);
+	free_netdev(priv->netdev);
+	pr_debug("%s(): done\n", __FUNCTION__);
+}
+
+static int ccat_eth_open(struct net_device *dev)
+{
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	priv->carrier_off(dev);
+	priv->poll_thread =
+	    kthread_run(run_poll_thread, dev, "%s_poll", DRV_NAME);
+
+	//TODO
+	return 0;
+}
+
+static const size_t CCATRXDESC_HEADER_LEN = 20;
+static void ccat_eth_receive(struct net_device *const dev,
+			     const struct ccat_eth_frame *const frame)
+{
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	const size_t len = frame->length - CCATRXDESC_HEADER_LEN;
+	struct sk_buff *skb = dev_alloc_skb(len + NET_IP_ALIGN);
+	if (!skb) {
+		pr_info("%s() out of memory :-(\n", __FUNCTION__);
+		atomic64_inc(&priv->rx_dropped);
+		return;
+	}
+	skb->dev = dev;
+	skb_reserve(skb, NET_IP_ALIGN);
+	skb_copy_to_linear_data(skb, frame->data, len);
+	skb_put(skb, len);
+	skb->protocol = eth_type_trans(skb, dev);
+	skb->ip_summed = CHECKSUM_UNNECESSARY;
+	atomic64_add(len, &priv->rx_bytes);
+	netif_rx(skb);
+}
+
+/**
+ * Rx handler in EtherCAT operation mode
+ * priv->ecdev should always be valid!
+ */
+static void ec_poll(struct net_device *dev)
+{
+	static size_t next = 0;
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	struct ccat_eth_frame *frame =
+	    ((struct ccat_eth_frame *)priv->rx_fifo.dma.virt) + next;
+	if (frame->received) {
+		ecdev_receive(priv->ecdev, frame->data,
+			      frame->length - CCATRXDESC_HEADER_LEN);
+		frame->received = 0;
+		ccat_eth_rx_fifo_add(frame, &priv->rx_fifo);
+		next = (next + 1) % FIFO_LENGTH;
+	} else {
+		//TODO dev_warn(&dev->dev, "%s(): frame was not ready\n", __FUNCTION__);
+	}
+}
+
+static netdev_tx_t ccat_eth_start_xmit(struct sk_buff *skb,
+				       struct net_device *dev)
+{
+	static size_t next = 0;
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	struct ccat_eth_frame *const frame =
+	    ((struct ccat_eth_frame *)priv->tx_fifo.dma.virt);
+	uint32_t addr_and_length;
+
+	if (skb_is_nonlinear(skb)) {
+		pr_warn("Non linear skb not supported -> drop frame.\n");
+		atomic64_inc(&priv->tx_dropped);
+		priv->kfree_skb_any(skb);
+		return NETDEV_TX_OK;
+	}
+
+	if (skb->len > sizeof(frame->data)) {
+		pr_warn("skb.len %llu exceeds dma buffer %llu -> drop frame.\n",
+			(uint64_t) skb->len, (uint64_t) sizeof(frame->data));
+		atomic64_inc(&priv->tx_dropped);
+		priv->kfree_skb_any(skb);
+		return NETDEV_TX_OK;
+	}
+
+	if (!frame[next].sent) {
+		netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
+		ccat_eth_tx_fifo_full(dev, &frame[next]);
+		return NETDEV_TX_BUSY;
+	}
+
+	/* prepare frame in DMA memory */
+	frame[next].sent = 0;
+	frame[next].length = skb->len;
+	memcpy(frame[next].data, skb->data, skb->len);
+
+	priv->kfree_skb_any(skb);
+
+	addr_and_length = 8 + (next * sizeof(*frame));
+	addr_and_length +=
+	    ((frame[next].length + sizeof(CCAT_HEADER_TAG) + 8) / 8) << 24;
+	iowrite32(addr_and_length, priv->reg.tx_fifo);	/* add to DMA fifo */
+	atomic64_add(frame[next].length, &priv->tx_bytes);	/* update stats */
+
+	next = (next + 1) % FIFO_LENGTH;
+	/* stop queue if tx ring is full */
+	if (!frame[next].sent) {
+		ccat_eth_tx_fifo_full(dev, &frame[next]);
+	}
+	return NETDEV_TX_OK;
+}
+
+static int ccat_eth_stop(struct net_device *dev)
+{
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	priv->stop_queue(dev);
+	if (priv->poll_thread) {
+		/* TODO care about smp context? */
+		kthread_stop(priv->poll_thread);
+		priv->poll_thread = NULL;
+	}
+	netdev_info(dev, "stopped.\n");
+	return 0;
+}
+
+static void ccat_eth_link_down(struct net_device *dev)
+{
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	priv->stop_queue(dev);
+	priv->carrier_off(dev);
+	netdev_info(dev, "NIC Link is Down\n");
+}
+
+static void ccat_eth_link_up(struct net_device *const dev)
+{
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	netdev_info(dev, "NIC Link is Up\n");
+	/* TODO netdev_info(dev, "NIC Link is Up %u Mbps %s Duplex\n",
+	   speed == SPEED_100 ? 100 : 10,
+	   cmd.duplex == DUPLEX_FULL ? "Full" : "Half"); */
+
+	ccat_eth_dma_fifo_reset(&priv->rx_fifo);
+	ccat_eth_dma_fifo_reset(&priv->tx_fifo);
+	ccat_eth_xmit_raw(dev, frameForwardEthernetFrames,
+			  sizeof(frameForwardEthernetFrames));
+	priv->carrier_on(dev);
+	priv->start_queue(dev);
+}
+
+/**
+ * Function to transmit a raw buffer to the network (f.e. frameForwardEthernetFrames)
+ * @dev a valid net_device
+ * @data pointer to your raw buffer
+ * @len number of bytes in the raw buffer to transmit
+ */
+static void ccat_eth_xmit_raw(struct net_device *dev, const char *const data,
+			      size_t len)
+{
+	struct sk_buff *skb = dev_alloc_skb(len);
+	skb->dev = dev;
+	skb_copy_to_linear_data(skb, data, len);
+	skb_put(skb, len);
+	ccat_eth_start_xmit(skb, dev);
+}
+
+/**
+ * Since CCAT doesn't support interrupts until now, we have to poll
+ * some status bits to recognize things like link change etc.
+ */
+static int run_poll_thread(void *data)
+{
+	struct net_device *const dev = (struct net_device *)data;
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	size_t link = 0;
+
+	while (!kthread_should_stop()) {
+		if (ccat_eth_priv_read_link_state(priv) != link) {
+			link = !link;
+			link ? ccat_eth_link_up(dev) : ccat_eth_link_down(dev);
+		}
+		usleep_range(POLL_DELAY_RANGE_USECS);
+	}
+	pr_debug("%s() stopped.\n", __FUNCTION__);
+	return 0;
+}
+
+static int run_rx_thread(void *data)
+{
+	struct net_device *const dev = (struct net_device *)data;
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+	struct ccat_eth_frame *frame = priv->rx_fifo.dma.virt;
+	const struct ccat_eth_frame *const end = frame + FIFO_LENGTH;
+
+	while (!kthread_should_stop()) {
+		/* wait until frame was used by DMA for Rx */
+		while (!kthread_should_stop() && !frame->received) {
+			usleep_range(DMA_POLL_DELAY_RANGE_USECS);
+		}
+
+		/* can be NULL, if we are asked to stop! */
+		if (frame->received) {
+			ccat_eth_receive(dev, frame);
+			frame->received = 0;
+			ccat_eth_rx_fifo_add(frame, &priv->rx_fifo);
+		}
+		if (++frame >= end) {
+			frame = priv->rx_fifo.dma.virt;
+		}
+	}
+	pr_debug("%s() stopped.\n", __FUNCTION__);
+	return 0;
+}
+
+/**
+ * Polling of tx dma descriptors in ethernet operating mode
+ */
+static int run_tx_thread(void *data)
+{
+	struct net_device *const dev = (struct net_device *)data;
+	struct ccat_eth_priv *const priv = netdev_priv(dev);
+
+	set_current_state(TASK_INTERRUPTIBLE);
+	while (!kthread_should_stop()) {
+		const struct ccat_eth_frame *const frame = priv->next_tx_frame;
+		if (frame) {
+			while (!kthread_should_stop() && !frame->sent) {
+				usleep_range(DMA_POLL_DELAY_RANGE_USECS);
+			}
+		}
+		netif_wake_queue(dev);
+		schedule();
+		set_current_state(TASK_INTERRUPTIBLE);
+	}
+	set_current_state(TASK_RUNNING);
+	pr_debug("%s() stopped.\n", __FUNCTION__);
+	return 0;
+}
--- a/devices/ccat/netdev.h	Fri Apr 04 08:32:09 2014 +0200
+++ b/devices/ccat/netdev.h	Fri Apr 04 08:59:37 2014 +0200
@@ -1,1 +1,26 @@
-../../../ccat/netdev.h
\ No newline at end of file
+/**
+    Network Driver for Beckhoff CCAT communication controller
+    Copyright (C) 2014  Beckhoff Automation GmbH
+    Author: Patrick Bruenn <p.bruenn@beckhoff.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef _NETDEV_H_
+#define _NETDEV_H_
+extern struct ccat_eth_priv *ccat_eth_init(const struct ccat_device *ccatdev,
+					   const void __iomem * addr);
+extern void ccat_eth_remove(struct ccat_eth_priv *priv);
+#endif /* #ifndef _NETDEV_H_ */
--- a/devices/ccat/print-3.4-ethercat.c	Fri Apr 04 08:32:09 2014 +0200
+++ b/devices/ccat/print-3.4-ethercat.c	Fri Apr 04 08:59:37 2014 +0200
@@ -1,1 +1,180 @@
-../../../ccat/print.c
\ No newline at end of file
+/**
+    Network Driver for Beckhoff CCAT communication controller
+    Copyright (C) 2014  Beckhoff Automation GmbH
+    Author: Patrick Bruenn <p.bruenn@beckhoff.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include <linux/kernel.h>
+#include "CCatDefinitions.h"
+#include "module.h"
+#include "print.h"
+
+#define TESTING_ENABLED 1
+void print_mem(const unsigned char *p, size_t lines)
+{
+#if TESTING_ENABLED
+	pr_info("mem at: %p\n", p);
+	pr_info(" 0  1  2  3  4  5  6  7   8  9  A  B  C  D  E  F\n");
+	while (lines > 0) {
+		pr_info
+		    ("%02x %02x %02x %02x %02x %02x %02x %02x  %02x %02x %02x %02x %02x %02x %02x %02x\n",
+		     p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8], p[9],
+		     p[10], p[11], p[12], p[13], p[14], p[15]);
+		p += 16;
+		--lines;
+	}
+#endif /* #if TESTING_ENABLED */
+}
+
+static const char *CCatFunctionTypes[CCATINFO_MAX + 1] = {
+	"not used",
+	"Informationblock",
+	"EtherCAT Slave",
+	"EtherCAT Master without DMA",
+	"Ethernet MAC without DMA",
+	"Ethernet Switch",
+	"Sercos III",
+	"Profibus",
+	"CAN Controller",
+	"KBUS Master",
+	"IP-Link Master (planned)",
+	"SPI Master",
+	"I²C",
+	"GPIO",
+	"Drive",
+	"CCAT Update",
+	"Systemtime",
+	"Interrupt Controller",
+	"EEPROM Controller",
+	"DMA Controller",
+	"EtherCAT Master with DMA",
+	"Ethernet MAC with DMA",
+	"SRAM Interface",
+	"Internal Copy block",
+	"unknown"
+};
+
+static void print_CCatDmaRxActBuf(const struct ccat_eth_priv *const priv)
+{
+	CCatDmaRxActBuf rx_fifo;
+	memcpy_fromio(&rx_fifo, priv->reg.rx_fifo, sizeof(rx_fifo));
+	pr_debug("Rx FIFO base address: %p\n", priv->reg.rx_fifo);
+	pr_debug("     Rx Frame Header start:   0x%08x\n", rx_fifo.startAddr);
+	pr_debug("     reserved:                0x%08x\n", rx_fifo.reserved1);
+	pr_debug("     Rx start address valid:    %8u\n", rx_fifo.nextValid);
+	pr_debug("     reserved:                0x%08x\n", rx_fifo.reserved2);
+	pr_debug("     FIFO level:              0x%08x\n", rx_fifo.FifoLevel);
+	pr_debug("     Buffer level:            0x%08x\n", rx_fifo.bufferLevel);
+	pr_debug("     next address:            0x%08x\n", rx_fifo.nextAddr);
+}
+
+static void print_CCatDmaTxFifo(const struct ccat_eth_priv *const priv)
+{
+	CCatDmaTxFifo tx_fifo;
+	memcpy_fromio(&tx_fifo, priv->reg.tx_fifo, sizeof(tx_fifo));
+	pr_debug("Tx FIFO base address: %p\n", priv->reg.tx_fifo);
+	pr_debug("     Tx Frame Header start:   0x%08x\n", tx_fifo.startAddr);
+	pr_debug("     # 64 bit words:          %10d\n", tx_fifo.numQuadWords);
+	pr_debug("     reserved:                0x%08x\n", tx_fifo.reserved1);
+	pr_debug("     FIFO reset:              0x%08x\n", tx_fifo.fifoReset);
+}
+
+static void print_CCatInfoBlock(const CCatInfoBlock * info,
+				const void __iomem * const base_addr)
+{
+	const size_t index = min((int)info->eCCatInfoType, CCATINFO_MAX);
+	pr_debug("%s\n", CCatFunctionTypes[index]);
+	pr_debug("     revision:     0x%x\n", info->nRevision);
+	pr_debug("     RX channel:   %d\n", info->rxDmaChn);
+	pr_debug("     TX channel:   %d\n", info->txDmaChn);
+	pr_debug("     baseaddr:     0x%x\n", info->nAddr);
+	pr_debug("     size:         0x%x\n", info->nSize);
+	pr_debug("     subfunction:  %p\n", base_addr);
+}
+
+static void print_CCatMacRegs(const struct ccat_eth_priv *const priv)
+{
+	CCatMacRegs mac;
+	memcpy_fromio(&mac, priv->reg.mac, sizeof(mac));
+	pr_debug("MAC base address: %p\n", priv->reg.mac);
+	pr_debug("     frame length error count:   %10d\n", mac.frameLenErrCnt);
+	pr_debug("     RX error count:             %10d\n", mac.rxErrCnt);
+	pr_debug("     CRC error count:            %10d\n", mac.crcErrCnt);
+	pr_debug("     Link lost error count:      %10d\n", mac.linkLostErrCnt);
+	pr_debug("     reserved:                   0x%08x\n", mac.reserved1);
+	pr_debug("     RX overflow count:          %10d\n",
+		 mac.dropFrameErrCnt);
+	pr_debug("     DMA overflow count:         %10d\n", mac.reserved2[0]);
+	//pr_debug("     reserverd:         %10d\n", DRV_NAME, mac.reserved2[1]);
+	pr_debug("     TX frame counter:           %10d\n", mac.txFrameCnt);
+	pr_debug("     RX frame counter:           %10d\n", mac.rxFrameCnt);
+	pr_debug("     TX-FIFO level:              0x%08x\n", mac.txFifoLevel);
+	pr_debug("     MII connection:             0x%08x\n", mac.miiConnected);
+}
+
+static void print_CCatMii(const struct ccat_eth_priv *const priv)
+{
+	CCatMii mii;
+	memcpy_fromio(&mii, priv->reg.mii, sizeof(mii));
+	pr_debug("MII base address: %p\n", priv->reg.mii);
+	pr_debug("     MII cycle:    %s\n",
+		 mii.startMiCycle ? "running" : "no cycle");
+	pr_debug("     reserved:     0x%x\n", mii.reserved1);
+	pr_debug("     cmd valid:    %s\n", mii.cmdErr ? "no" : "yes");
+	pr_debug("     cmd:          0x%x\n", mii.cmd);
+	pr_debug("     reserved:     0x%x\n", mii.reserved2);
+	pr_debug("     PHY addr:     0x%x\n", mii.phyAddr);
+	pr_debug("     reserved:     0x%x\n", mii.reserved3);
+	pr_debug("     PHY reg:      0x%x\n", mii.phyReg);
+	pr_debug("     reserved:     0x%x\n", mii.reserved4);
+	pr_debug("     PHY write:    0x%x\n", mii.phyWriteData);
+	pr_debug("     PHY read:     0x%x\n", mii.phyReadData);
+	pr_debug("     MAC addr:     %02x:%02x:%02x:%02x:%02x:%02x\n",
+		 mii.macAddr.b[0], mii.macAddr.b[1], mii.macAddr.b[2],
+		 mii.macAddr.b[3], mii.macAddr.b[4], mii.macAddr.b[5]);
+	pr_debug("     MAC filter enable:   %s\n",
+		 mii.macFilterEnabled ? "enabled" : "disabled");
+	pr_debug("     reserved:     0x%x\n", mii.reserved6);
+	pr_debug("     Link State:   %s\n",
+		 mii.linkStatus ? "link" : "no link");
+	pr_debug("     reserved:     0x%x\n", mii.reserved7);
+	//pr_debug("     reserved:     0x%x\n", DRV_NAME, mii.reserved8);
+	//TODO add leds, systemtime insertion and interrupts
+}
+
+void ccat_print_function_info(struct ccat_eth_priv *priv)
+{
+	print_CCatInfoBlock(&priv->info, priv->ccatdev->bar[0].ioaddr);
+	print_CCatMii(priv);
+	print_CCatDmaTxFifo(priv);
+	print_CCatDmaRxActBuf(priv);
+	print_CCatMacRegs(priv);
+	pr_debug("  RX window:    %p\n", priv->reg.rx_mem);
+	pr_debug("  TX memory:    %p\n", priv->reg.tx_mem);
+	pr_debug("  misc:         %p\n", priv->reg.misc);
+}
+
+void print_update_info(const CCatInfoBlock * const info,
+		       void __iomem * const ioaddr)
+{
+	const size_t index = min((int)info->eCCatInfoType, CCATINFO_MAX);
+	pr_debug("%s\n", CCatFunctionTypes[index]);
+	pr_debug("     revision:     0x%x\n", info->nRevision);
+	pr_debug("     baseaddr:     0x%x\n", info->nAddr);
+	pr_debug("     size:         0x%x\n", info->nSize);
+	pr_debug("     PROM ID is:   0x%x\n", ccat_get_prom_id(ioaddr));
+}
--- a/devices/ccat/print.h	Fri Apr 04 08:32:09 2014 +0200
+++ b/devices/ccat/print.h	Fri Apr 04 08:59:37 2014 +0200
@@ -1,1 +1,30 @@
-../../../ccat/print.h
\ No newline at end of file
+/**
+    Network Driver for Beckhoff CCAT communication controller
+    Copyright (C) 2014  Beckhoff Automation GmbH
+    Author: Patrick Bruenn <p.bruenn@beckhoff.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef _PRINT_H_
+#define _PRINT_H_
+
+#include "update.h"
+
+extern void ccat_print_function_info(struct ccat_eth_priv *priv);
+extern void print_mem(const unsigned char *p, size_t lines);
+extern void print_update_info(const CCatInfoBlock * const info,
+			      void __iomem * const ioaddr);
+#endif /* #ifndef _PRINT_H_ */
--- a/devices/ccat/update-3.4-ethercat.c	Fri Apr 04 08:32:09 2014 +0200
+++ b/devices/ccat/update-3.4-ethercat.c	Fri Apr 04 08:59:37 2014 +0200
@@ -1,1 +1,458 @@
-../../../ccat/update.c
\ No newline at end of file
+/**
+    Network Driver for Beckhoff CCAT communication controller
+    Copyright (C) 2014  Beckhoff Automation GmbH
+    Author: Patrick Bruenn <p.bruenn@beckhoff.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/uaccess.h>
+
+#include "module.h"
+#include "print.h"
+#include "update.h"
+
+#define CCAT_DATA_IN_4 0x038
+#define CCAT_DATA_IN_N 0x7F0
+#define CCAT_DATA_OUT_4 0x030
+#define CCAT_DATA_BLOCK_SIZE (size_t)((CCAT_DATA_IN_N - CCAT_DATA_IN_4)/8)
+#define CCAT_WRITE_BLOCK_SIZE 128
+#define CCAT_FLASH_SIZE (size_t)0xE0000
+
+/**     FUNCTION_NAME            CMD,  CLOCKS          */
+#define CCAT_BULK_ERASE          0xE3, 8
+#define CCAT_GET_PROM_ID         0xD5, 40
+#define CCAT_READ_FLASH          0xC0, 32
+#define CCAT_READ_STATUS         0xA0, 16
+#define CCAT_WRITE_ENABLE        0x60, 8
+#define CCAT_WRITE_FLASH         0x40, 32
+
+/* from http://graphics.stanford.edu/~seander/bithacks.html#ReverseByteWith32Bits */
+#define SWAP_BITS(B) \
+	((((B) * 0x0802LU & 0x22110LU) | ((B) * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16)
+
+/**
+ * struct update_buffer - keep track of a CCAT FPGA update
+ * @update: pointer to a valid ccat_update object
+ * @data: buffer used for write operations
+ * @size: number of bytes written to the data buffer, if 0 on ccat_update_release() no data will be written to FPGA
+ */
+struct update_buffer {
+	struct ccat_update *update;
+	char data[CCAT_FLASH_SIZE];
+	size_t size;
+};
+
+static void ccat_wait_status_cleared(void __iomem * const ioaddr);
+static int ccat_read_flash(void __iomem * const ioaddr, char __user * buf,
+			   uint32_t len, loff_t * off);
+static void ccat_write_flash(const struct update_buffer *const buf);
+static void ccat_update_cmd(void __iomem * const ioaddr, uint8_t cmd,
+			    uint16_t clocks);
+static void ccat_update_destroy(struct kref *ref);
+
+/**
+ * wait_until_busy_reset() - wait until the busy flag was reset
+ * @ioaddr: address of the CCAT Update function in PCI config space
+ */
+static inline void wait_until_busy_reset(void __iomem * const ioaddr)
+{
+	wmb();
+	while (ioread8(ioaddr + 1)) {
+		schedule();
+	}
+}
+
+static int ccat_update_open(struct inode *const i, struct file *const f)
+{
+	struct ccat_update *update =
+	    container_of(i->i_cdev, struct ccat_update, cdev);
+	struct update_buffer *buf;
+	kref_get(&update->refcount);
+	if (atomic_read(&update->refcount.refcount) > 2) {
+		kref_put(&update->refcount, ccat_update_destroy);
+		return -EBUSY;
+	}
+
+	buf = kzalloc(sizeof(*buf), GFP_KERNEL);
+	if (!buf) {
+		kref_put(&update->refcount, ccat_update_destroy);
+		return -ENOMEM;
+	}
+
+	buf->update = update;
+	f->private_data = buf;
+	return 0;
+}
+
+static int ccat_update_release(struct inode *const i, struct file *const f)
+{
+	const struct update_buffer *const buf = f->private_data;
+	struct ccat_update *const update = buf->update;
+	if (buf->size > 0) {
+		ccat_update_cmd(update->ioaddr, CCAT_WRITE_ENABLE);
+		ccat_update_cmd(update->ioaddr, CCAT_BULK_ERASE);
+		ccat_wait_status_cleared(update->ioaddr);
+		ccat_write_flash(buf);
+	}
+	kfree(f->private_data);
+	kref_put(&update->refcount, ccat_update_destroy);
+	return 0;
+}
+
+/**
+ * ccat_update_read() - Read CCAT configuration data from flash
+ * @f: file handle previously initialized with ccat_update_open()
+ * @buf: buffer in user space provided for our data
+ * @len: length of the user space buffer
+ * @off: current offset of our file operation
+ *
+ * Copies data from the CCAT FPGA's configuration flash to user space.
+ * Note that the size of the FPGA's firmware is not known exactly so it
+ * is very possible that the overall buffer ends with a lot of 0xff.
+ *
+ * Return: the number of bytes written, or 0 if EOF reached
+ */
+static ssize_t ccat_update_read(struct file *const f, char __user * buf,
+				size_t len, loff_t * off)
+{
+	struct update_buffer *update = f->private_data;
+	if (!buf || !off) {
+		return -EINVAL;
+	}
+	if (*off >= CCAT_FLASH_SIZE) {
+		return 0;
+	}
+	if (*off + len >= CCAT_FLASH_SIZE) {
+		len = CCAT_FLASH_SIZE - *off;
+	}
+	return ccat_read_flash(update->update->ioaddr, buf, len, off);
+}
+
+/**
+ * ccat_update_write() - Write data to the CCAT FPGA's configuration flash
+ * @f: file handle previously initialized with ccat_update_open()
+ * @buf: buffer in user space providing the new configuration data (from *.rbf)
+ * @len: length of the user space buffer
+ * @off: current offset in the configuration data
+ *
+ * Copies data from user space (possibly a *.rbf) to the CCAT FPGA's
+ * configuration flash to user space.
+ *
+ * Return: the number of bytes written, or 0 if flash end is reached
+ */
+
+static ssize_t ccat_update_write(struct file *const f, const char __user * buf,
+				 size_t len, loff_t * off)
+{
+	struct update_buffer *const update = f->private_data;
+	if (*off + len > sizeof(update->data))
+		return 0;
+
+	copy_from_user(update->data + *off, buf, len);
+	*off += len;
+	update->size = *off;
+	return len;
+}
+
+static struct file_operations update_ops = {
+	.owner = THIS_MODULE,
+	.open = ccat_update_open,
+	.release = ccat_update_release,
+	.read = ccat_update_read,
+	.write = ccat_update_write,
+};
+
+/**
+ * __ccat_update_cmd() - Helper to issue a FPGA flash command
+ * @ioaddr: address of the CCAT Update function in PCI config space
+ * @cmd: the command identifier
+ * @clocks: the number of clocks associated with the specified command
+ *
+ * no write memory barrier is called and the busy flag is not evaluated
+ */
+static inline void __ccat_update_cmd(void __iomem * const ioaddr, uint8_t cmd,
+				     uint16_t clocks)
+{
+	iowrite8((0xff00 & clocks) >> 8, ioaddr);
+	iowrite8(0x00ff & clocks, ioaddr + 0x8);
+	iowrite8(cmd, ioaddr + 0x10);
+}
+
+/**
+ * ccat_update_cmd() - Helper to issue a FPGA flash command
+ * @ioaddr: address of the CCAT Update function in PCI config space
+ * @cmd: the command identifier
+ * @clocks: the number of clocks associated with the specified command
+ *
+ * Triggers a full flash command cycle with write memory barrier and
+ * command activate. This call blocks until the busy flag is reset.
+ */
+static inline void ccat_update_cmd(void __iomem * const ioaddr, uint8_t cmd,
+				   uint16_t clocks)
+{
+	__ccat_update_cmd(ioaddr, cmd, clocks);
+	wmb();
+	iowrite8(0xff, ioaddr + 0x7f8);
+	wait_until_busy_reset(ioaddr);
+}
+
+/**
+ * ccat_update_cmd_addr() - Helper to issue a FPGA flash command with address parameter
+ * @ioaddr: address of the CCAT Update function in PCI config space
+ * @cmd: the command identifier
+ * @clocks: the number of clocks associated with the specified command
+ * @addr: 24 bit address associated with the specified command
+ *
+ * Triggers a full flash command cycle with write memory barrier and
+ * command activate. This call blocks until the busy flag is reset.
+ */
+static inline void ccat_update_cmd_addr(void __iomem * const ioaddr,
+					uint8_t cmd, uint16_t clocks,
+					uint32_t addr)
+{
+	const uint8_t addr_0 = SWAP_BITS(addr & 0xff);
+	const uint8_t addr_1 = SWAP_BITS((addr & 0xff00) >> 8);
+	const uint8_t addr_2 = SWAP_BITS((addr & 0xff0000) >> 16);
+	__ccat_update_cmd(ioaddr, cmd, clocks);
+	iowrite8(addr_2, ioaddr + 0x18);
+	iowrite8(addr_1, ioaddr + 0x20);
+	iowrite8(addr_0, ioaddr + 0x28);
+	wmb();
+	iowrite8(0xff, ioaddr + 0x7f8);
+	wait_until_busy_reset(ioaddr);
+}
+
+/**
+ * ccat_get_prom_id() - Read CCAT PROM ID
+ * @ioaddr: address of the CCAT Update function in PCI config space
+ *
+ * Return: the CCAT FPGA's PROM identifier
+ */
+uint8_t ccat_get_prom_id(void __iomem * const ioaddr)
+{
+	ccat_update_cmd(ioaddr, CCAT_GET_PROM_ID);
+	return ioread8(ioaddr + 0x38);
+}
+
+/**
+ * ccat_get_status() - Read CCAT Update status
+ * @ioaddr: address of the CCAT Update function in PCI config space
+ *
+ * Return: the current status of the CCAT Update function
+ */
+static uint8_t ccat_get_status(void __iomem * const ioaddr)
+{
+	ccat_update_cmd(ioaddr, CCAT_READ_STATUS);
+	return ioread8(ioaddr + 0x20);
+}
+
+/**
+ * ccat_wait_status_cleared() - wait until CCAT status is cleared
+ * @ioaddr: address of the CCAT Update function in PCI config space
+ *
+ * Blocks until bit 7 of the CCAT Update status is reset
+ */
+
+static void ccat_wait_status_cleared(void __iomem * const ioaddr)
+{
+	uint8_t status;
+	do {
+		status = ccat_get_status(ioaddr);
+	} while (status & (1 << 7));
+}
+
+/**
+ * ccat_read_flash_block() - Read a block of CCAT configuration data from flash
+ * @ioaddr: address of the CCAT Update function in PCI config space
+ * @addr: 24 bit address of the block to read
+ * @len: number of bytes to read from this block, len <= CCAT_DATA_BLOCK_SIZE
+ * @buf: output buffer in user space
+ *
+ * Copies one block of configuration data from the CCAT FPGA's flash to
+ * the user space buffer.
+ * Note that the size of the FPGA's firmware is not known exactly so it
+ * is very possible that the overall buffer ends with a lot of 0xff.
+ *
+ * Return: the number of bytes copied
+ */
+static int ccat_read_flash_block(void __iomem * const ioaddr,
+				 const uint32_t addr, const uint16_t len,
+				 char __user * const buf)
+{
+	uint16_t i;
+	const uint16_t clocks = 8 * len;
+	ccat_update_cmd_addr(ioaddr, CCAT_READ_FLASH + clocks, addr);
+	for (i = 0; i < len; i++) {
+		put_user(ioread8(ioaddr + CCAT_DATA_IN_4 + 8 * i), buf + i);
+	}
+	return len;
+}
+
+/**
+ * ccat_read_flash() - Read a chunk of CCAT configuration data from flash
+ * @ioaddr: address of the CCAT Update function in PCI config space
+ * @buf: output buffer in user space
+ * @len: number of bytes to read
+ * @off: offset in the configuration data
+ *
+ * Copies multiple blocks of configuration data from the CCAT FPGA's
+ * flash to the user space buffer.
+ *
+ * Return: the number of bytes copied
+ */
+static int ccat_read_flash(void __iomem * const ioaddr, char __user * buf,
+			   uint32_t len, loff_t * off)
+{
+	const loff_t start = *off;
+	while (len > CCAT_DATA_BLOCK_SIZE) {
+		*off +=
+		    ccat_read_flash_block(ioaddr, *off, CCAT_DATA_BLOCK_SIZE,
+					  buf);
+		buf += CCAT_DATA_BLOCK_SIZE;
+		len -= CCAT_DATA_BLOCK_SIZE;
+	}
+	*off += ccat_read_flash_block(ioaddr, *off, len, buf);
+	return *off - start;
+}
+
+/**
+ * ccat_write_flash_block() - Write a block of CCAT configuration data to flash
+ * @ioaddr: address of the CCAT Update function in PCI config space
+ * @addr: 24 bit start address in the CCAT FPGA's flash
+ * @len: number of bytes to write in this block, len <= CCAT_WRITE_BLOCK_SIZE
+ * @buf: input buffer
+ *
+ * Copies one block of configuration data to the CCAT FPGA's flash
+ *
+ * Return: the number of bytes copied
+ */
+static int ccat_write_flash_block(void __iomem * const ioaddr,
+				  const uint32_t addr, const uint16_t len,
+				  const char *const buf)
+{
+	const uint16_t clocks = 8 * len;
+	uint16_t i;
+	ccat_update_cmd(ioaddr, CCAT_WRITE_ENABLE);
+	for (i = 0; i < len; i++) {
+		iowrite8(buf[i], ioaddr + CCAT_DATA_OUT_4 + 8 * i);
+	}
+	ccat_update_cmd_addr(ioaddr, CCAT_WRITE_FLASH + clocks, addr);
+	ccat_wait_status_cleared(ioaddr);
+	return len;
+}
+
+/**
+ * ccat_write_flash() - Write a new CCAT configuration to FPGA's flash
+ * @update: a CCAT Update buffer containing the new FPGA configuration
+ */
+static void ccat_write_flash(const struct update_buffer *const update)
+{
+	const char *buf = update->data;
+	uint32_t off = 0;
+	size_t len = update->size;
+	while (len > CCAT_WRITE_BLOCK_SIZE) {
+		ccat_write_flash_block(update->update->ioaddr, off,
+				       (uint16_t) CCAT_WRITE_BLOCK_SIZE, buf);
+		off += CCAT_WRITE_BLOCK_SIZE;
+		buf += CCAT_WRITE_BLOCK_SIZE;
+		len -= CCAT_WRITE_BLOCK_SIZE;
+	}
+	ccat_write_flash_block(update->update->ioaddr, off, (uint16_t) len,
+			       buf);
+}
+
+/**
+ * ccat_update_init() - Initialize the CCAT Update function
+ */
+struct ccat_update *ccat_update_init(const struct ccat_device *const ccatdev,
+				     void __iomem * const addr)
+{
+	struct ccat_update *const update = kzalloc(sizeof(*update), GFP_KERNEL);
+	if (!update) {
+		return NULL;
+	}
+	kref_init(&update->refcount);
+	update->ioaddr = ccatdev->bar[0].ioaddr + ioread32(addr + 0x8);
+	memcpy_fromio(&update->info, addr, sizeof(update->info));
+	print_update_info(&update->info, update->ioaddr);
+
+	if (0x00 != update->info.nRevision) {
+		pr_warn("CCAT Update rev. %d not supported\n",
+			update->info.nRevision);
+		goto cleanup;
+	}
+
+	if (alloc_chrdev_region(&update->dev, 0, 1, DRV_NAME)) {
+		pr_warn("alloc_chrdev_region() failed\n");
+		goto cleanup;
+	}
+
+	update->class = class_create(THIS_MODULE, "ccat_update");
+	if (NULL == update->class) {
+		pr_warn("Create device class failed\n");
+		goto cleanup;
+	}
+
+	if (NULL ==
+	    device_create(update->class, NULL, update->dev, NULL,
+			  "ccat_update")) {
+		pr_warn("device_create() failed\n");
+		goto cleanup;
+	}
+
+	cdev_init(&update->cdev, &update_ops);
+	update->cdev.owner = THIS_MODULE;
+	update->cdev.ops = &update_ops;
+	if (cdev_add(&update->cdev, update->dev, 1)) {
+		pr_warn("add update device failed\n");
+		goto cleanup;
+	}
+	return update;
+cleanup:
+	kref_put(&update->refcount, ccat_update_destroy);
+	return NULL;
+}
+
+/**
+ * ccat_update_destroy() - Cleanup the CCAT Update function
+ * @ref: pointer to a struct kref embedded into a struct ccat_update, which we intend to destroy
+ *
+ * Retrieves the parent struct ccat_update and destroys it.
+ */
+static void ccat_update_destroy(struct kref *ref)
+{
+	struct ccat_update *update =
+	    container_of(ref, struct ccat_update, refcount);
+	cdev_del(&update->cdev);
+	device_destroy(update->class, update->dev);
+	class_destroy(update->class);
+	unregister_chrdev_region(update->dev, 1);
+	kfree(update);
+	pr_debug("%s(): done\n", __FUNCTION__);
+}
+
+/**
+ * ccat_update_remove() - Prepare the CCAT Update function for removal
+ */
+void ccat_update_remove(struct ccat_update *update)
+{
+	kref_put(&update->refcount, ccat_update_destroy);
+	pr_debug("%s(): done\n", __FUNCTION__);
+}
--- a/devices/ccat/update.h	Fri Apr 04 08:32:09 2014 +0200
+++ b/devices/ccat/update.h	Fri Apr 04 08:59:37 2014 +0200
@@ -1,1 +1,27 @@
-../../../ccat/update.h
\ No newline at end of file
+/**
+    Network Driver for Beckhoff CCAT communication controller
+    Copyright (C) 2014  Beckhoff Automation GmbH
+    Author: Patrick Bruenn <p.bruenn@beckhoff.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef _UPDATE_H_
+#define _UPDATE_H_
+extern uint8_t ccat_get_prom_id(void __iomem * const ioaddr);
+extern struct ccat_update *ccat_update_init(const struct ccat_device *ccatdev,
+					    void __iomem * addr);
+extern void ccat_update_remove(struct ccat_update *update);
+#endif /* #ifndef _UPDATE_H_ */