3

    Copyright (C) 2014 - 2015  Beckhoff Automation GmbH

    26

#ifdef CONFIG_PCI

    27

#include <asm/dma.h>

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#else

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#define free_dma(X)

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#define request_dma(X, Y) ((int)(-EINVAL))

    31

#endif

    32

    53

#define POLL_TIME ktime_set(0, 50 * NSEC_PER_USEC)

    54

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struct ccat_dma_frame_hdr {

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	__le32 reserved1;

    57

	__le32 rx_flags;

    58

#define CCAT_FRAME_RECEIVED 0x1

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	__le16 length;

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	__le16 reserved3;

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	__le32 tx_flags;

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#define CCAT_FRAME_SENT 0x1

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	__le64 timestamp;

    64

};

    65

    66

struct ccat_eim_frame_hdr {

    67

	__le16 length;

    68

	__le16 reserved3;

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	__le32 tx_flags;

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	__le64 timestamp;

    71

};

    72

    73

struct ccat_eth_frame {

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	u8 placeholder[0x800];

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};

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struct ccat_dma_frame {

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	struct ccat_dma_frame_hdr hdr;

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	u8 data[sizeof(struct ccat_eth_frame) -

    80

		sizeof(struct ccat_dma_frame_hdr)];

    81

};

    82

    83

struct ccat_eim_frame {

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	struct ccat_eim_frame_hdr hdr;

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	u8 data[sizeof(struct ccat_eth_frame) -

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		sizeof(struct ccat_eim_frame_hdr)];

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};

    88

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#define MAX_PAYLOAD_SIZE \

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	(sizeof(struct ccat_eth_frame) - max(sizeof(struct ccat_dma_frame_hdr), sizeof(struct ccat_eim_frame_hdr)))

    91

    92

/**

    93

 * struct ccat_eth_register - CCAT register addresses in the PCI BAR

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 * @mii: address of the CCAT management interface register

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 * @tx_fifo: address of the CCAT TX DMA fifo register

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 * @rx_fifo: address of the CCAT RX DMA fifo register

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 * @mac: address of the CCAT media access control register

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 * @rx_mem: address of the CCAT register holding the RX DMA address

    99

 * @tx_mem: address of the CCAT register holding the TX DMA address

   100

 * @misc: address of a CCAT register holding miscellaneous information

   101

 */

   102

struct ccat_eth_register {

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	void __iomem *mii;

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	void __iomem *tx_fifo;

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	void __iomem *rx_fifo;

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	void __iomem *mac;

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	void __iomem *rx_mem;

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	void __iomem *tx_mem;

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	void __iomem *misc;

   110

};

   111

   112

/**

   113

 * struct ccat_dma - CCAT DMA channel configuration

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 * @phys: device-viewed address(physical) of the associated DMA memory

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 * @start: CPU-viewed address(virtual) of the associated DMA memory

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 * @size: number of bytes in the associated DMA memory

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 * @channel: CCAT DMA channel number

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 * @dev: valid struct device pointer

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 */

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struct ccat_dma {

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	struct ccat_dma_frame *next;

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	void *start;

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	size_t size;

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	dma_addr_t phys;

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	size_t channel;

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	struct device *dev;

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};

   128

   129

struct ccat_eim {

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	struct ccat_eim_frame __iomem *next;

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	void __iomem *start;

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	size_t size;

   133

};

   134

   135

struct ccat_mem {

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	struct ccat_eth_frame *next;

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	void *start;

   138

};

   139

   140

/**

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 * struct ccat_eth_fifo - CCAT RX or TX DMA fifo

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 * @add: callback used to add a frame to this fifo

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 * @reg: PCI register address of this DMA fifo

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 * @dma: information about the associated DMA memory

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 */

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struct ccat_eth_fifo {

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	void (*add) (struct ccat_eth_fifo *);

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	void (*copy_to_skb) (struct ccat_eth_fifo *, struct sk_buff *, size_t);

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	void (*queue_skb) (struct ccat_eth_fifo * const, struct sk_buff *);

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	void __iomem *reg;

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	const struct ccat_eth_frame *end;

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	union {

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		struct ccat_mem mem;

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		struct ccat_dma dma;

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		struct ccat_eim eim;

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	};

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};

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   159

/**

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 * same as: typedef struct _CCatInfoBlockOffs from CCatDefinitions.h

   161

 */

   162

struct ccat_mac_infoblock {

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	u32 reserved;

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	u32 mii;

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	u32 tx_fifo;

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	u32 mac;

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	u32 rx_mem;

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	u32 tx_mem;

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	u32 misc;

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};

   171

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/**

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 * struct ccat_eth_priv - CCAT Ethernet/EtherCAT Master function (netdev)

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 * @func: pointer to the parent struct ccat_function

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 * @netdev: the net_device structure used by the kernel networking stack

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 * @info: holds a copy of the CCAT Ethernet/EtherCAT Master function information block (read from PCI config space)

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 * @reg: register addresses in PCI config space of the Ethernet/EtherCAT Master function

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 * @rx_fifo: DMA fifo used for RX DMA descriptors

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 * @tx_fifo: DMA fifo used for TX DMA descriptors

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 * @poll_timer: interval timer used to poll CCAT for events like link changed, rx done, tx done

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 * @rx_bytes: number of bytes received -> reported with ndo_get_stats64()

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 * @rx_dropped: number of received frames, which were dropped -> reported with ndo_get_stats64()

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 * @tx_bytes: number of bytes send -> reported with ndo_get_stats64()

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 * @tx_dropped: number of frames requested to send, which were dropped -> reported with ndo_get_stats64()

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 */

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struct ccat_eth_priv {

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	void (*free) (struct ccat_eth_priv *);

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	 bool(*tx_ready) (const struct ccat_eth_priv *);

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	 size_t(*rx_ready) (struct ccat_eth_fifo *);

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	struct ccat_function *func;

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	struct net_device *netdev;

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	struct ccat_eth_register reg;

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	struct ccat_eth_fifo rx_fifo;

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	struct ccat_eth_fifo tx_fifo;

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	struct hrtimer poll_timer;

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	atomic64_t rx_bytes;

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	atomic64_t rx_dropped;

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	atomic64_t tx_bytes;

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	atomic64_t tx_dropped;

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	ec_device_t *ecdev;

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	void (*carrier_off) (struct net_device * netdev);

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	 bool(*carrier_ok) (const struct net_device * netdev);

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	void (*carrier_on) (struct net_device * netdev);

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	void (*kfree_skb_any) (struct sk_buff * skb);

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	void (*receive) (struct ccat_eth_priv *, size_t);

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	void (*start_queue) (struct net_device * netdev);

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	void (*stop_queue) (struct net_device * netdev);

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	void (*unregister) (struct net_device * netdev);

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};

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struct ccat_mac_register {

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	/** MAC error register     @+0x0 */

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	u8 frame_len_err;

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	u8 rx_err;

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	u8 crc_err;

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	u8 link_lost_err;

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	u32 reserved1;

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	/** Buffer overflow errors @+0x8 */

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	u8 rx_mem_full;

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	u8 reserved2[7];

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	/** MAC frame counter      @+0x10 */

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	u32 tx_frames;

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	u32 rx_frames;

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	u64 reserved3;

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	/** MAC fifo level         @+0x20 */

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	u8 tx_fifo_level:7;

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	u8 reserved4:1;

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	u8 reserved5[7];

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	/** TX memory full error   @+0x28 */

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	u8 tx_mem_full;

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	u8 reserved6[7];

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	u64 reserved8[9];

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	/** Connection             @+0x78 */

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	u8 mii_connected;

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};

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static void ccat_dma_free(struct ccat_dma *const dma)

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{

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	const struct ccat_dma tmp = *dma;

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	free_dma(dma->channel);

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	memset(dma, 0, sizeof(*dma));

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	dma_free_coherent(tmp.dev, tmp.size, tmp.start, tmp.phys);

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}

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/**

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 * ccat_dma_init() - Initialize CCAT and host memory for DMA transfer

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 * @dma object for management data which will be initialized

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 * @channel number of the DMA channel

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 * @ioaddr of the pci bar2 configspace used to calculate the address of the pci dma configuration

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 * @dev which should be configured for DMA

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 */

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static int ccat_dma_init(struct ccat_dma *const dma, size_t channel,

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			 void __iomem * const ioaddr, struct device *const dev)

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{

   256

	void *frame;

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	u64 addr;

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	u32 translateAddr;

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	u32 memTranslate;

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	u32 memSize;

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	u32 data = 0xffffffff;

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	u32 offset = (sizeof(u64) * channel) + 0x1000;

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	dma->channel = channel;

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	dma->dev = dev;

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   267

	/* calculate size and alignments */

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	iowrite32(data, ioaddr + offset);

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	wmb();

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	data = ioread32(ioaddr + offset);

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	memTranslate = data & 0xfffffffc;

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	memSize = (~memTranslate) + 1;

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	dma->size = 2 * memSize - PAGE_SIZE;

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	dma->start =

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	    dma_zalloc_coherent(dev, dma->size, &dma->phys, GFP_KERNEL);

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	if (!dma->start || !dma->phys) {

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		pr_info("init DMA%llu memory failed.\n", (u64) channel);

   278

		return -ENOMEM;

   279

	}

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   281

	if (request_dma(channel, KBUILD_MODNAME)) {

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		pr_info("request dma channel %llu failed\n", (u64) channel);

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		ccat_dma_free(dma);

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		return -EINVAL;

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	}

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   287

	translateAddr = (dma->phys + memSize - PAGE_SIZE) & memTranslate;

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	addr = translateAddr;

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	memcpy_toio(ioaddr + offset, &addr, sizeof(addr));

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	frame = dma->start + translateAddr - dma->phys;

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	pr_debug

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	    ("DMA%llu mem initialized\n start:         0x%p\n phys:         0x%llx\n translated:   0x%llx\n pci addr:     0x%08x%x\n memTranslate: 0x%x\n size:         %llu bytes.\n",

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	     (u64) channel, dma->start, (u64) (dma->phys), addr,

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	     ioread32(ioaddr + offset + 4), ioread32(ioaddr + offset),

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	     memTranslate, (u64) dma->size);

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	return 0;

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static void ecdev_receive_dma(struct ccat_eth_priv *const priv, size_t len)

   328

{

   329

	ecdev_receive(priv->ecdev, priv->rx_fifo.dma.next->data, len);

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}

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static void ecdev_receive_eim(struct ccat_eth_priv *const priv, size_t len)

   333

{

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	ecdev_receive(priv->ecdev, priv->rx_fifo.eim.next->data, len);

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}

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static inline bool fifo_eim_tx_ready(const struct ccat_eth_priv *const priv)

   345

{

   346

	static const size_t TX_FIFO_LEVEL_OFFSET = 0x20;

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	static const u8 TX_FIFO_LEVEL_MASK = 0x3F;

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	void __iomem *addr = priv->reg.mac + TX_FIFO_LEVEL_OFFSET;

   349

   350

	return !(ioread8(addr) & TX_FIFO_LEVEL_MASK);

   351

}

   352

   353

static inline size_t fifo_eim_rx_ready(struct ccat_eth_fifo *const fifo)

   354

{

   355

	static const size_t OVERHEAD = sizeof(struct ccat_eim_frame_hdr);

   356

	const size_t len = ioread16(&fifo->eim.next->hdr.length);

   357

   358

	return (len < OVERHEAD) ? 0 : len - OVERHEAD;

   359

}

   360

   361

static void ccat_eth_fifo_inc(struct ccat_eth_fifo *fifo)

   362

{

   363

	if (++fifo->mem.next > fifo->end)

   364

		fifo->mem.next = fifo->mem.start;

   365

}

   366

   367

static void fifo_eim_rx_add(struct ccat_eth_fifo *const fifo)

   368

{

   369

	struct ccat_eim_frame __iomem *frame = fifo->eim.next;

   370

	iowrite16(0, frame);

   371

	wmb();

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}

   373

   374

static void fifo_eim_tx_add(struct ccat_eth_fifo *const fifo)

   375

{

   376

}

   377

   378

#define memcpy_from_ccat(DEST, SRC, LEN) memcpy(DEST,(__force void*)(SRC), LEN)

   379

#define memcpy_to_ccat(DEST, SRC, LEN) memcpy((__force void*)(DEST),SRC, LEN)

   380

static void fifo_eim_copy_to_linear_skb(struct ccat_eth_fifo *const fifo,

   381

					struct sk_buff *skb, const size_t len)

   382

{

   383

	memcpy_from_ccat(skb->data, fifo->eim.next->data, len);

   384

}

   385

   386

static void fifo_eim_queue_skb(struct ccat_eth_fifo *const fifo,

   387

			       struct sk_buff *skb)

   388

{

   389

	struct ccat_eim_frame __iomem *frame = fifo->eim.next;

   390

	const u32 addr_and_length =

   391

	    (void __iomem *)frame - (void __iomem *)fifo->eim.start;

   392

   393

	const __le16 length = cpu_to_le16(skb->len);

   394

	memcpy_to_ccat(&frame->hdr.length, &length, sizeof(length));

   395

	memcpy_to_ccat(frame->data, skb->data, skb->len);

   396

	iowrite32(addr_and_length, fifo->reg);

   397

}

   398

   399

static void ccat_eth_priv_free_eim(struct ccat_eth_priv *priv)

   400

{

   401

	/* reset hw fifo's */

   402

	iowrite32(0, priv->tx_fifo.reg + 0x8);

   403

	wmb();

   404

}

   405

   406

static void ccat_eth_fifo_reset(struct ccat_eth_fifo *const fifo)

   407

{

   408

	/* reset hw fifo */

   409

	if (fifo->reg) {

   410

		iowrite32(0, fifo->reg + 0x8);

   411

		wmb();

   412

	}

   413

   414

	if (fifo->add) {

   415

		fifo->mem.next = fifo->mem.start;

   416

		do {

   417

			fifo->add(fifo);

   418

			ccat_eth_fifo_inc(fifo);

   419

		} while (fifo->mem.next != fifo->mem.start);

   420

	}

   421

}

   422

   423

static inline bool fifo_dma_tx_ready(const struct ccat_eth_priv *const priv)

   424

{

   425

	const struct ccat_dma_frame *frame = priv->tx_fifo.dma.next;

   426

	return le32_to_cpu(frame->hdr.tx_flags) & CCAT_FRAME_SENT;

   427

}

   428

   429

static inline size_t fifo_dma_rx_ready(struct ccat_eth_fifo *const fifo)

   430

{

   431

	static const size_t OVERHEAD =

   432

	    offsetof(struct ccat_dma_frame_hdr, rx_flags);

   433

	const struct ccat_dma_frame *const frame = fifo->dma.next;

   434

   435

	if (le32_to_cpu(frame->hdr.rx_flags) & CCAT_FRAME_RECEIVED) {

   436

		const size_t len = le16_to_cpu(frame->hdr.length);

   437

		return (len < OVERHEAD) ? 0 : len - OVERHEAD;

   438

	}

   439

	return 0;

   440

}

   441

   442

static void ccat_eth_rx_fifo_dma_add(struct ccat_eth_fifo *const fifo)

   443

{

   444

	struct ccat_dma_frame *const frame = fifo->dma.next;

   445

	const size_t offset = (void *)frame - fifo->dma.start;

   448

	frame->hdr.rx_flags = cpu_to_le32(0);

   452

static void ccat_eth_tx_fifo_dma_add_free(struct ccat_eth_fifo *const fifo)

   455

	fifo->dma.next->hdr.tx_flags = cpu_to_le32(CCAT_FRAME_SENT);

   456

}

   457

   458

static void fifo_dma_copy_to_linear_skb(struct ccat_eth_fifo *const fifo,

   459

					struct sk_buff *skb, const size_t len)

   460

{

   461

	skb_copy_to_linear_data(skb, fifo->dma.next->data, len);

   462

}

   463

   464

static void fifo_dma_queue_skb(struct ccat_eth_fifo *const fifo,

   465

			       struct sk_buff *skb)

   466

{

   467

	struct ccat_dma_frame *frame = fifo->dma.next;

   468

	u32 addr_and_length;

   469

   470

	frame->hdr.tx_flags = cpu_to_le32(0);

   471

	frame->hdr.length = cpu_to_le16(skb->len);

   472

   473

	memcpy(frame->data, skb->data, skb->len);

   474

   475

	/* Queue frame into CCAT TX-FIFO, CCAT ignores the first 8 bytes of the tx descriptor */

   476

	addr_and_length = offsetof(struct ccat_dma_frame_hdr, length);

   477

	addr_and_length += ((void *)frame - fifo->dma.start);

   478

	addr_and_length +=

   479

	    ((skb->len + sizeof(struct ccat_dma_frame_hdr)) / 8) << 24;

   480

	iowrite32(addr_and_length, fifo->reg);

   481

}

   482