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/**

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    Network Driver for Beckhoff CCAT communication controller

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    Copyright (C) 2014  Beckhoff Automation GmbH

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    Author: Patrick Bruenn <p.bruenn@beckhoff.com>

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    This program is free software; you can redistribute it and/or modify

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    it under the terms of the GNU General Public License as published by

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    the Free Software Foundation; either version 2 of the License, or

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    (at your option) any later version.

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    This program is distributed in the hope that it will be useful,

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    but WITHOUT ANY WARRANTY; without even the implied warranty of

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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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    GNU General Public License for more details.

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    You should have received a copy of the GNU General Public License along

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    with this program; if not, write to the Free Software Foundation, Inc.,

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    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

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*/

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#include <linux/kernel.h>

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#include <linux/module.h>

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#include <linux/sched.h>

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#include <linux/uaccess.h>

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#include "module.h"

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#define CCAT_DEVICES_MAX 5

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#define CCAT_DATA_IN_4 0x038

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#define CCAT_DATA_IN_N 0x7F0

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#define CCAT_DATA_OUT_4 0x030

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#define CCAT_DATA_BLOCK_SIZE (size_t)((CCAT_DATA_IN_N - CCAT_DATA_IN_4)/8)

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#define CCAT_WRITE_BLOCK_SIZE 128

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#define CCAT_FLASH_SIZE (size_t)0xE0000

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/**     FUNCTION_NAME            CMD,  CLOCKS          */

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#define CCAT_BULK_ERASE          0xE3, 8

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#define CCAT_GET_PROM_ID         0xD5, 40

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#define CCAT_READ_FLASH          0xC0, 32

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#define CCAT_READ_STATUS         0xA0, 16

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#define CCAT_WRITE_ENABLE        0x60, 8

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#define CCAT_WRITE_FLASH         0x40, 32

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/* from http://graphics.stanford.edu/~seander/bithacks.html#ReverseByteWith32Bits */

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#define SWAP_BITS(B) \

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	((((B) * 0x0802LU & 0x22110LU) | ((B) * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16)

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/**

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 * wait_until_busy_reset() - wait until the busy flag was reset

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 * @ioaddr: address of the CCAT Update function in PCI config space

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 */

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static inline void wait_until_busy_reset(void __iomem * const ioaddr)

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{

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	wmb();

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	while (ioread8(ioaddr + 1)) {

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		schedule();

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	}

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}

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/**

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 * __ccat_update_cmd() - Helper to issue a FPGA flash command

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 * @ioaddr: address of the CCAT Update function in PCI config space

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 * @cmd: the command identifier

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 * @clocks: the number of clocks associated with the specified command

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 *

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 * no write memory barrier is called and the busy flag is not evaluated

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 */

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static inline void __ccat_update_cmd(void __iomem * const ioaddr, u8 cmd,

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				     u16 clocks)

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{

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	iowrite8((0xff00 & clocks) >> 8, ioaddr);

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	iowrite8(0x00ff & clocks, ioaddr + 0x8);

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	iowrite8(cmd, ioaddr + 0x10);

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}

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/**

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 * ccat_update_cmd() - Helper to issue a FPGA flash command

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 * @ioaddr: address of the CCAT Update function in PCI config space

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 * @cmd: the command identifier

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 * @clocks: the number of clocks associated with the specified command

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 *

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 * Triggers a full flash command cycle with write memory barrier and

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 * command activate. This call blocks until the busy flag is reset.

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 */

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static inline void ccat_update_cmd(void __iomem * const ioaddr, u8 cmd,

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				   u16 clocks)

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{

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	__ccat_update_cmd(ioaddr, cmd, clocks);

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	wmb();

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	iowrite8(0xff, ioaddr + 0x7f8);

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	wait_until_busy_reset(ioaddr);

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}

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/**

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 * ccat_update_cmd_addr() - Helper to issue a FPGA flash command with address parameter

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 * @ioaddr: address of the CCAT Update function in PCI config space

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 * @cmd: the command identifier

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 * @clocks: the number of clocks associated with the specified command

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 * @addr: 24 bit address associated with the specified command

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 *

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 * Triggers a full flash command cycle with write memory barrier and

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 * command activate. This call blocks until the busy flag is reset.

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 */

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static inline void ccat_update_cmd_addr(void __iomem * const ioaddr,

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					u8 cmd, u16 clocks, u32 addr)

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{

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	const u8 addr_0 = SWAP_BITS(addr & 0xff);

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	const u8 addr_1 = SWAP_BITS((addr & 0xff00) >> 8);

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	const u8 addr_2 = SWAP_BITS((addr & 0xff0000) >> 16);

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	__ccat_update_cmd(ioaddr, cmd, clocks);

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	iowrite8(addr_2, ioaddr + 0x18);

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	iowrite8(addr_1, ioaddr + 0x20);

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	iowrite8(addr_0, ioaddr + 0x28);

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	wmb();

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	iowrite8(0xff, ioaddr + 0x7f8);

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	wait_until_busy_reset(ioaddr);

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}

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/**

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 * ccat_get_status() - Read CCAT Update status

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 * @ioaddr: address of the CCAT Update function in PCI config space

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 *

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 * Return: the current status of the CCAT Update function

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 */

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static u8 ccat_get_status(void __iomem * const ioaddr)

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{

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	ccat_update_cmd(ioaddr, CCAT_READ_STATUS);

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	return ioread8(ioaddr + 0x20);

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}

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/**

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 * ccat_read_flash_block() - Read a block of CCAT configuration data from flash

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 * @ioaddr: address of the CCAT Update function in PCI config space

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 * @addr: 24 bit address of the block to read

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 * @len: number of bytes to read from this block, len <= CCAT_DATA_BLOCK_SIZE

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 * @buf: output buffer in user space

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 *

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 * Copies one block of configuration data from the CCAT FPGA's flash to

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 * the user space buffer.

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 * Note that the size of the FPGA's firmware is not known exactly so it

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 * is very possible that the overall buffer ends with a lot of 0xff.

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 *

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 * Return: the number of bytes copied

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 */

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static int ccat_read_flash_block(void __iomem * const ioaddr,

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				 const u32 addr, const u16 len,

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				 char __user * const buf)

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{

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	u16 i;

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	const u16 clocks = 8 * len;

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	ccat_update_cmd_addr(ioaddr, CCAT_READ_FLASH + clocks, addr);

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	for (i = 0; i < len; i++) {

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		put_user(ioread8(ioaddr + CCAT_DATA_IN_4 + 8 * i), buf + i);

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	}

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	return len;

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}

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/**

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 * ccat_read_flash() - Read a chunk of CCAT configuration data from flash

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 * @ioaddr: address of the CCAT Update function in PCI config space

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 * @buf: output buffer in user space

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 * @len: number of bytes to read

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 * @off: offset in the configuration data

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 *

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 * Copies multiple blocks of configuration data from the CCAT FPGA's

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 * flash to the user space buffer.

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 *

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 * Return: the number of bytes copied

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 */

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static int ccat_read_flash(void __iomem * const ioaddr, char __user * buf,

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			   u32 len, loff_t * off)

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{

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	const loff_t start = *off;

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	while (len > CCAT_DATA_BLOCK_SIZE) {

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		*off +=

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		    ccat_read_flash_block(ioaddr, *off, CCAT_DATA_BLOCK_SIZE,

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					  buf);

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		buf += CCAT_DATA_BLOCK_SIZE;

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		len -= CCAT_DATA_BLOCK_SIZE;

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	}

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	*off += ccat_read_flash_block(ioaddr, *off, len, buf);

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	return *off - start;

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}

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/**

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 * ccat_wait_status_cleared() - wait until CCAT status is cleared

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 * @ioaddr: address of the CCAT Update function in PCI config space

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 *

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 * Blocks until bit 7 of the CCAT Update status is reset

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 */

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static void ccat_wait_status_cleared(void __iomem * const ioaddr)

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{

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	u8 status;

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	do {

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		status = ccat_get_status(ioaddr);

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	} while (status & (1 << 7));

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}

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/**

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 * ccat_write_flash_block() - Write a block of CCAT configuration data to flash

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 * @ioaddr: address of the CCAT Update function in PCI config space

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 * @addr: 24 bit start address in the CCAT FPGA's flash

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 * @len: number of bytes to write in this block, len <= CCAT_WRITE_BLOCK_SIZE

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 * @buf: input buffer

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 *

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 * Copies one block of configuration data to the CCAT FPGA's flash

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 *

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 * Return: the number of bytes copied

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 */

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static int ccat_write_flash_block(void __iomem * const ioaddr,

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				  const u32 addr, const u16 len,

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				  const char *const buf)

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{

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	const u16 clocks = 8 * len;

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	u16 i;

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	ccat_update_cmd(ioaddr, CCAT_WRITE_ENABLE);

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	for (i = 0; i < len; i++) {

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		iowrite8(buf[i], ioaddr + CCAT_DATA_OUT_4 + 8 * i);

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	}

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	ccat_update_cmd_addr(ioaddr, CCAT_WRITE_FLASH + clocks, addr);

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	ccat_wait_status_cleared(ioaddr);

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	return len;

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}

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/**

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 * ccat_write_flash() - Write a new CCAT configuration to FPGA's flash

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 * @update: a CCAT Update buffer containing the new FPGA configuration

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 */

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static void ccat_write_flash(const struct cdev_buffer *const buffer)

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{

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	const char *buf = buffer->data;

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	u32 off = 0;

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	size_t len = buffer->size;

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	while (len > CCAT_WRITE_BLOCK_SIZE) {

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		ccat_write_flash_block(buffer->ccdev->ioaddr, off,

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				       (u16) CCAT_WRITE_BLOCK_SIZE, buf);

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		off += CCAT_WRITE_BLOCK_SIZE;

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		buf += CCAT_WRITE_BLOCK_SIZE;

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		len -= CCAT_WRITE_BLOCK_SIZE;

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	}

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	ccat_write_flash_block(buffer->ccdev->ioaddr, off, (u16) len, buf);

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}

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static int ccat_update_release(struct inode *const i, struct file *const f)

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{

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	const struct cdev_buffer *const buf = f->private_data;

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	void __iomem *ioaddr = buf->ccdev->ioaddr;

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	if (buf->size > 0) {

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		ccat_update_cmd(ioaddr, CCAT_WRITE_ENABLE);

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		ccat_update_cmd(ioaddr, CCAT_BULK_ERASE);

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		ccat_wait_status_cleared(ioaddr);

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		ccat_write_flash(buf);

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	}

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	return ccat_cdev_release(i, f);

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}

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/**

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 * ccat_update_read() - Read CCAT configuration data from flash

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 * @f: file handle previously initialized with ccat_update_open()

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 * @buf: buffer in user space provided for our data

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 * @len: length of the user space buffer

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 * @off: current offset of our file operation

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 *

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 * Copies data from the CCAT FPGA's configuration flash to user space.

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 * Note that the size of the FPGA's firmware is not known exactly so it

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 * is very possible that the overall buffer ends with a lot of 0xff.

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 *

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 * Return: the number of bytes written, or 0 if EOF reached

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 */

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static ssize_t ccat_update_read(struct file *const f, char __user * buf,

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				size_t len, loff_t * off)

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{

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	struct cdev_buffer *buffer = f->private_data;

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	const size_t iosize = buffer->ccdev->iosize;

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	if (*off >= iosize) {

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		return 0;

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	}

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	len = min(len, (size_t) (iosize - *off));

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	return ccat_read_flash(buffer->ccdev->ioaddr, buf, len, off);

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}

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/**

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 * ccat_update_write() - Write data to the CCAT FPGA's configuration flash

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 * @f: file handle previously initialized with ccat_update_open()

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 * @buf: buffer in user space providing the new configuration data (from *.rbf)

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 * @len: length of the user space buffer

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 * @off: current offset in the configuration data

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 *

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 * Copies data from user space (possibly a *.rbf) to the CCAT FPGA's

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 * configuration flash.

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 *

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 * Return: the number of bytes written, or 0 if flash end is reached

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 */

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static ssize_t ccat_update_write(struct file *const f, const char __user * buf,

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				 size_t len, loff_t * off)

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{

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	struct cdev_buffer *const buffer = f->private_data;

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	if (*off + len > buffer->ccdev->iosize) {

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		return 0;

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	}

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	if (copy_from_user(buffer->data + *off, buf, len)) {

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		return -EFAULT;

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	}

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	*off += len;

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	buffer->size = *off;

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	return len;

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}

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static struct ccat_cdev dev_table[CCAT_DEVICES_MAX];

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static struct ccat_class cdev_class = {

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	.count = CCAT_DEVICES_MAX,

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	.devices = dev_table,

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	.name = "ccat_update",

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	.fops = {

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		 .owner = THIS_MODULE,

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		 .open = ccat_cdev_open,

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		 .release = ccat_update_release,

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		 .read = ccat_update_read,

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		 .write = ccat_update_write,

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		 },

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};

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static int ccat_update_probe(struct ccat_function *func)

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{

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	static const u16 SUPPORTED_REVISION = 0x00;

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	if (SUPPORTED_REVISION != func->info.rev) {

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		pr_warn("CCAT Update rev. %d not supported\n", func->info.rev);

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		return -ENODEV;

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	}

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	return ccat_cdev_probe(func, &cdev_class, CCAT_FLASH_SIZE);

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}

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const struct ccat_driver update_driver = {

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	.type = CCATINFO_EPCS_PROM,

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	.probe = ccat_update_probe,

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	.remove = ccat_cdev_remove,

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	.cdev_class = &cdev_class,

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};