master/master.c
changeset 1426 af45bba80d85
parent 1425 c1322a8793c0
child 1434 4c6fe0ae37f1
--- a/master/master.c	Thu Apr 30 14:12:47 2009 +0000
+++ b/master/master.c	Thu Apr 30 14:37:02 2009 +0000
@@ -1431,9 +1431,9 @@
 
 /*****************************************************************************/
 
-/** Calculates the bus transition delays.
- */
-void ec_master_calc_transition_delays(
+/** Calculates the bus transmission delays.
+ */
+void ec_master_calc_transmission_delays(
         ec_master_t *master /**< EtherCAT master. */
 		)
 {
@@ -1447,7 +1447,7 @@
 
     if (master->dc_ref_clock) {
         uint32_t delay = 0;
-        ec_slave_calc_transition_delays_rec(master->dc_ref_clock, &delay);
+        ec_slave_calc_transmission_delays_rec(master->dc_ref_clock, &delay);
     }
 }
 
@@ -1465,7 +1465,7 @@
     // calculate bus topology
     ec_master_calc_topology(master);
 
-    ec_master_calc_transition_delays(master);
+    ec_master_calc_transmission_delays(master);
 }
 
 /******************************************************************************