1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2009 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /*

    30  * 82571EB Gigabit Ethernet Controller

    31  * 82571EB Gigabit Ethernet Controller (Copper)

    32  * 82571EB Gigabit Ethernet Controller (Fiber)

    33  * 82571EB Dual Port Gigabit Mezzanine Adapter

    34  * 82571EB Quad Port Gigabit Mezzanine Adapter

    35  * 82571PT Gigabit PT Quad Port Server ExpressModule

    36  * 82572EI Gigabit Ethernet Controller (Copper)

    37  * 82572EI Gigabit Ethernet Controller (Fiber)

    38  * 82572EI Gigabit Ethernet Controller

    39  * 82573V Gigabit Ethernet Controller (Copper)

    40  * 82573E Gigabit Ethernet Controller (Copper)

    41  * 82573L Gigabit Ethernet Controller

    42  * 82574L Gigabit Network Connection

    43  * 82583V Gigabit Network Connection

    44  */

    45 

    46 #include "e1000.h"

    47 

    48 #define ID_LED_RESERVED_F746 0xF746

    49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \

    50 			      (ID_LED_OFF1_ON2  <<  8) | \

    51 			      (ID_LED_DEF1_DEF2 <<  4) | \

    52 			      (ID_LED_DEF1_DEF2))

    53 

    54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000

    55 

    56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */

    57 

    58 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);

    59 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);

    60 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);

    61 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);

    62 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,

    63 				      u16 words, u16 *data);

    64 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);

    65 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);

    66 static s32 e1000_setup_link_82571(struct e1000_hw *hw);

    67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);

    68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);

    69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);

    70 static s32 e1000_led_on_82574(struct e1000_hw *hw);

    71 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);

    72 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);

    73 

    74 /**

    75  *  e1000_init_phy_params_82571 - Init PHY func ptrs.

    76  *  @hw: pointer to the HW structure

    77  **/

    78 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)

    79 {

    80 	struct e1000_phy_info *phy = &hw->phy;

    81 	s32 ret_val;

    82 

    83 	if (hw->phy.media_type != e1000_media_type_copper) {

    84 		phy->type = e1000_phy_none;

    85 		return 0;

    86 	}

    87 

    88 	phy->addr			 = 1;

    89 	phy->autoneg_mask		 = AUTONEG_ADVERTISE_SPEED_DEFAULT;

    90 	phy->reset_delay_us		 = 100;

    91 

    92 	phy->ops.power_up		 = e1000_power_up_phy_copper;

    93 	phy->ops.power_down		 = e1000_power_down_phy_copper_82571;

    94 

    95 	switch (hw->mac.type) {

    96 	case e1000_82571:

    97 	case e1000_82572:

    98 		phy->type		 = e1000_phy_igp_2;

    99 		break;

   100 	case e1000_82573:

   101 		phy->type		 = e1000_phy_m88;

   102 		break;

   103 	case e1000_82574:

   104 	case e1000_82583:

   105 		phy->type		 = e1000_phy_bm;

   106 		break;

   107 	default:

   108 		return -E1000_ERR_PHY;

   109 		break;

   110 	}

   111 

   112 	/* This can only be done after all function pointers are setup. */

   113 	ret_val = e1000_get_phy_id_82571(hw);

   114 

   115 	/* Verify phy id */

   116 	switch (hw->mac.type) {

   117 	case e1000_82571:

   118 	case e1000_82572:

   119 		if (phy->id != IGP01E1000_I_PHY_ID)

   120 			return -E1000_ERR_PHY;

   121 		break;

   122 	case e1000_82573:

   123 		if (phy->id != M88E1111_I_PHY_ID)

   124 			return -E1000_ERR_PHY;

   125 		break;

   126 	case e1000_82574:

   127 	case e1000_82583:

   128 		if (phy->id != BME1000_E_PHY_ID_R2)

   129 			return -E1000_ERR_PHY;

   130 		break;

   131 	default:

   132 		return -E1000_ERR_PHY;

   133 		break;

   134 	}

   135 

   136 	return 0;

   137 }

   138 

   139 /**

   140  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.

   141  *  @hw: pointer to the HW structure

   142  **/

   143 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)

   144 {

   145 	struct e1000_nvm_info *nvm = &hw->nvm;

   146 	u32 eecd = er32(EECD);

   147 	u16 size;

   148 

   149 	nvm->opcode_bits = 8;

   150 	nvm->delay_usec = 1;

   151 	switch (nvm->override) {

   152 	case e1000_nvm_override_spi_large:

   153 		nvm->page_size = 32;

   154 		nvm->address_bits = 16;

   155 		break;

   156 	case e1000_nvm_override_spi_small:

   157 		nvm->page_size = 8;

   158 		nvm->address_bits = 8;

   159 		break;

   160 	default:

   161 		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   162 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   163 		break;

   164 	}

   165 

   166 	switch (hw->mac.type) {

   167 	case e1000_82573:

   168 	case e1000_82574:

   169 	case e1000_82583:

   170 		if (((eecd >> 15) & 0x3) == 0x3) {

   171 			nvm->type = e1000_nvm_flash_hw;

   172 			nvm->word_size = 2048;

   173 			/*

   174 			 * Autonomous Flash update bit must be cleared due

   175 			 * to Flash update issue.

   176 			 */

   177 			eecd &= ~E1000_EECD_AUPDEN;

   178 			ew32(EECD, eecd);

   179 			break;

   180 		}

   181 		/* Fall Through */

   182 	default:

   183 		nvm->type = e1000_nvm_eeprom_spi;

   184 		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   185 				  E1000_EECD_SIZE_EX_SHIFT);

   186 		/*

   187 		 * Added to a constant, "size" becomes the left-shift value

   188 		 * for setting word_size.

   189 		 */

   190 		size += NVM_WORD_SIZE_BASE_SHIFT;

   191 

   192 		/* EEPROM access above 16k is unsupported */

   193 		if (size > 14)

   194 			size = 14;

   195 		nvm->word_size	= 1 << size;

   196 		break;

   197 	}

   198 

   199 	return 0;

   200 }

   201 

   202 /**

   203  *  e1000_init_mac_params_82571 - Init MAC func ptrs.

   204  *  @hw: pointer to the HW structure

   205  **/

   206 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)

   207 {

   208 	struct e1000_hw *hw = &adapter->hw;

   209 	struct e1000_mac_info *mac = &hw->mac;

   210 	struct e1000_mac_operations *func = &mac->ops;

   211 	u32 swsm = 0;

   212 	u32 swsm2 = 0;

   213 	bool force_clear_smbi = false;

   214 

   215 	/* Set media type */

   216 	switch (adapter->pdev->device) {

   217 	case E1000_DEV_ID_82571EB_FIBER:

   218 	case E1000_DEV_ID_82572EI_FIBER:

   219 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   220 		hw->phy.media_type = e1000_media_type_fiber;

   221 		break;

   222 	case E1000_DEV_ID_82571EB_SERDES:

   223 	case E1000_DEV_ID_82572EI_SERDES:

   224 	case E1000_DEV_ID_82571EB_SERDES_DUAL:

   225 	case E1000_DEV_ID_82571EB_SERDES_QUAD:

   226 		hw->phy.media_type = e1000_media_type_internal_serdes;

   227 		break;

   228 	default:

   229 		hw->phy.media_type = e1000_media_type_copper;

   230 		break;

   231 	}

   232 

   233 	/* Set mta register count */

   234 	mac->mta_reg_count = 128;

   235 	/* Set rar entry count */

   236 	mac->rar_entry_count = E1000_RAR_ENTRIES;

   237 	/* Adaptive IFS supported */

   238 	mac->adaptive_ifs = true;

   239 

   240 	/* check for link */

   241 	switch (hw->phy.media_type) {

   242 	case e1000_media_type_copper:

   243 		func->setup_physical_interface = e1000_setup_copper_link_82571;

   244 		func->check_for_link = e1000e_check_for_copper_link;

   245 		func->get_link_up_info = e1000e_get_speed_and_duplex_copper;

   246 		break;

   247 	case e1000_media_type_fiber:

   248 		func->setup_physical_interface =

   249 			e1000_setup_fiber_serdes_link_82571;

   250 		func->check_for_link = e1000e_check_for_fiber_link;

   251 		func->get_link_up_info =

   252 			e1000e_get_speed_and_duplex_fiber_serdes;

   253 		break;

   254 	case e1000_media_type_internal_serdes:

   255 		func->setup_physical_interface =

   256 			e1000_setup_fiber_serdes_link_82571;

   257 		func->check_for_link = e1000_check_for_serdes_link_82571;

   258 		func->get_link_up_info =

   259 			e1000e_get_speed_and_duplex_fiber_serdes;

   260 		break;

   261 	default:

   262 		return -E1000_ERR_CONFIG;

   263 		break;

   264 	}

   265 

   266 	switch (hw->mac.type) {

   267 	case e1000_82573:

   268 		func->set_lan_id = e1000_set_lan_id_single_port;

   269 		func->check_mng_mode = e1000e_check_mng_mode_generic;

   270 		func->led_on = e1000e_led_on_generic;

   271 

   272 		/* FWSM register */

   273 		mac->has_fwsm = true;

   274 		/*

   275 		 * ARC supported; valid only if manageability features are

   276 		 * enabled.

   277 		 */

   278 		mac->arc_subsystem_valid =

   279 			(er32(FWSM) & E1000_FWSM_MODE_MASK)

   280 			? true : false;

   281 		break;

   282 	case e1000_82574:

   283 	case e1000_82583:

   284 		func->set_lan_id = e1000_set_lan_id_single_port;

   285 		func->check_mng_mode = e1000_check_mng_mode_82574;

   286 		func->led_on = e1000_led_on_82574;

   287 		break;

   288 	default:

   289 		func->check_mng_mode = e1000e_check_mng_mode_generic;

   290 		func->led_on = e1000e_led_on_generic;

   291 

   292 		/* FWSM register */

   293 		mac->has_fwsm = true;

   294 		break;

   295 	}

   296 

   297 	/*

   298 	 * Ensure that the inter-port SWSM.SMBI lock bit is clear before

   299 	 * first NVM or PHY acess. This should be done for single-port

   300 	 * devices, and for one port only on dual-port devices so that

   301 	 * for those devices we can still use the SMBI lock to synchronize

   302 	 * inter-port accesses to the PHY & NVM.

   303 	 */

   304 	switch (hw->mac.type) {

   305 	case e1000_82571:

   306 	case e1000_82572:

   307 		swsm2 = er32(SWSM2);

   308 

   309 		if (!(swsm2 & E1000_SWSM2_LOCK)) {

   310 			/* Only do this for the first interface on this card */

   311 			ew32(SWSM2,

   312 			    swsm2 | E1000_SWSM2_LOCK);

   313 			force_clear_smbi = true;

   314 		} else

   315 			force_clear_smbi = false;

   316 		break;

   317 	default:

   318 		force_clear_smbi = true;

   319 		break;

   320 	}

   321 

   322 	if (force_clear_smbi) {

   323 		/* Make sure SWSM.SMBI is clear */

   324 		swsm = er32(SWSM);

   325 		if (swsm & E1000_SWSM_SMBI) {

   326 			/* This bit should not be set on a first interface, and

   327 			 * indicates that the bootagent or EFI code has

   328 			 * improperly left this bit enabled

   329 			 */

   330 			e_dbg("Please update your 82571 Bootagent\n");

   331 		}

   332 		ew32(SWSM, swsm & ~E1000_SWSM_SMBI);

   333 	}

   334 

   335 	/*

   336 	 * Initialize device specific counter of SMBI acquisition

   337 	 * timeouts.

   338 	 */

   339 	 hw->dev_spec.e82571.smb_counter = 0;

   340 

   341 	return 0;

   342 }

   343 

   344 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)

   345 {

   346 	struct e1000_hw *hw = &adapter->hw;

   347 	static int global_quad_port_a; /* global port a indication */

   348 	struct pci_dev *pdev = adapter->pdev;

   349 	int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;

   350 	s32 rc;

   351 

   352 	rc = e1000_init_mac_params_82571(adapter);

   353 	if (rc)

   354 		return rc;

   355 

   356 	rc = e1000_init_nvm_params_82571(hw);

   357 	if (rc)

   358 		return rc;

   359 

   360 	rc = e1000_init_phy_params_82571(hw);

   361 	if (rc)

   362 		return rc;

   363 

   364 	/* tag quad port adapters first, it's used below */

   365 	switch (pdev->device) {

   366 	case E1000_DEV_ID_82571EB_QUAD_COPPER:

   367 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   368 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:

   369 	case E1000_DEV_ID_82571PT_QUAD_COPPER:

   370 		adapter->flags |= FLAG_IS_QUAD_PORT;

   371 		/* mark the first port */

   372 		if (global_quad_port_a == 0)

   373 			adapter->flags |= FLAG_IS_QUAD_PORT_A;

   374 		/* Reset for multiple quad port adapters */

   375 		global_quad_port_a++;

   376 		if (global_quad_port_a == 4)

   377 			global_quad_port_a = 0;

   378 		break;

   379 	default:

   380 		break;

   381 	}

   382 

   383 	switch (adapter->hw.mac.type) {

   384 	case e1000_82571:

   385 		/* these dual ports don't have WoL on port B at all */

   386 		if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||

   387 		     (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||

   388 		     (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&

   389 		    (is_port_b))

   390 			adapter->flags &= ~FLAG_HAS_WOL;

   391 		/* quad ports only support WoL on port A */

   392 		if (adapter->flags & FLAG_IS_QUAD_PORT &&

   393 		    (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))

   394 			adapter->flags &= ~FLAG_HAS_WOL;

   395 		/* Does not support WoL on any port */

   396 		if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)

   397 			adapter->flags &= ~FLAG_HAS_WOL;

   398 		break;

   399 	case e1000_82573:

   400 	case e1000_82574:

   401 	case e1000_82583:

   402 		/* Disable ASPM L0s due to hardware errata */

   403 		e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S);

   404 

   405 		if (pdev->device == E1000_DEV_ID_82573L) {

   406 			adapter->flags |= FLAG_HAS_JUMBO_FRAMES;

   407 			adapter->max_hw_frame_size = DEFAULT_JUMBO;

   408 		}

   409 		break;

   410 	default:

   411 		break;

   412 	}

   413 

   414 	return 0;

   415 }

   416 

   417 /**

   418  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision

   419  *  @hw: pointer to the HW structure

   420  *

   421  *  Reads the PHY registers and stores the PHY ID and possibly the PHY

   422  *  revision in the hardware structure.

   423  **/

   424 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)

   425 {

   426 	struct e1000_phy_info *phy = &hw->phy;

   427 	s32 ret_val;

   428 	u16 phy_id = 0;

   429 

   430 	switch (hw->mac.type) {

   431 	case e1000_82571:

   432 	case e1000_82572:

   433 		/*

   434 		 * The 82571 firmware may still be configuring the PHY.

   435 		 * In this case, we cannot access the PHY until the

   436 		 * configuration is done.  So we explicitly set the

   437 		 * PHY ID.

   438 		 */

   439 		phy->id = IGP01E1000_I_PHY_ID;

   440 		break;

   441 	case e1000_82573:

   442 		return e1000e_get_phy_id(hw);

   443 		break;

   444 	case e1000_82574:

   445 	case e1000_82583:

   446 		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);

   447 		if (ret_val)

   448 			return ret_val;

   449 

   450 		phy->id = (u32)(phy_id << 16);

   451 		udelay(20);

   452 		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);

   453 		if (ret_val)

   454 			return ret_val;

   455 

   456 		phy->id |= (u32)(phy_id);

   457 		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

   458 		break;

   459 	default:

   460 		return -E1000_ERR_PHY;

   461 		break;

   462 	}

   463 

   464 	return 0;

   465 }

   466 

   467 /**

   468  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore

   469  *  @hw: pointer to the HW structure

   470  *

   471  *  Acquire the HW semaphore to access the PHY or NVM

   472  **/

   473 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)

   474 {

   475 	u32 swsm;

   476 	s32 sw_timeout = hw->nvm.word_size + 1;

   477 	s32 fw_timeout = hw->nvm.word_size + 1;

   478 	s32 i = 0;

   479 

   480 	/*

   481 	 * If we have timedout 3 times on trying to acquire

   482 	 * the inter-port SMBI semaphore, there is old code

   483 	 * operating on the other port, and it is not

   484 	 * releasing SMBI. Modify the number of times that

   485 	 * we try for the semaphore to interwork with this

   486 	 * older code.

   487 	 */

   488 	if (hw->dev_spec.e82571.smb_counter > 2)

   489 		sw_timeout = 1;

   490 

   491 	/* Get the SW semaphore */

   492 	while (i < sw_timeout) {

   493 		swsm = er32(SWSM);

   494 		if (!(swsm & E1000_SWSM_SMBI))

   495 			break;

   496 

   497 		udelay(50);

   498 		i++;

   499 	}

   500 

   501 	if (i == sw_timeout) {

   502 		e_dbg("Driver can't access device - SMBI bit is set.\n");

   503 		hw->dev_spec.e82571.smb_counter++;

   504 	}

   505 	/* Get the FW semaphore. */

   506 	for (i = 0; i < fw_timeout; i++) {

   507 		swsm = er32(SWSM);

   508 		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);

   509 

   510 		/* Semaphore acquired if bit latched */

   511 		if (er32(SWSM) & E1000_SWSM_SWESMBI)

   512 			break;

   513 

   514 		udelay(50);

   515 	}

   516 

   517 	if (i == fw_timeout) {

   518 		/* Release semaphores */

   519 		e1000_put_hw_semaphore_82571(hw);

   520 		e_dbg("Driver can't access the NVM\n");

   521 		return -E1000_ERR_NVM;

   522 	}

   523 

   524 	return 0;

   525 }

   526 

   527 /**

   528  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore

   529  *  @hw: pointer to the HW structure

   530  *

   531  *  Release hardware semaphore used to access the PHY or NVM

   532  **/

   533 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)

   534 {

   535 	u32 swsm;

   536 

   537 	swsm = er32(SWSM);

   538 	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);

   539 	ew32(SWSM, swsm);

   540 }

   541 

   542 /**

   543  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM

   544  *  @hw: pointer to the HW structure

   545  *

   546  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.

   547  *  Then for non-82573 hardware, set the EEPROM access request bit and wait

   548  *  for EEPROM access grant bit.  If the access grant bit is not set, release

   549  *  hardware semaphore.

   550  **/

   551 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)

   552 {

   553 	s32 ret_val;

   554 

   555 	ret_val = e1000_get_hw_semaphore_82571(hw);

   556 	if (ret_val)

   557 		return ret_val;

   558 

   559 	switch (hw->mac.type) {

   560 	case e1000_82573:

   561 	case e1000_82574:

   562 	case e1000_82583:

   563 		break;

   564 	default:

   565 		ret_val = e1000e_acquire_nvm(hw);

   566 		break;

   567 	}

   568 

   569 	if (ret_val)

   570 		e1000_put_hw_semaphore_82571(hw);

   571 

   572 	return ret_val;

   573 }

   574 

   575 /**

   576  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM

   577  *  @hw: pointer to the HW structure

   578  *

   579  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.

   580  **/

   581 static void e1000_release_nvm_82571(struct e1000_hw *hw)

   582 {

   583 	e1000e_release_nvm(hw);

   584 	e1000_put_hw_semaphore_82571(hw);

   585 }

   586 

   587 /**

   588  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface

   589  *  @hw: pointer to the HW structure

   590  *  @offset: offset within the EEPROM to be written to

   591  *  @words: number of words to write

   592  *  @data: 16 bit word(s) to be written to the EEPROM

   593  *

   594  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.

   595  *

   596  *  If e1000e_update_nvm_checksum is not called after this function, the

   597  *  EEPROM will most likely contain an invalid checksum.

   598  **/

   599 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,

   600 				 u16 *data)

   601 {

   602 	s32 ret_val;

   603 

   604 	switch (hw->mac.type) {

   605 	case e1000_82573:

   606 	case e1000_82574:

   607 	case e1000_82583:

   608 		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);

   609 		break;

   610 	case e1000_82571:

   611 	case e1000_82572:

   612 		ret_val = e1000e_write_nvm_spi(hw, offset, words, data);

   613 		break;

   614 	default:

   615 		ret_val = -E1000_ERR_NVM;

   616 		break;

   617 	}

   618 

   619 	return ret_val;

   620 }

   621 

   622 /**

   623  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum

   624  *  @hw: pointer to the HW structure

   625  *

   626  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM

   627  *  up to the checksum.  Then calculates the EEPROM checksum and writes the

   628  *  value to the EEPROM.

   629  **/

   630 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)

   631 {

   632 	u32 eecd;

   633 	s32 ret_val;

   634 	u16 i;

   635 

   636 	ret_val = e1000e_update_nvm_checksum_generic(hw);

   637 	if (ret_val)

   638 		return ret_val;

   639 

   640 	/*

   641 	 * If our nvm is an EEPROM, then we're done

   642 	 * otherwise, commit the checksum to the flash NVM.

   643 	 */

   644 	if (hw->nvm.type != e1000_nvm_flash_hw)

   645 		return ret_val;

   646 

   647 	/* Check for pending operations. */

   648 	for (i = 0; i < E1000_FLASH_UPDATES; i++) {

   649 		msleep(1);

   650 		if ((er32(EECD) & E1000_EECD_FLUPD) == 0)

   651 			break;

   652 	}

   653 

   654 	if (i == E1000_FLASH_UPDATES)

   655 		return -E1000_ERR_NVM;

   656 

   657 	/* Reset the firmware if using STM opcode. */

   658 	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {

   659 		/*

   660 		 * The enabling of and the actual reset must be done

   661 		 * in two write cycles.

   662 		 */

   663 		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);

   664 		e1e_flush();

   665 		ew32(HICR, E1000_HICR_FW_RESET);

   666 	}

   667 

   668 	/* Commit the write to flash */

   669 	eecd = er32(EECD) | E1000_EECD_FLUPD;

   670 	ew32(EECD, eecd);

   671 

   672 	for (i = 0; i < E1000_FLASH_UPDATES; i++) {

   673 		msleep(1);

   674 		if ((er32(EECD) & E1000_EECD_FLUPD) == 0)

   675 			break;

   676 	}

   677 

   678 	if (i == E1000_FLASH_UPDATES)

   679 		return -E1000_ERR_NVM;

   680 

   681 	return 0;

   682 }

   683 

   684 /**

   685  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum

   686  *  @hw: pointer to the HW structure

   687  *

   688  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM

   689  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.

   690  **/

   691 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)

   692 {

   693 	if (hw->nvm.type == e1000_nvm_flash_hw)

   694 		e1000_fix_nvm_checksum_82571(hw);

   695 

   696 	return e1000e_validate_nvm_checksum_generic(hw);

   697 }

   698 

   699 /**

   700  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon

   701  *  @hw: pointer to the HW structure

   702  *  @offset: offset within the EEPROM to be written to

   703  *  @words: number of words to write

   704  *  @data: 16 bit word(s) to be written to the EEPROM

   705  *

   706  *  After checking for invalid values, poll the EEPROM to ensure the previous

   707  *  command has completed before trying to write the next word.  After write

   708  *  poll for completion.

   709  *

   710  *  If e1000e_update_nvm_checksum is not called after this function, the

   711  *  EEPROM will most likely contain an invalid checksum.

   712  **/

   713 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,

   714 				      u16 words, u16 *data)

   715 {

   716 	struct e1000_nvm_info *nvm = &hw->nvm;

   717 	u32 i, eewr = 0;

   718 	s32 ret_val = 0;

   719 

   720 	/*

   721 	 * A check for invalid values:  offset too large, too many words,

   722 	 * and not enough words.

   723 	 */

   724 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||

   725 	    (words == 0)) {

   726 		e_dbg("nvm parameter(s) out of bounds\n");

   727 		return -E1000_ERR_NVM;

   728 	}

   729 

   730 	for (i = 0; i < words; i++) {

   731 		eewr = (data[i] << E1000_NVM_RW_REG_DATA) |

   732 		       ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |

   733 		       E1000_NVM_RW_REG_START;

   734 

   735 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

   736 		if (ret_val)

   737 			break;

   738 

   739 		ew32(EEWR, eewr);

   740 

   741 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

   742 		if (ret_val)

   743 			break;

   744 	}

   745 

   746 	return ret_val;

   747 }

   748 

   749 /**

   750  *  e1000_get_cfg_done_82571 - Poll for configuration done

   751  *  @hw: pointer to the HW structure

   752  *

   753  *  Reads the management control register for the config done bit to be set.

   754  **/

   755 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)

   756 {

   757 	s32 timeout = PHY_CFG_TIMEOUT;

   758 

   759 	while (timeout) {

   760 		if (er32(EEMNGCTL) &

   761 		    E1000_NVM_CFG_DONE_PORT_0)

   762 			break;

   763 		msleep(1);

   764 		timeout--;

   765 	}

   766 	if (!timeout) {

   767 		e_dbg("MNG configuration cycle has not completed.\n");

   768 		return -E1000_ERR_RESET;

   769 	}

   770 

   771 	return 0;

   772 }

   773 

   774 /**

   775  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state

   776  *  @hw: pointer to the HW structure

   777  *  @active: true to enable LPLU, false to disable

   778  *

   779  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU

   780  *  this function also disables smart speed and vice versa.  LPLU will not be

   781  *  activated unless the device autonegotiation advertisement meets standards

   782  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function

   783  *  pointer entry point only called by PHY setup routines.

   784  **/

   785 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)

   786 {

   787 	struct e1000_phy_info *phy = &hw->phy;

   788 	s32 ret_val;

   789 	u16 data;

   790 

   791 	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);

   792 	if (ret_val)

   793 		return ret_val;

   794 

   795 	if (active) {

   796 		data |= IGP02E1000_PM_D0_LPLU;

   797 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

   798 		if (ret_val)

   799 			return ret_val;

   800 

   801 		/* When LPLU is enabled, we should disable SmartSpeed */

   802 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);

   803 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;

   804 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);

   805 		if (ret_val)

   806 			return ret_val;

   807 	} else {

   808 		data &= ~IGP02E1000_PM_D0_LPLU;

   809 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

   810 		/*

   811 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used

   812 		 * during Dx states where the power conservation is most

   813 		 * important.  During driver activity we should enable

   814 		 * SmartSpeed, so performance is maintained.

   815 		 */

   816 		if (phy->smart_speed == e1000_smart_speed_on) {

   817 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   818 					   &data);

   819 			if (ret_val)

   820 				return ret_val;

   821 

   822 			data |= IGP01E1000_PSCFR_SMART_SPEED;

   823 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   824 					   data);

   825 			if (ret_val)

   826 				return ret_val;

   827 		} else if (phy->smart_speed == e1000_smart_speed_off) {

   828 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   829 					   &data);

   830 			if (ret_val)

   831 				return ret_val;

   832 

   833 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;

   834 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   835 					   data);

   836 			if (ret_val)

   837 				return ret_val;

   838 		}

   839 	}

   840 

   841 	return 0;

   842 }

   843 

   844 /**

   845  *  e1000_reset_hw_82571 - Reset hardware

   846  *  @hw: pointer to the HW structure

   847  *

   848  *  This resets the hardware into a known state.

   849  **/

   850 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)

   851 {

   852 	u32 ctrl, extcnf_ctrl, ctrl_ext, icr;

   853 	s32 ret_val;

   854 	u16 i = 0;

   855 

   856 	/*

   857 	 * Prevent the PCI-E bus from sticking if there is no TLP connection

   858 	 * on the last TLP read/write transaction when MAC is reset.

   859 	 */

   860 	ret_val = e1000e_disable_pcie_master(hw);

   861 	if (ret_val)

   862 		e_dbg("PCI-E Master disable polling has failed.\n");

   863 

   864 	e_dbg("Masking off all interrupts\n");

   865 	ew32(IMC, 0xffffffff);

   866 

   867 	ew32(RCTL, 0);

   868 	ew32(TCTL, E1000_TCTL_PSP);

   869 	e1e_flush();

   870 

   871 	msleep(10);

   872 

   873 	/*

   874 	 * Must acquire the MDIO ownership before MAC reset.

   875 	 * Ownership defaults to firmware after a reset.

   876 	 */

   877 	switch (hw->mac.type) {

   878 	case e1000_82573:

   879 	case e1000_82574:

   880 	case e1000_82583:

   881 		extcnf_ctrl = er32(EXTCNF_CTRL);

   882 		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   883 

   884 		do {

   885 			ew32(EXTCNF_CTRL, extcnf_ctrl);

   886 			extcnf_ctrl = er32(EXTCNF_CTRL);

   887 

   888 			if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

   889 				break;

   890 

   891 			extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   892 

   893 			msleep(2);

   894 			i++;

   895 		} while (i < MDIO_OWNERSHIP_TIMEOUT);

   896 		break;

   897 	default:

   898 		break;

   899 	}

   900 

   901 	ctrl = er32(CTRL);

   902 

   903 	e_dbg("Issuing a global reset to MAC\n");

   904 	ew32(CTRL, ctrl | E1000_CTRL_RST);

   905 

   906 	if (hw->nvm.type == e1000_nvm_flash_hw) {

   907 		udelay(10);

   908 		ctrl_ext = er32(CTRL_EXT);

   909 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   910 		ew32(CTRL_EXT, ctrl_ext);

   911 		e1e_flush();

   912 	}

   913 

   914 	ret_val = e1000e_get_auto_rd_done(hw);

   915 	if (ret_val)

   916 		/* We don't want to continue accessing MAC registers. */

   917 		return ret_val;

   918 

   919 	/*

   920 	 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.

   921 	 * Need to wait for Phy configuration completion before accessing

   922 	 * NVM and Phy.

   923 	 */

   924 

   925 	switch (hw->mac.type) {

   926 	case e1000_82573:

   927 	case e1000_82574:

   928 	case e1000_82583:

   929 		msleep(25);

   930 		break;

   931 	default:

   932 		break;

   933 	}

   934 

   935 	/* Clear any pending interrupt events. */

   936 	ew32(IMC, 0xffffffff);

   937 	icr = er32(ICR);

   938 

   939 	if (hw->mac.type == e1000_82571) {

   940 		/* Install any alternate MAC address into RAR0 */

   941 		ret_val = e1000_check_alt_mac_addr_generic(hw);

   942 		if (ret_val)

   943 			return ret_val;

   944 

   945 		e1000e_set_laa_state_82571(hw, true);

   946 	}

   947 

   948 	/* Reinitialize the 82571 serdes link state machine */

   949 	if (hw->phy.media_type == e1000_media_type_internal_serdes)

   950 		hw->mac.serdes_link_state = e1000_serdes_link_down;

   951 

   952 	return 0;

   953 }

   954 

   955 /**

   956  *  e1000_init_hw_82571 - Initialize hardware

   957  *  @hw: pointer to the HW structure

   958  *

   959  *  This inits the hardware readying it for operation.

   960  **/

   961 static s32 e1000_init_hw_82571(struct e1000_hw *hw)

   962 {

   963 	struct e1000_mac_info *mac = &hw->mac;

   964 	u32 reg_data;

   965 	s32 ret_val;

   966 	u16 i, rar_count = mac->rar_entry_count;

   967 

   968 	e1000_initialize_hw_bits_82571(hw);

   969 

   970 	/* Initialize identification LED */

   971 	ret_val = e1000e_id_led_init(hw);

   972 	if (ret_val)

   973 		e_dbg("Error initializing identification LED\n");

   974 		/* This is not fatal and we should not stop init due to this */

   975 

   976 	/* Disabling VLAN filtering */

   977 	e_dbg("Initializing the IEEE VLAN\n");

   978 	mac->ops.clear_vfta(hw);

   979 

   980 	/* Setup the receive address. */

   981 	/*

   982 	 * If, however, a locally administered address was assigned to the

   983 	 * 82571, we must reserve a RAR for it to work around an issue where

   984 	 * resetting one port will reload the MAC on the other port.

   985 	 */

   986 	if (e1000e_get_laa_state_82571(hw))

   987 		rar_count--;

   988 	e1000e_init_rx_addrs(hw, rar_count);

   989 

   990 	/* Zero out the Multicast HASH table */

   991 	e_dbg("Zeroing the MTA\n");

   992 	for (i = 0; i < mac->mta_reg_count; i++)

   993 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);

   994 

   995 	/* Setup link and flow control */

   996 	ret_val = e1000_setup_link_82571(hw);

   997 

   998 	/* Set the transmit descriptor write-back policy */

   999 	reg_data = er32(TXDCTL(0));

  1000 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

  1001 		   E1000_TXDCTL_FULL_TX_DESC_WB |

  1002 		   E1000_TXDCTL_COUNT_DESC;

  1003 	ew32(TXDCTL(0), reg_data);

  1004 

  1005 	/* ...for both queues. */

  1006 	switch (mac->type) {

  1007 	case e1000_82573:

  1008 		e1000e_enable_tx_pkt_filtering(hw);

  1009 		/* fall through */

  1010 	case e1000_82574:

  1011 	case e1000_82583:

  1012 		reg_data = er32(GCR);

  1013 		reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;

  1014 		ew32(GCR, reg_data);

  1015 		break;

  1016 	default:

  1017 		reg_data = er32(TXDCTL(1));

  1018 		reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

  1019 			   E1000_TXDCTL_FULL_TX_DESC_WB |

  1020 			   E1000_TXDCTL_COUNT_DESC;

  1021 		ew32(TXDCTL(1), reg_data);

  1022 		break;

  1023 	}

  1024 

  1025 	/*

  1026 	 * Clear all of the statistics registers (clear on read).  It is

  1027 	 * important that we do this after we have tried to establish link

  1028 	 * because the symbol error count will increment wildly if there

  1029 	 * is no link.

  1030 	 */

  1031 	e1000_clear_hw_cntrs_82571(hw);

  1032 

  1033 	return ret_val;

  1034 }

  1035 

  1036 /**

  1037  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits

  1038  *  @hw: pointer to the HW structure

  1039  *

  1040  *  Initializes required hardware-dependent bits needed for normal operation.

  1041  **/

  1042 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)

  1043 {

  1044 	u32 reg;

  1045 

  1046 	/* Transmit Descriptor Control 0 */

  1047 	reg = er32(TXDCTL(0));

  1048 	reg |= (1 << 22);

  1049 	ew32(TXDCTL(0), reg);

  1050 

  1051 	/* Transmit Descriptor Control 1 */

  1052 	reg = er32(TXDCTL(1));

  1053 	reg |= (1 << 22);

  1054 	ew32(TXDCTL(1), reg);

  1055 

  1056 	/* Transmit Arbitration Control 0 */

  1057 	reg = er32(TARC(0));

  1058 	reg &= ~(0xF << 27); /* 30:27 */

  1059 	switch (hw->mac.type) {

  1060 	case e1000_82571:

  1061 	case e1000_82572:

  1062 		reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);

  1063 		break;

  1064 	default:

  1065 		break;

  1066 	}

  1067 	ew32(TARC(0), reg);

  1068 

  1069 	/* Transmit Arbitration Control 1 */

  1070 	reg = er32(TARC(1));

  1071 	switch (hw->mac.type) {

  1072 	case e1000_82571:

  1073 	case e1000_82572:

  1074 		reg &= ~((1 << 29) | (1 << 30));

  1075 		reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);

  1076 		if (er32(TCTL) & E1000_TCTL_MULR)

  1077 			reg &= ~(1 << 28);

  1078 		else

  1079 			reg |= (1 << 28);

  1080 		ew32(TARC(1), reg);

  1081 		break;

  1082 	default:

  1083 		break;

  1084 	}

  1085 

  1086 	/* Device Control */

  1087 	switch (hw->mac.type) {

  1088 	case e1000_82573:

  1089 	case e1000_82574:

  1090 	case e1000_82583:

  1091 		reg = er32(CTRL);

  1092 		reg &= ~(1 << 29);

  1093 		ew32(CTRL, reg);

  1094 		break;

  1095 	default:

  1096 		break;

  1097 	}

  1098 

  1099 	/* Extended Device Control */

  1100 	switch (hw->mac.type) {

  1101 	case e1000_82573:

  1102 	case e1000_82574:

  1103 	case e1000_82583:

  1104 		reg = er32(CTRL_EXT);

  1105 		reg &= ~(1 << 23);

  1106 		reg |= (1 << 22);

  1107 		ew32(CTRL_EXT, reg);

  1108 		break;

  1109 	default:

  1110 		break;

  1111 	}

  1112 

  1113 	if (hw->mac.type == e1000_82571) {

  1114 		reg = er32(PBA_ECC);

  1115 		reg |= E1000_PBA_ECC_CORR_EN;

  1116 		ew32(PBA_ECC, reg);

  1117 	}

  1118 	/*

  1119 	 * Workaround for hardware errata.

  1120 	 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572

  1121 	 */

  1122 

  1123         if ((hw->mac.type == e1000_82571) ||

  1124            (hw->mac.type == e1000_82572)) {

  1125                 reg = er32(CTRL_EXT);

  1126                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;

  1127                 ew32(CTRL_EXT, reg);

  1128         }

  1129 

  1130 

  1131 	/* PCI-Ex Control Registers */

  1132 	switch (hw->mac.type) {

  1133 	case e1000_82574:

  1134 	case e1000_82583:

  1135 		reg = er32(GCR);