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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2006 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 */ |
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28 |
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29 /* e1000_hw.c |
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30 * Shared functions for accessing and configuring the MAC |
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31 */ |
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32 |
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33 #include "e1000.h" |
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34 |
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35 static s32 e1000_check_downshift(struct e1000_hw *hw); |
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36 static s32 e1000_check_polarity(struct e1000_hw *hw, |
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37 e1000_rev_polarity *polarity); |
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38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw); |
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39 static void e1000_clear_vfta(struct e1000_hw *hw); |
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40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
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41 bool link_up); |
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42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); |
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43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw); |
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44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); |
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45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, |
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46 u16 *max_length); |
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47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); |
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48 static s32 e1000_id_led_init(struct e1000_hw *hw); |
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49 static void e1000_init_rx_addrs(struct e1000_hw *hw); |
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50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, |
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51 struct e1000_phy_info *phy_info); |
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52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, |
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53 struct e1000_phy_info *phy_info); |
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54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); |
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55 static s32 e1000_wait_autoneg(struct e1000_hw *hw); |
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56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); |
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57 static s32 e1000_set_phy_type(struct e1000_hw *hw); |
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58 static void e1000_phy_init_script(struct e1000_hw *hw); |
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59 static s32 e1000_setup_copper_link(struct e1000_hw *hw); |
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60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); |
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61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); |
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62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); |
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63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); |
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64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); |
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65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); |
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66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count); |
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67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); |
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68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); |
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69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, |
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70 u16 words, u16 *data); |
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71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, |
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72 u16 words, u16 *data); |
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73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); |
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74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); |
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75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); |
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76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); |
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77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
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78 u16 phy_data); |
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79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
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80 u16 *phy_data); |
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81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); |
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82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw); |
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83 static void e1000_release_eeprom(struct e1000_hw *hw); |
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84 static void e1000_standby_eeprom(struct e1000_hw *hw); |
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85 static s32 e1000_set_vco_speed(struct e1000_hw *hw); |
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86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); |
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87 static s32 e1000_set_phy_mode(struct e1000_hw *hw); |
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88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
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89 u16 *data); |
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90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
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91 u16 *data); |
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92 |
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93 /* IGP cable length table */ |
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94 static const |
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95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { |
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96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, |
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97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, |
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98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, |
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99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, |
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100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, |
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101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, |
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102 100, |
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103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, |
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104 110, 110, |
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105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, |
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106 120, 120 |
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107 }; |
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108 |
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109 static DEFINE_SPINLOCK(e1000_eeprom_lock); |
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110 |
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111 /** |
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112 * e1000_set_phy_type - Set the phy type member in the hw struct. |
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113 * @hw: Struct containing variables accessed by shared code |
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114 */ |
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115 static s32 e1000_set_phy_type(struct e1000_hw *hw) |
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116 { |
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117 e_dbg("e1000_set_phy_type"); |
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118 |
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119 if (hw->mac_type == e1000_undefined) |
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120 return -E1000_ERR_PHY_TYPE; |
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121 |
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122 switch (hw->phy_id) { |
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123 case M88E1000_E_PHY_ID: |
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124 case M88E1000_I_PHY_ID: |
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125 case M88E1011_I_PHY_ID: |
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126 case M88E1111_I_PHY_ID: |
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127 hw->phy_type = e1000_phy_m88; |
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128 break; |
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129 case IGP01E1000_I_PHY_ID: |
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130 if (hw->mac_type == e1000_82541 || |
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131 hw->mac_type == e1000_82541_rev_2 || |
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132 hw->mac_type == e1000_82547 || |
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133 hw->mac_type == e1000_82547_rev_2) { |
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134 hw->phy_type = e1000_phy_igp; |
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135 break; |
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136 } |
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137 default: |
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138 /* Should never have loaded on this device */ |
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139 hw->phy_type = e1000_phy_undefined; |
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140 return -E1000_ERR_PHY_TYPE; |
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141 } |
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142 |
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143 return E1000_SUCCESS; |
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144 } |
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145 |
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146 /** |
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147 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY |
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148 * @hw: Struct containing variables accessed by shared code |
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149 */ |
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150 static void e1000_phy_init_script(struct e1000_hw *hw) |
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151 { |
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152 u32 ret_val; |
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153 u16 phy_saved_data; |
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154 |
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155 e_dbg("e1000_phy_init_script"); |
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156 |
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157 if (hw->phy_init_script) { |
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158 msleep(20); |
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159 |
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160 /* Save off the current value of register 0x2F5B to be restored at |
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161 * the end of this routine. */ |
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162 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
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163 |
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164 /* Disabled the PHY transmitter */ |
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165 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
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166 msleep(20); |
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167 |
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168 e1000_write_phy_reg(hw, 0x0000, 0x0140); |
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169 msleep(5); |
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170 |
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171 switch (hw->mac_type) { |
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172 case e1000_82541: |
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173 case e1000_82547: |
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174 e1000_write_phy_reg(hw, 0x1F95, 0x0001); |
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175 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); |
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176 e1000_write_phy_reg(hw, 0x1F79, 0x0018); |
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177 e1000_write_phy_reg(hw, 0x1F30, 0x1600); |
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178 e1000_write_phy_reg(hw, 0x1F31, 0x0014); |
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179 e1000_write_phy_reg(hw, 0x1F32, 0x161C); |
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180 e1000_write_phy_reg(hw, 0x1F94, 0x0003); |
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181 e1000_write_phy_reg(hw, 0x1F96, 0x003F); |
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182 e1000_write_phy_reg(hw, 0x2010, 0x0008); |
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183 break; |
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184 |
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185 case e1000_82541_rev_2: |
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186 case e1000_82547_rev_2: |
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187 e1000_write_phy_reg(hw, 0x1F73, 0x0099); |
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188 break; |
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189 default: |
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190 break; |
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191 } |
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192 |
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193 e1000_write_phy_reg(hw, 0x0000, 0x3300); |
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194 msleep(20); |
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195 |
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196 /* Now enable the transmitter */ |
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197 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
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198 |
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199 if (hw->mac_type == e1000_82547) { |
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200 u16 fused, fine, coarse; |
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201 |
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202 /* Move to analog registers page */ |
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203 e1000_read_phy_reg(hw, |
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204 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, |
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205 &fused); |
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206 |
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207 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { |
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208 e1000_read_phy_reg(hw, |
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209 IGP01E1000_ANALOG_FUSE_STATUS, |
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210 &fused); |
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211 |
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212 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; |
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213 coarse = |
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214 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; |
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215 |
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216 if (coarse > |
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217 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { |
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218 coarse -= |
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219 IGP01E1000_ANALOG_FUSE_COARSE_10; |
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220 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; |
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221 } else if (coarse == |
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222 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) |
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223 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; |
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224 |
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225 fused = |
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226 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | |
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227 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | |
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228 (coarse & |
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229 IGP01E1000_ANALOG_FUSE_COARSE_MASK); |
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230 |
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231 e1000_write_phy_reg(hw, |
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232 IGP01E1000_ANALOG_FUSE_CONTROL, |
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233 fused); |
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234 e1000_write_phy_reg(hw, |
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235 IGP01E1000_ANALOG_FUSE_BYPASS, |
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236 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); |
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237 } |
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238 } |
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239 } |
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240 } |
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241 |
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242 /** |
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243 * e1000_set_mac_type - Set the mac type member in the hw struct. |
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244 * @hw: Struct containing variables accessed by shared code |
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245 */ |
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246 s32 e1000_set_mac_type(struct e1000_hw *hw) |
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247 { |
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248 e_dbg("e1000_set_mac_type"); |
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249 |
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250 switch (hw->device_id) { |
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251 case E1000_DEV_ID_82542: |
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252 switch (hw->revision_id) { |
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253 case E1000_82542_2_0_REV_ID: |
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254 hw->mac_type = e1000_82542_rev2_0; |
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255 break; |
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256 case E1000_82542_2_1_REV_ID: |
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257 hw->mac_type = e1000_82542_rev2_1; |
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258 break; |
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259 default: |
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260 /* Invalid 82542 revision ID */ |
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261 return -E1000_ERR_MAC_TYPE; |
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262 } |
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263 break; |
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264 case E1000_DEV_ID_82543GC_FIBER: |
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265 case E1000_DEV_ID_82543GC_COPPER: |
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266 hw->mac_type = e1000_82543; |
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267 break; |
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268 case E1000_DEV_ID_82544EI_COPPER: |
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269 case E1000_DEV_ID_82544EI_FIBER: |
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270 case E1000_DEV_ID_82544GC_COPPER: |
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271 case E1000_DEV_ID_82544GC_LOM: |
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272 hw->mac_type = e1000_82544; |
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273 break; |
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274 case E1000_DEV_ID_82540EM: |
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275 case E1000_DEV_ID_82540EM_LOM: |
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276 case E1000_DEV_ID_82540EP: |
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277 case E1000_DEV_ID_82540EP_LOM: |
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278 case E1000_DEV_ID_82540EP_LP: |
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279 hw->mac_type = e1000_82540; |
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280 break; |
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281 case E1000_DEV_ID_82545EM_COPPER: |
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282 case E1000_DEV_ID_82545EM_FIBER: |
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283 hw->mac_type = e1000_82545; |
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284 break; |
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285 case E1000_DEV_ID_82545GM_COPPER: |
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286 case E1000_DEV_ID_82545GM_FIBER: |
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287 case E1000_DEV_ID_82545GM_SERDES: |
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288 hw->mac_type = e1000_82545_rev_3; |
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289 break; |
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290 case E1000_DEV_ID_82546EB_COPPER: |
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291 case E1000_DEV_ID_82546EB_FIBER: |
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292 case E1000_DEV_ID_82546EB_QUAD_COPPER: |
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293 hw->mac_type = e1000_82546; |
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294 break; |
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295 case E1000_DEV_ID_82546GB_COPPER: |
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296 case E1000_DEV_ID_82546GB_FIBER: |
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297 case E1000_DEV_ID_82546GB_SERDES: |
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298 case E1000_DEV_ID_82546GB_PCIE: |
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299 case E1000_DEV_ID_82546GB_QUAD_COPPER: |
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300 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: |
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301 hw->mac_type = e1000_82546_rev_3; |
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302 break; |
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303 case E1000_DEV_ID_82541EI: |
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304 case E1000_DEV_ID_82541EI_MOBILE: |
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305 case E1000_DEV_ID_82541ER_LOM: |
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306 hw->mac_type = e1000_82541; |
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307 break; |
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308 case E1000_DEV_ID_82541ER: |
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309 case E1000_DEV_ID_82541GI: |
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310 case E1000_DEV_ID_82541GI_LF: |
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311 case E1000_DEV_ID_82541GI_MOBILE: |
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312 hw->mac_type = e1000_82541_rev_2; |
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313 break; |
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314 case E1000_DEV_ID_82547EI: |
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315 case E1000_DEV_ID_82547EI_MOBILE: |
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316 hw->mac_type = e1000_82547; |
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317 break; |
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318 case E1000_DEV_ID_82547GI: |
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319 hw->mac_type = e1000_82547_rev_2; |
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320 break; |
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321 default: |
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322 /* Should never have loaded on this device */ |
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323 return -E1000_ERR_MAC_TYPE; |
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324 } |
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325 |
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326 switch (hw->mac_type) { |
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327 case e1000_82541: |
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328 case e1000_82547: |
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329 case e1000_82541_rev_2: |
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330 case e1000_82547_rev_2: |
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331 hw->asf_firmware_present = true; |
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332 break; |
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333 default: |
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334 break; |
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335 } |
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336 |
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337 /* The 82543 chip does not count tx_carrier_errors properly in |
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338 * FD mode |
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339 */ |
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340 if (hw->mac_type == e1000_82543) |
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341 hw->bad_tx_carr_stats_fd = true; |
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342 |
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343 if (hw->mac_type > e1000_82544) |
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344 hw->has_smbus = true; |
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345 |
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346 return E1000_SUCCESS; |
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347 } |
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348 |
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349 /** |
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350 * e1000_set_media_type - Set media type and TBI compatibility. |
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351 * @hw: Struct containing variables accessed by shared code |
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352 */ |
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353 void e1000_set_media_type(struct e1000_hw *hw) |
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354 { |
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355 u32 status; |
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356 |
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357 e_dbg("e1000_set_media_type"); |
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358 |
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359 if (hw->mac_type != e1000_82543) { |
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360 /* tbi_compatibility is only valid on 82543 */ |
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361 hw->tbi_compatibility_en = false; |
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362 } |
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363 |
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364 switch (hw->device_id) { |
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365 case E1000_DEV_ID_82545GM_SERDES: |
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366 case E1000_DEV_ID_82546GB_SERDES: |
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367 hw->media_type = e1000_media_type_internal_serdes; |
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368 break; |
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369 default: |
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370 switch (hw->mac_type) { |
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371 case e1000_82542_rev2_0: |
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372 case e1000_82542_rev2_1: |
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373 hw->media_type = e1000_media_type_fiber; |
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374 break; |
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375 default: |
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376 status = er32(STATUS); |
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377 if (status & E1000_STATUS_TBIMODE) { |
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378 hw->media_type = e1000_media_type_fiber; |
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379 /* tbi_compatibility not valid on fiber */ |
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380 hw->tbi_compatibility_en = false; |
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381 } else { |
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382 hw->media_type = e1000_media_type_copper; |
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383 } |
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384 break; |
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385 } |
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386 } |
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387 } |
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388 |
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389 /** |
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390 * e1000_reset_hw: reset the hardware completely |
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391 * @hw: Struct containing variables accessed by shared code |
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392 * |
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393 * Reset the transmit and receive units; mask and clear all interrupts. |
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394 */ |
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395 s32 e1000_reset_hw(struct e1000_hw *hw) |
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396 { |
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397 u32 ctrl; |
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398 u32 ctrl_ext; |
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399 u32 icr; |
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400 u32 manc; |
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401 u32 led_ctrl; |
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402 s32 ret_val; |
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403 |
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404 e_dbg("e1000_reset_hw"); |
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405 |
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406 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
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407 if (hw->mac_type == e1000_82542_rev2_0) { |
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408 e_dbg("Disabling MWI on 82542 rev 2.0\n"); |
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409 e1000_pci_clear_mwi(hw); |
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410 } |
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411 |
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412 /* Clear interrupt mask to stop board from generating interrupts */ |
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413 e_dbg("Masking off all interrupts\n"); |
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414 ew32(IMC, 0xffffffff); |
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415 |
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416 /* Disable the Transmit and Receive units. Then delay to allow |
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417 * any pending transactions to complete before we hit the MAC with |
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418 * the global reset. |
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419 */ |
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420 ew32(RCTL, 0); |
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421 ew32(TCTL, E1000_TCTL_PSP); |
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422 E1000_WRITE_FLUSH(); |
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423 |
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424 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ |
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425 hw->tbi_compatibility_on = false; |
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426 |
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427 /* Delay to allow any outstanding PCI transactions to complete before |
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428 * resetting the device |
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429 */ |
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430 msleep(10); |
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431 |
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432 ctrl = er32(CTRL); |
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433 |
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434 /* Must reset the PHY before resetting the MAC */ |
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435 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
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436 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
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437 msleep(5); |
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438 } |
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439 |
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440 /* Issue a global reset to the MAC. This will reset the chip's |
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441 * transmit, receive, DMA, and link units. It will not effect |
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442 * the current PCI configuration. The global reset bit is self- |
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443 * clearing, and should clear within a microsecond. |
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444 */ |
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445 e_dbg("Issuing a global reset to MAC\n"); |
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446 |
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447 switch (hw->mac_type) { |
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448 case e1000_82544: |
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449 case e1000_82540: |
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450 case e1000_82545: |
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451 case e1000_82546: |
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452 case e1000_82541: |
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453 case e1000_82541_rev_2: |
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454 /* These controllers can't ack the 64-bit write when issuing the |
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455 * reset, so use IO-mapping as a workaround to issue the reset */ |
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456 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
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457 break; |
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458 case e1000_82545_rev_3: |
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459 case e1000_82546_rev_3: |
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460 /* Reset is performed on a shadow of the control register */ |
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461 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); |
|
462 break; |
|
463 default: |
|
464 ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
|
465 break; |
|
466 } |
|
467 |
|
468 /* After MAC reset, force reload of EEPROM to restore power-on settings to |
|
469 * device. Later controllers reload the EEPROM automatically, so just wait |
|
470 * for reload to complete. |
|
471 */ |
|
472 switch (hw->mac_type) { |
|
473 case e1000_82542_rev2_0: |
|
474 case e1000_82542_rev2_1: |
|
475 case e1000_82543: |
|
476 case e1000_82544: |
|
477 /* Wait for reset to complete */ |
|
478 udelay(10); |
|
479 ctrl_ext = er32(CTRL_EXT); |
|
480 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
481 ew32(CTRL_EXT, ctrl_ext); |
|
482 E1000_WRITE_FLUSH(); |
|
483 /* Wait for EEPROM reload */ |
|
484 msleep(2); |
|
485 break; |
|
486 case e1000_82541: |
|
487 case e1000_82541_rev_2: |
|
488 case e1000_82547: |
|
489 case e1000_82547_rev_2: |
|
490 /* Wait for EEPROM reload */ |
|
491 msleep(20); |
|
492 break; |
|
493 default: |
|
494 /* Auto read done will delay 5ms or poll based on mac type */ |
|
495 ret_val = e1000_get_auto_rd_done(hw); |
|
496 if (ret_val) |
|
497 return ret_val; |
|
498 break; |
|
499 } |
|
500 |
|
501 /* Disable HW ARPs on ASF enabled adapters */ |
|
502 if (hw->mac_type >= e1000_82540) { |
|
503 manc = er32(MANC); |
|
504 manc &= ~(E1000_MANC_ARP_EN); |
|
505 ew32(MANC, manc); |
|
506 } |
|
507 |
|
508 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
509 e1000_phy_init_script(hw); |
|
510 |
|
511 /* Configure activity LED after PHY reset */ |
|
512 led_ctrl = er32(LEDCTL); |
|
513 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
514 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
515 ew32(LEDCTL, led_ctrl); |
|
516 } |
|
517 |
|
518 /* Clear interrupt mask to stop board from generating interrupts */ |
|
519 e_dbg("Masking off all interrupts\n"); |
|
520 ew32(IMC, 0xffffffff); |
|
521 |
|
522 /* Clear any pending interrupt events. */ |
|
523 icr = er32(ICR); |
|
524 |
|
525 /* If MWI was previously enabled, reenable it. */ |
|
526 if (hw->mac_type == e1000_82542_rev2_0) { |
|
527 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
|
528 e1000_pci_set_mwi(hw); |
|
529 } |
|
530 |
|
531 return E1000_SUCCESS; |
|
532 } |
|
533 |
|
534 /** |
|
535 * e1000_init_hw: Performs basic configuration of the adapter. |
|
536 * @hw: Struct containing variables accessed by shared code |
|
537 * |
|
538 * Assumes that the controller has previously been reset and is in a |
|
539 * post-reset uninitialized state. Initializes the receive address registers, |
|
540 * multicast table, and VLAN filter table. Calls routines to setup link |
|
541 * configuration and flow control settings. Clears all on-chip counters. Leaves |
|
542 * the transmit and receive units disabled and uninitialized. |
|
543 */ |
|
544 s32 e1000_init_hw(struct e1000_hw *hw) |
|
545 { |
|
546 u32 ctrl; |
|
547 u32 i; |
|
548 s32 ret_val; |
|
549 u32 mta_size; |
|
550 u32 ctrl_ext; |
|
551 |
|
552 e_dbg("e1000_init_hw"); |
|
553 |
|
554 /* Initialize Identification LED */ |
|
555 ret_val = e1000_id_led_init(hw); |
|
556 if (ret_val) { |
|
557 e_dbg("Error Initializing Identification LED\n"); |
|
558 return ret_val; |
|
559 } |
|
560 |
|
561 /* Set the media type and TBI compatibility */ |
|
562 e1000_set_media_type(hw); |
|
563 |
|
564 /* Disabling VLAN filtering. */ |
|
565 e_dbg("Initializing the IEEE VLAN\n"); |
|
566 if (hw->mac_type < e1000_82545_rev_3) |
|
567 ew32(VET, 0); |
|
568 e1000_clear_vfta(hw); |
|
569 |
|
570 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
|
571 if (hw->mac_type == e1000_82542_rev2_0) { |
|
572 e_dbg("Disabling MWI on 82542 rev 2.0\n"); |
|
573 e1000_pci_clear_mwi(hw); |
|
574 ew32(RCTL, E1000_RCTL_RST); |
|
575 E1000_WRITE_FLUSH(); |
|
576 msleep(5); |
|
577 } |
|
578 |
|
579 /* Setup the receive address. This involves initializing all of the Receive |
|
580 * Address Registers (RARs 0 - 15). |
|
581 */ |
|
582 e1000_init_rx_addrs(hw); |
|
583 |
|
584 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ |
|
585 if (hw->mac_type == e1000_82542_rev2_0) { |
|
586 ew32(RCTL, 0); |
|
587 E1000_WRITE_FLUSH(); |
|
588 msleep(1); |
|
589 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
|
590 e1000_pci_set_mwi(hw); |
|
591 } |
|
592 |
|
593 /* Zero out the Multicast HASH table */ |
|
594 e_dbg("Zeroing the MTA\n"); |
|
595 mta_size = E1000_MC_TBL_SIZE; |
|
596 for (i = 0; i < mta_size; i++) { |
|
597 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
|
598 /* use write flush to prevent Memory Write Block (MWB) from |
|
599 * occurring when accessing our register space */ |
|
600 E1000_WRITE_FLUSH(); |
|
601 } |
|
602 |
|
603 /* Set the PCI priority bit correctly in the CTRL register. This |
|
604 * determines if the adapter gives priority to receives, or if it |
|
605 * gives equal priority to transmits and receives. Valid only on |
|
606 * 82542 and 82543 silicon. |
|
607 */ |
|
608 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { |
|
609 ctrl = er32(CTRL); |
|
610 ew32(CTRL, ctrl | E1000_CTRL_PRIOR); |
|
611 } |
|
612 |
|
613 switch (hw->mac_type) { |
|
614 case e1000_82545_rev_3: |
|
615 case e1000_82546_rev_3: |
|
616 break; |
|
617 default: |
|
618 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
|
619 if (hw->bus_type == e1000_bus_type_pcix |
|
620 && e1000_pcix_get_mmrbc(hw) > 2048) |
|
621 e1000_pcix_set_mmrbc(hw, 2048); |
|
622 break; |
|
623 } |
|
624 |
|
625 /* Call a subroutine to configure the link and setup flow control. */ |
|
626 ret_val = e1000_setup_link(hw); |
|
627 |
|
628 /* Set the transmit descriptor write-back policy */ |
|
629 if (hw->mac_type > e1000_82544) { |
|
630 ctrl = er32(TXDCTL); |
|
631 ctrl = |
|
632 (ctrl & ~E1000_TXDCTL_WTHRESH) | |
|
633 E1000_TXDCTL_FULL_TX_DESC_WB; |
|
634 ew32(TXDCTL, ctrl); |
|
635 } |
|
636 |
|
637 /* Clear all of the statistics registers (clear on read). It is |
|
638 * important that we do this after we have tried to establish link |
|
639 * because the symbol error count will increment wildly if there |
|
640 * is no link. |
|
641 */ |
|
642 e1000_clear_hw_cntrs(hw); |
|
643 |
|
644 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
|
645 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { |
|
646 ctrl_ext = er32(CTRL_EXT); |
|
647 /* Relaxed ordering must be disabled to avoid a parity |
|
648 * error crash in a PCI slot. */ |
|
649 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
|
650 ew32(CTRL_EXT, ctrl_ext); |
|
651 } |
|
652 |
|
653 return ret_val; |
|
654 } |
|
655 |
|
656 /** |
|
657 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting. |
|
658 * @hw: Struct containing variables accessed by shared code. |
|
659 */ |
|
660 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) |
|
661 { |
|
662 u16 eeprom_data; |
|
663 s32 ret_val; |
|
664 |
|
665 e_dbg("e1000_adjust_serdes_amplitude"); |
|
666 |
|
667 if (hw->media_type != e1000_media_type_internal_serdes) |
|
668 return E1000_SUCCESS; |
|
669 |
|
670 switch (hw->mac_type) { |
|
671 case e1000_82545_rev_3: |
|
672 case e1000_82546_rev_3: |
|
673 break; |
|
674 default: |
|
675 return E1000_SUCCESS; |
|
676 } |
|
677 |
|
678 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, |
|
679 &eeprom_data); |
|
680 if (ret_val) { |
|
681 return ret_val; |
|
682 } |
|
683 |
|
684 if (eeprom_data != EEPROM_RESERVED_WORD) { |
|
685 /* Adjust SERDES output amplitude only. */ |
|
686 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
|
687 ret_val = |
|
688 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
|
689 if (ret_val) |
|
690 return ret_val; |
|
691 } |
|
692 |
|
693 return E1000_SUCCESS; |
|
694 } |
|
695 |
|
696 /** |
|
697 * e1000_setup_link - Configures flow control and link settings. |
|
698 * @hw: Struct containing variables accessed by shared code |
|
699 * |
|
700 * Determines which flow control settings to use. Calls the appropriate media- |
|
701 * specific link configuration function. Configures the flow control settings. |
|
702 * Assuming the adapter has a valid link partner, a valid link should be |
|
703 * established. Assumes the hardware has previously been reset and the |
|
704 * transmitter and receiver are not enabled. |
|
705 */ |
|
706 s32 e1000_setup_link(struct e1000_hw *hw) |
|
707 { |
|
708 u32 ctrl_ext; |
|
709 s32 ret_val; |
|
710 u16 eeprom_data; |
|
711 |
|
712 e_dbg("e1000_setup_link"); |
|
713 |
|
714 /* Read and store word 0x0F of the EEPROM. This word contains bits |
|
715 * that determine the hardware's default PAUSE (flow control) mode, |
|
716 * a bit that determines whether the HW defaults to enabling or |
|
717 * disabling auto-negotiation, and the direction of the |
|
718 * SW defined pins. If there is no SW over-ride of the flow |
|
719 * control setting, then the variable hw->fc will |
|
720 * be initialized based on a value in the EEPROM. |
|
721 */ |
|
722 if (hw->fc == E1000_FC_DEFAULT) { |
|
723 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
|
724 1, &eeprom_data); |
|
725 if (ret_val) { |
|
726 e_dbg("EEPROM Read Error\n"); |
|
727 return -E1000_ERR_EEPROM; |
|
728 } |
|
729 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
|
730 hw->fc = E1000_FC_NONE; |
|
731 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
|
732 EEPROM_WORD0F_ASM_DIR) |
|
733 hw->fc = E1000_FC_TX_PAUSE; |
|
734 else |
|
735 hw->fc = E1000_FC_FULL; |
|
736 } |
|
737 |
|
738 /* We want to save off the original Flow Control configuration just |
|
739 * in case we get disconnected and then reconnected into a different |
|
740 * hub or switch with different Flow Control capabilities. |
|
741 */ |
|
742 if (hw->mac_type == e1000_82542_rev2_0) |
|
743 hw->fc &= (~E1000_FC_TX_PAUSE); |
|
744 |
|
745 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) |
|
746 hw->fc &= (~E1000_FC_RX_PAUSE); |
|
747 |
|
748 hw->original_fc = hw->fc; |
|
749 |
|
750 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc); |
|
751 |
|
752 /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
|
753 * polarity value for the SW controlled pins, and setup the |
|
754 * Extended Device Control reg with that info. |
|
755 * This is needed because one of the SW controlled pins is used for |
|
756 * signal detection. So this should be done before e1000_setup_pcs_link() |
|
757 * or e1000_phy_setup() is called. |
|
758 */ |
|
759 if (hw->mac_type == e1000_82543) { |
|
760 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
|
761 1, &eeprom_data); |
|
762 if (ret_val) { |
|
763 e_dbg("EEPROM Read Error\n"); |
|
764 return -E1000_ERR_EEPROM; |
|
765 } |
|
766 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
|
767 SWDPIO__EXT_SHIFT); |
|
768 ew32(CTRL_EXT, ctrl_ext); |
|
769 } |
|
770 |
|
771 /* Call the necessary subroutine to configure the link. */ |
|
772 ret_val = (hw->media_type == e1000_media_type_copper) ? |
|
773 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); |
|
774 |
|
775 /* Initialize the flow control address, type, and PAUSE timer |
|
776 * registers to their default values. This is done even if flow |
|
777 * control is disabled, because it does not hurt anything to |
|
778 * initialize these registers. |
|
779 */ |
|
780 e_dbg("Initializing the Flow Control address, type and timer regs\n"); |
|
781 |
|
782 ew32(FCT, FLOW_CONTROL_TYPE); |
|
783 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
|
784 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); |
|
785 |
|
786 ew32(FCTTV, hw->fc_pause_time); |
|
787 |
|
788 /* Set the flow control receive threshold registers. Normally, |
|
789 * these registers will be set to a default threshold that may be |
|
790 * adjusted later by the driver's runtime code. However, if the |
|
791 * ability to transmit pause frames in not enabled, then these |
|
792 * registers will be set to 0. |
|
793 */ |
|
794 if (!(hw->fc & E1000_FC_TX_PAUSE)) { |
|
795 ew32(FCRTL, 0); |
|
796 ew32(FCRTH, 0); |
|
797 } else { |
|
798 /* We need to set up the Receive Threshold high and low water marks |
|
799 * as well as (optionally) enabling the transmission of XON frames. |
|
800 */ |
|
801 if (hw->fc_send_xon) { |
|
802 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); |
|
803 ew32(FCRTH, hw->fc_high_water); |
|
804 } else { |
|
805 ew32(FCRTL, hw->fc_low_water); |
|
806 ew32(FCRTH, hw->fc_high_water); |
|
807 } |
|
808 } |
|
809 return ret_val; |
|
810 } |
|
811 |
|
812 /** |
|
813 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link |
|
814 * @hw: Struct containing variables accessed by shared code |
|
815 * |
|
816 * Manipulates Physical Coding Sublayer functions in order to configure |
|
817 * link. Assumes the hardware has been previously reset and the transmitter |
|
818 * and receiver are not enabled. |
|
819 */ |
|
820 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) |
|
821 { |
|
822 u32 ctrl; |
|
823 u32 status; |
|
824 u32 txcw = 0; |
|
825 u32 i; |
|
826 u32 signal = 0; |
|
827 s32 ret_val; |
|
828 |
|
829 e_dbg("e1000_setup_fiber_serdes_link"); |
|
830 |
|
831 /* On adapters with a MAC newer than 82544, SWDP 1 will be |
|
832 * set when the optics detect a signal. On older adapters, it will be |
|
833 * cleared when there is a signal. This applies to fiber media only. |
|
834 * If we're on serdes media, adjust the output amplitude to value |
|
835 * set in the EEPROM. |
|
836 */ |
|
837 ctrl = er32(CTRL); |
|
838 if (hw->media_type == e1000_media_type_fiber) |
|
839 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
|
840 |
|
841 ret_val = e1000_adjust_serdes_amplitude(hw); |
|
842 if (ret_val) |
|
843 return ret_val; |
|
844 |
|
845 /* Take the link out of reset */ |
|
846 ctrl &= ~(E1000_CTRL_LRST); |
|
847 |
|
848 /* Adjust VCO speed to improve BER performance */ |
|
849 ret_val = e1000_set_vco_speed(hw); |
|
850 if (ret_val) |
|
851 return ret_val; |
|
852 |
|
853 e1000_config_collision_dist(hw); |
|
854 |
|
855 /* Check for a software override of the flow control settings, and setup |
|
856 * the device accordingly. If auto-negotiation is enabled, then software |
|
857 * will have to set the "PAUSE" bits to the correct value in the Tranmsit |
|
858 * Config Word Register (TXCW) and re-start auto-negotiation. However, if |
|
859 * auto-negotiation is disabled, then software will have to manually |
|
860 * configure the two flow control enable bits in the CTRL register. |
|
861 * |
|
862 * The possible values of the "fc" parameter are: |
|
863 * 0: Flow control is completely disabled |
|
864 * 1: Rx flow control is enabled (we can receive pause frames, but |
|
865 * not send pause frames). |
|
866 * 2: Tx flow control is enabled (we can send pause frames but we do |
|
867 * not support receiving pause frames). |
|
868 * 3: Both Rx and TX flow control (symmetric) are enabled. |
|
869 */ |
|
870 switch (hw->fc) { |
|
871 case E1000_FC_NONE: |
|
872 /* Flow control is completely disabled by a software over-ride. */ |
|
873 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
|
874 break; |
|
875 case E1000_FC_RX_PAUSE: |
|
876 /* RX Flow control is enabled and TX Flow control is disabled by a |
|
877 * software over-ride. Since there really isn't a way to advertise |
|
878 * that we are capable of RX Pause ONLY, we will advertise that we |
|
879 * support both symmetric and asymmetric RX PAUSE. Later, we will |
|
880 * disable the adapter's ability to send PAUSE frames. |
|
881 */ |
|
882 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
883 break; |
|
884 case E1000_FC_TX_PAUSE: |
|
885 /* TX Flow control is enabled, and RX Flow control is disabled, by a |
|
886 * software over-ride. |
|
887 */ |
|
888 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
|
889 break; |
|
890 case E1000_FC_FULL: |
|
891 /* Flow control (both RX and TX) is enabled by a software over-ride. */ |
|
892 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
893 break; |
|
894 default: |
|
895 e_dbg("Flow control param set incorrectly\n"); |
|
896 return -E1000_ERR_CONFIG; |
|
897 break; |
|
898 } |
|
899 |
|
900 /* Since auto-negotiation is enabled, take the link out of reset (the link |
|
901 * will be in reset, because we previously reset the chip). This will |
|
902 * restart auto-negotiation. If auto-negotiation is successful then the |
|
903 * link-up status bit will be set and the flow control enable bits (RFCE |
|
904 * and TFCE) will be set according to their negotiated value. |
|
905 */ |
|
906 e_dbg("Auto-negotiation enabled\n"); |
|
907 |
|
908 ew32(TXCW, txcw); |
|
909 ew32(CTRL, ctrl); |
|
910 E1000_WRITE_FLUSH(); |
|
911 |
|
912 hw->txcw = txcw; |
|
913 msleep(1); |
|
914 |
|
915 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" |
|
916 * indication in the Device Status Register. Time-out if a link isn't |
|
917 * seen in 500 milliseconds seconds (Auto-negotiation should complete in |
|
918 * less than 500 milliseconds even if the other end is doing it in SW). |
|
919 * For internal serdes, we just assume a signal is present, then poll. |
|
920 */ |
|
921 if (hw->media_type == e1000_media_type_internal_serdes || |
|
922 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
|
923 e_dbg("Looking for Link\n"); |
|
924 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
|
925 msleep(10); |
|
926 status = er32(STATUS); |
|
927 if (status & E1000_STATUS_LU) |
|
928 break; |
|
929 } |
|
930 if (i == (LINK_UP_TIMEOUT / 10)) { |
|
931 e_dbg("Never got a valid link from auto-neg!!!\n"); |
|
932 hw->autoneg_failed = 1; |
|
933 /* AutoNeg failed to achieve a link, so we'll call |
|
934 * e1000_check_for_link. This routine will force the link up if |
|
935 * we detect a signal. This will allow us to communicate with |
|
936 * non-autonegotiating link partners. |
|
937 */ |
|
938 ret_val = e1000_check_for_link(hw); |
|
939 if (ret_val) { |
|
940 e_dbg("Error while checking for link\n"); |
|
941 return ret_val; |
|
942 } |
|
943 hw->autoneg_failed = 0; |
|
944 } else { |
|
945 hw->autoneg_failed = 0; |
|
946 e_dbg("Valid Link Found\n"); |
|
947 } |
|
948 } else { |
|
949 e_dbg("No Signal Detected\n"); |
|
950 } |
|
951 return E1000_SUCCESS; |
|
952 } |
|
953 |
|
954 /** |
|
955 * e1000_copper_link_preconfig - early configuration for copper |
|
956 * @hw: Struct containing variables accessed by shared code |
|
957 * |
|
958 * Make sure we have a valid PHY and change PHY mode before link setup. |
|
959 */ |
|
960 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) |
|
961 { |
|
962 u32 ctrl; |
|
963 s32 ret_val; |
|
964 u16 phy_data; |
|
965 |
|
966 e_dbg("e1000_copper_link_preconfig"); |
|
967 |
|
968 ctrl = er32(CTRL); |
|
969 /* With 82543, we need to force speed and duplex on the MAC equal to what |
|
970 * the PHY speed and duplex configuration is. In addition, we need to |
|
971 * perform a hardware reset on the PHY to take it out of reset. |
|
972 */ |
|
973 if (hw->mac_type > e1000_82543) { |
|
974 ctrl |= E1000_CTRL_SLU; |
|
975 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
976 ew32(CTRL, ctrl); |
|
977 } else { |
|
978 ctrl |= |
|
979 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); |
|
980 ew32(CTRL, ctrl); |
|
981 ret_val = e1000_phy_hw_reset(hw); |
|
982 if (ret_val) |
|
983 return ret_val; |
|
984 } |
|
985 |
|
986 /* Make sure we have a valid PHY */ |
|
987 ret_val = e1000_detect_gig_phy(hw); |
|
988 if (ret_val) { |
|
989 e_dbg("Error, did not detect valid phy.\n"); |
|
990 return ret_val; |
|
991 } |
|
992 e_dbg("Phy ID = %x\n", hw->phy_id); |
|
993 |
|
994 /* Set PHY to class A mode (if necessary) */ |
|
995 ret_val = e1000_set_phy_mode(hw); |
|
996 if (ret_val) |
|
997 return ret_val; |
|
998 |
|
999 if ((hw->mac_type == e1000_82545_rev_3) || |
|
1000 (hw->mac_type == e1000_82546_rev_3)) { |
|
1001 ret_val = |
|
1002 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1003 phy_data |= 0x00000008; |
|
1004 ret_val = |
|
1005 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1006 } |
|
1007 |
|
1008 if (hw->mac_type <= e1000_82543 || |
|
1009 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || |
|
1010 hw->mac_type == e1000_82541_rev_2 |
|
1011 || hw->mac_type == e1000_82547_rev_2) |
|
1012 hw->phy_reset_disable = false; |
|
1013 |
|
1014 return E1000_SUCCESS; |
|
1015 } |
|
1016 |
|
1017 /** |
|
1018 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series. |
|
1019 * @hw: Struct containing variables accessed by shared code |
|
1020 */ |
|
1021 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) |
|
1022 { |
|
1023 u32 led_ctrl; |
|
1024 s32 ret_val; |
|
1025 u16 phy_data; |
|
1026 |
|
1027 e_dbg("e1000_copper_link_igp_setup"); |
|
1028 |
|
1029 if (hw->phy_reset_disable) |
|
1030 return E1000_SUCCESS; |
|
1031 |
|
1032 ret_val = e1000_phy_reset(hw); |
|
1033 if (ret_val) { |
|
1034 e_dbg("Error Resetting the PHY\n"); |
|
1035 return ret_val; |
|
1036 } |
|
1037 |
|
1038 /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
|
1039 msleep(15); |
|
1040 /* Configure activity LED after PHY reset */ |
|
1041 led_ctrl = er32(LEDCTL); |
|
1042 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
1043 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
1044 ew32(LEDCTL, led_ctrl); |
|
1045 |
|
1046 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ |
|
1047 if (hw->phy_type == e1000_phy_igp) { |
|
1048 /* disable lplu d3 during driver init */ |
|
1049 ret_val = e1000_set_d3_lplu_state(hw, false); |
|
1050 if (ret_val) { |
|
1051 e_dbg("Error Disabling LPLU D3\n"); |
|
1052 return ret_val; |
|
1053 } |
|
1054 } |
|
1055 |
|
1056 /* Configure mdi-mdix settings */ |
|
1057 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
1058 if (ret_val) |
|
1059 return ret_val; |
|
1060 |
|
1061 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
1062 hw->dsp_config_state = e1000_dsp_config_disabled; |
|
1063 /* Force MDI for earlier revs of the IGP PHY */ |
|
1064 phy_data &= |
|
1065 ~(IGP01E1000_PSCR_AUTO_MDIX | |
|
1066 IGP01E1000_PSCR_FORCE_MDI_MDIX); |
|
1067 hw->mdix = 1; |
|
1068 |
|
1069 } else { |
|
1070 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
1071 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
1072 |
|
1073 switch (hw->mdix) { |
|
1074 case 1: |
|
1075 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1076 break; |
|
1077 case 2: |
|
1078 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1079 break; |
|
1080 case 0: |
|
1081 default: |
|
1082 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; |
|
1083 break; |
|
1084 } |
|
1085 } |
|
1086 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
1087 if (ret_val) |
|
1088 return ret_val; |
|
1089 |
|
1090 /* set auto-master slave resolution settings */ |
|
1091 if (hw->autoneg) { |
|
1092 e1000_ms_type phy_ms_setting = hw->master_slave; |
|
1093 |
|
1094 if (hw->ffe_config_state == e1000_ffe_config_active) |
|
1095 hw->ffe_config_state = e1000_ffe_config_enabled; |
|
1096 |
|
1097 if (hw->dsp_config_state == e1000_dsp_config_activated) |
|
1098 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
1099 |
|
1100 /* when autonegotiation advertisement is only 1000Mbps then we |
|
1101 * should disable SmartSpeed and enable Auto MasterSlave |
|
1102 * resolution as hardware default. */ |
|
1103 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
|
1104 /* Disable SmartSpeed */ |
|
1105 ret_val = |
|
1106 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1107 &phy_data); |
|
1108 if (ret_val) |
|
1109 return ret_val; |
|
1110 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
1111 ret_val = |
|
1112 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1113 phy_data); |
|
1114 if (ret_val) |
|
1115 return ret_val; |
|
1116 /* Set auto Master/Slave resolution process */ |
|
1117 ret_val = |
|
1118 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
|
1119 if (ret_val) |
|
1120 return ret_val; |
|
1121 phy_data &= ~CR_1000T_MS_ENABLE; |
|
1122 ret_val = |
|
1123 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
|
1124 if (ret_val) |
|
1125 return ret_val; |
|
1126 } |
|
1127 |
|
1128 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
|
1129 if (ret_val) |
|
1130 return ret_val; |
|
1131 |
|
1132 /* load defaults for future use */ |
|
1133 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? |
|
1134 ((phy_data & CR_1000T_MS_VALUE) ? |
|
1135 e1000_ms_force_master : |
|
1136 e1000_ms_force_slave) : e1000_ms_auto; |
|
1137 |
|
1138 switch (phy_ms_setting) { |
|
1139 case e1000_ms_force_master: |
|
1140 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
|
1141 break; |
|
1142 case e1000_ms_force_slave: |
|
1143 phy_data |= CR_1000T_MS_ENABLE; |
|
1144 phy_data &= ~(CR_1000T_MS_VALUE); |
|
1145 break; |
|
1146 case e1000_ms_auto: |
|
1147 phy_data &= ~CR_1000T_MS_ENABLE; |
|
1148 default: |
|
1149 break; |
|
1150 } |
|
1151 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
|
1152 if (ret_val) |
|
1153 return ret_val; |
|
1154 } |
|
1155 |
|
1156 return E1000_SUCCESS; |
|
1157 } |
|
1158 |
|
1159 /** |
|
1160 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series. |
|
1161 * @hw: Struct containing variables accessed by shared code |
|
1162 */ |
|
1163 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) |
|
1164 { |
|
1165 s32 ret_val; |
|
1166 u16 phy_data; |
|
1167 |
|
1168 e_dbg("e1000_copper_link_mgp_setup"); |
|
1169 |
|
1170 if (hw->phy_reset_disable) |
|
1171 return E1000_SUCCESS; |
|
1172 |
|
1173 /* Enable CRS on TX. This must be set for half-duplex operation. */ |
|
1174 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1175 if (ret_val) |
|
1176 return ret_val; |
|
1177 |
|
1178 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
1179 |
|
1180 /* Options: |
|
1181 * MDI/MDI-X = 0 (default) |
|
1182 * 0 - Auto for all speeds |
|
1183 * 1 - MDI mode |
|
1184 * 2 - MDI-X mode |
|
1185 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
|
1186 */ |
|
1187 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
1188 |
|
1189 switch (hw->mdix) { |
|
1190 case 1: |
|
1191 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
|
1192 break; |
|
1193 case 2: |
|
1194 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
|
1195 break; |
|
1196 case 3: |
|
1197 phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
|
1198 break; |
|
1199 case 0: |
|
1200 default: |
|
1201 phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
|
1202 break; |
|
1203 } |
|
1204 |
|
1205 /* Options: |
|
1206 * disable_polarity_correction = 0 (default) |
|
1207 * Automatic Correction for Reversed Cable Polarity |
|
1208 * 0 - Disabled |
|
1209 * 1 - Enabled |
|
1210 */ |
|
1211 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
|
1212 if (hw->disable_polarity_correction == 1) |
|
1213 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
|
1214 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1215 if (ret_val) |
|
1216 return ret_val; |
|
1217 |
|
1218 if (hw->phy_revision < M88E1011_I_REV_4) { |
|
1219 /* Force TX_CLK in the Extended PHY Specific Control Register |
|
1220 * to 25MHz clock. |
|
1221 */ |
|
1222 ret_val = |
|
1223 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
|
1224 &phy_data); |
|
1225 if (ret_val) |
|
1226 return ret_val; |
|
1227 |
|
1228 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
1229 |
|
1230 if ((hw->phy_revision == E1000_REVISION_2) && |
|
1231 (hw->phy_id == M88E1111_I_PHY_ID)) { |
|
1232 /* Vidalia Phy, set the downshift counter to 5x */ |
|
1233 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); |
|
1234 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
|
1235 ret_val = e1000_write_phy_reg(hw, |
|
1236 M88E1000_EXT_PHY_SPEC_CTRL, |
|
1237 phy_data); |
|
1238 if (ret_val) |
|
1239 return ret_val; |
|
1240 } else { |
|
1241 /* Configure Master and Slave downshift values */ |
|
1242 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
|
1243 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
|
1244 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
|
1245 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
|
1246 ret_val = e1000_write_phy_reg(hw, |
|
1247 M88E1000_EXT_PHY_SPEC_CTRL, |
|
1248 phy_data); |
|
1249 if (ret_val) |
|
1250 return ret_val; |
|
1251 } |
|
1252 } |
|
1253 |
|
1254 /* SW Reset the PHY so all changes take effect */ |
|
1255 ret_val = e1000_phy_reset(hw); |
|
1256 if (ret_val) { |
|
1257 e_dbg("Error Resetting the PHY\n"); |
|
1258 return ret_val; |
|
1259 } |
|
1260 |
|
1261 return E1000_SUCCESS; |
|
1262 } |
|
1263 |
|
1264 /** |
|
1265 * e1000_copper_link_autoneg - setup auto-neg |
|
1266 * @hw: Struct containing variables accessed by shared code |
|
1267 * |
|
1268 * Setup auto-negotiation and flow control advertisements, |
|
1269 * and then perform auto-negotiation. |
|
1270 */ |
|
1271 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) |
|
1272 { |
|
1273 s32 ret_val; |
|
1274 u16 phy_data; |
|
1275 |
|
1276 e_dbg("e1000_copper_link_autoneg"); |
|
1277 |
|
1278 /* Perform some bounds checking on the hw->autoneg_advertised |
|
1279 * parameter. If this variable is zero, then set it to the default. |
|
1280 */ |
|
1281 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
1282 |
|
1283 /* If autoneg_advertised is zero, we assume it was not defaulted |
|
1284 * by the calling code so we set to advertise full capability. |
|
1285 */ |
|
1286 if (hw->autoneg_advertised == 0) |
|
1287 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
1288 |
|
1289 e_dbg("Reconfiguring auto-neg advertisement params\n"); |
|
1290 ret_val = e1000_phy_setup_autoneg(hw); |
|
1291 if (ret_val) { |
|
1292 e_dbg("Error Setting up Auto-Negotiation\n"); |
|
1293 return ret_val; |
|
1294 } |
|
1295 e_dbg("Restarting Auto-Neg\n"); |
|
1296 |
|
1297 /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
|
1298 * the Auto Neg Restart bit in the PHY control register. |
|
1299 */ |
|
1300 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
|
1301 if (ret_val) |
|
1302 return ret_val; |
|
1303 |
|
1304 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
|
1305 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
|
1306 if (ret_val) |
|
1307 return ret_val; |
|
1308 |
|
1309 /* Does the user want to wait for Auto-Neg to complete here, or |
|
1310 * check at a later time (for example, callback routine). |
|
1311 */ |
|
1312 if (hw->wait_autoneg_complete) { |
|
1313 ret_val = e1000_wait_autoneg(hw); |
|
1314 if (ret_val) { |
|
1315 e_dbg |
|
1316 ("Error while waiting for autoneg to complete\n"); |
|
1317 return ret_val; |
|
1318 } |
|
1319 } |
|
1320 |
|
1321 hw->get_link_status = true; |
|
1322 |
|
1323 return E1000_SUCCESS; |
|
1324 } |
|
1325 |
|
1326 /** |
|
1327 * e1000_copper_link_postconfig - post link setup |
|
1328 * @hw: Struct containing variables accessed by shared code |
|
1329 * |
|
1330 * Config the MAC and the PHY after link is up. |
|
1331 * 1) Set up the MAC to the current PHY speed/duplex |
|
1332 * if we are on 82543. If we |
|
1333 * are on newer silicon, we only need to configure |
|
1334 * collision distance in the Transmit Control Register. |
|
1335 * 2) Set up flow control on the MAC to that established with |
|
1336 * the link partner. |
|
1337 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
|
1338 */ |
|
1339 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) |
|
1340 { |
|
1341 s32 ret_val; |
|
1342 e_dbg("e1000_copper_link_postconfig"); |
|
1343 |
|
1344 if (hw->mac_type >= e1000_82544) { |
|
1345 e1000_config_collision_dist(hw); |
|
1346 } else { |
|
1347 ret_val = e1000_config_mac_to_phy(hw); |
|
1348 if (ret_val) { |
|
1349 e_dbg("Error configuring MAC to PHY settings\n"); |
|
1350 return ret_val; |
|
1351 } |
|
1352 } |
|
1353 ret_val = e1000_config_fc_after_link_up(hw); |
|
1354 if (ret_val) { |
|
1355 e_dbg("Error Configuring Flow Control\n"); |
|
1356 return ret_val; |
|
1357 } |
|
1358 |
|
1359 /* Config DSP to improve Giga link quality */ |
|
1360 if (hw->phy_type == e1000_phy_igp) { |
|
1361 ret_val = e1000_config_dsp_after_link_change(hw, true); |
|
1362 if (ret_val) { |
|
1363 e_dbg("Error Configuring DSP after link up\n"); |
|
1364 return ret_val; |
|
1365 } |
|
1366 } |
|
1367 |
|
1368 return E1000_SUCCESS; |
|
1369 } |
|
1370 |
|
1371 /** |
|
1372 * e1000_setup_copper_link - phy/speed/duplex setting |
|
1373 * @hw: Struct containing variables accessed by shared code |
|
1374 * |
|
1375 * Detects which PHY is present and sets up the speed and duplex |
|
1376 */ |
|
1377 static s32 e1000_setup_copper_link(struct e1000_hw *hw) |
|
1378 { |
|
1379 s32 ret_val; |
|
1380 u16 i; |
|
1381 u16 phy_data; |
|
1382 |
|
1383 e_dbg("e1000_setup_copper_link"); |
|
1384 |
|
1385 /* Check if it is a valid PHY and set PHY mode if necessary. */ |
|
1386 ret_val = e1000_copper_link_preconfig(hw); |
|
1387 if (ret_val) |
|
1388 return ret_val; |
|
1389 |
|
1390 if (hw->phy_type == e1000_phy_igp) { |
|
1391 ret_val = e1000_copper_link_igp_setup(hw); |
|
1392 if (ret_val) |
|
1393 return ret_val; |
|
1394 } else if (hw->phy_type == e1000_phy_m88) { |
|
1395 ret_val = e1000_copper_link_mgp_setup(hw); |
|
1396 if (ret_val) |
|
1397 return ret_val; |
|
1398 } |
|
1399 |
|
1400 if (hw->autoneg) { |
|
1401 /* Setup autoneg and flow control advertisement |
|
1402 * and perform autonegotiation */ |
|
1403 ret_val = e1000_copper_link_autoneg(hw); |
|
1404 if (ret_val) |
|
1405 return ret_val; |
|
1406 } else { |
|
1407 /* PHY will be set to 10H, 10F, 100H,or 100F |
|
1408 * depending on value from forced_speed_duplex. */ |
|
1409 e_dbg("Forcing speed and duplex\n"); |
|
1410 ret_val = e1000_phy_force_speed_duplex(hw); |
|
1411 if (ret_val) { |
|
1412 e_dbg("Error Forcing Speed and Duplex\n"); |
|
1413 return ret_val; |
|
1414 } |
|
1415 } |
|
1416 |
|
1417 /* Check link status. Wait up to 100 microseconds for link to become |
|
1418 * valid. |
|
1419 */ |
|
1420 for (i = 0; i < 10; i++) { |
|
1421 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
1422 if (ret_val) |
|
1423 return ret_val; |
|
1424 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
1425 if (ret_val) |
|
1426 return ret_val; |
|
1427 |
|
1428 if (phy_data & MII_SR_LINK_STATUS) { |
|
1429 /* Config the MAC and PHY after link is up */ |
|
1430 ret_val = e1000_copper_link_postconfig(hw); |
|
1431 if (ret_val) |
|
1432 return ret_val; |
|
1433 |
|
1434 e_dbg("Valid link established!!!\n"); |
|
1435 return E1000_SUCCESS; |
|
1436 } |
|
1437 udelay(10); |
|
1438 } |
|
1439 |
|
1440 e_dbg("Unable to establish link!!!\n"); |
|
1441 return E1000_SUCCESS; |
|
1442 } |
|
1443 |
|
1444 /** |
|
1445 * e1000_phy_setup_autoneg - phy settings |
|
1446 * @hw: Struct containing variables accessed by shared code |
|
1447 * |
|
1448 * Configures PHY autoneg and flow control advertisement settings |
|
1449 */ |
|
1450 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) |
|
1451 { |
|
1452 s32 ret_val; |
|
1453 u16 mii_autoneg_adv_reg; |
|
1454 u16 mii_1000t_ctrl_reg; |
|
1455 |
|
1456 e_dbg("e1000_phy_setup_autoneg"); |
|
1457 |
|
1458 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
|
1459 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
|
1460 if (ret_val) |
|
1461 return ret_val; |
|
1462 |
|
1463 /* Read the MII 1000Base-T Control Register (Address 9). */ |
|
1464 ret_val = |
|
1465 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
|
1466 if (ret_val) |
|
1467 return ret_val; |
|
1468 |
|
1469 /* Need to parse both autoneg_advertised and fc and set up |
|
1470 * the appropriate PHY registers. First we will parse for |
|
1471 * autoneg_advertised software override. Since we can advertise |
|
1472 * a plethora of combinations, we need to check each bit |
|
1473 * individually. |
|
1474 */ |
|
1475 |
|
1476 /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
|
1477 * Advertisement Register (Address 4) and the 1000 mb speed bits in |
|
1478 * the 1000Base-T Control Register (Address 9). |
|
1479 */ |
|
1480 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; |
|
1481 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; |
|
1482 |
|
1483 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised); |
|
1484 |
|
1485 /* Do we want to advertise 10 Mb Half Duplex? */ |
|
1486 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { |
|
1487 e_dbg("Advertise 10mb Half duplex\n"); |
|
1488 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
|
1489 } |
|
1490 |
|
1491 /* Do we want to advertise 10 Mb Full Duplex? */ |
|
1492 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { |
|
1493 e_dbg("Advertise 10mb Full duplex\n"); |
|
1494 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
|
1495 } |
|
1496 |
|
1497 /* Do we want to advertise 100 Mb Half Duplex? */ |
|
1498 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { |
|
1499 e_dbg("Advertise 100mb Half duplex\n"); |
|
1500 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
|
1501 } |
|
1502 |
|
1503 /* Do we want to advertise 100 Mb Full Duplex? */ |
|
1504 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { |
|
1505 e_dbg("Advertise 100mb Full duplex\n"); |
|
1506 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
|
1507 } |
|
1508 |
|
1509 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
|
1510 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
|
1511 e_dbg |
|
1512 ("Advertise 1000mb Half duplex requested, request denied!\n"); |
|
1513 } |
|
1514 |
|
1515 /* Do we want to advertise 1000 Mb Full Duplex? */ |
|
1516 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
|
1517 e_dbg("Advertise 1000mb Full duplex\n"); |
|
1518 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
|
1519 } |
|
1520 |
|
1521 /* Check for a software override of the flow control settings, and |
|
1522 * setup the PHY advertisement registers accordingly. If |
|
1523 * auto-negotiation is enabled, then software will have to set the |
|
1524 * "PAUSE" bits to the correct value in the Auto-Negotiation |
|
1525 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. |
|
1526 * |
|
1527 * The possible values of the "fc" parameter are: |
|
1528 * 0: Flow control is completely disabled |
|
1529 * 1: Rx flow control is enabled (we can receive pause frames |
|
1530 * but not send pause frames). |
|
1531 * 2: Tx flow control is enabled (we can send pause frames |
|
1532 * but we do not support receiving pause frames). |
|
1533 * 3: Both Rx and TX flow control (symmetric) are enabled. |
|
1534 * other: No software override. The flow control configuration |
|
1535 * in the EEPROM is used. |
|
1536 */ |
|
1537 switch (hw->fc) { |
|
1538 case E1000_FC_NONE: /* 0 */ |
|
1539 /* Flow control (RX & TX) is completely disabled by a |
|
1540 * software over-ride. |
|
1541 */ |
|
1542 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1543 break; |
|
1544 case E1000_FC_RX_PAUSE: /* 1 */ |
|
1545 /* RX Flow control is enabled, and TX Flow control is |
|
1546 * disabled, by a software over-ride. |
|
1547 */ |
|
1548 /* Since there really isn't a way to advertise that we are |
|
1549 * capable of RX Pause ONLY, we will advertise that we |
|
1550 * support both symmetric and asymmetric RX PAUSE. Later |
|
1551 * (in e1000_config_fc_after_link_up) we will disable the |
|
1552 *hw's ability to send PAUSE frames. |
|
1553 */ |
|
1554 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1555 break; |
|
1556 case E1000_FC_TX_PAUSE: /* 2 */ |
|
1557 /* TX Flow control is enabled, and RX Flow control is |
|
1558 * disabled, by a software over-ride. |
|
1559 */ |
|
1560 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
|
1561 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
|
1562 break; |
|
1563 case E1000_FC_FULL: /* 3 */ |
|
1564 /* Flow control (both RX and TX) is enabled by a software |
|
1565 * over-ride. |
|
1566 */ |
|
1567 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1568 break; |
|
1569 default: |
|
1570 e_dbg("Flow control param set incorrectly\n"); |
|
1571 return -E1000_ERR_CONFIG; |
|
1572 } |
|
1573 |
|
1574 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
|
1575 if (ret_val) |
|
1576 return ret_val; |
|
1577 |
|
1578 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
|
1579 |
|
1580 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
|
1581 if (ret_val) |
|
1582 return ret_val; |
|
1583 |
|
1584 return E1000_SUCCESS; |
|
1585 } |
|
1586 |
|
1587 /** |
|
1588 * e1000_phy_force_speed_duplex - force link settings |
|
1589 * @hw: Struct containing variables accessed by shared code |
|
1590 * |
|
1591 * Force PHY speed and duplex settings to hw->forced_speed_duplex |
|
1592 */ |
|
1593 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) |
|
1594 { |
|
1595 u32 ctrl; |
|
1596 s32 ret_val; |
|
1597 u16 mii_ctrl_reg; |
|
1598 u16 mii_status_reg; |
|
1599 u16 phy_data; |
|
1600 u16 i; |
|
1601 |
|
1602 e_dbg("e1000_phy_force_speed_duplex"); |
|
1603 |
|
1604 /* Turn off Flow control if we are forcing speed and duplex. */ |
|
1605 hw->fc = E1000_FC_NONE; |
|
1606 |
|
1607 e_dbg("hw->fc = %d\n", hw->fc); |
|
1608 |
|
1609 /* Read the Device Control Register. */ |
|
1610 ctrl = er32(CTRL); |
|
1611 |
|
1612 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ |
|
1613 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1614 ctrl &= ~(DEVICE_SPEED_MASK); |
|
1615 |
|
1616 /* Clear the Auto Speed Detect Enable bit. */ |
|
1617 ctrl &= ~E1000_CTRL_ASDE; |
|
1618 |
|
1619 /* Read the MII Control Register. */ |
|
1620 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); |
|
1621 if (ret_val) |
|
1622 return ret_val; |
|
1623 |
|
1624 /* We need to disable autoneg in order to force link and duplex. */ |
|
1625 |
|
1626 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; |
|
1627 |
|
1628 /* Are we forcing Full or Half Duplex? */ |
|
1629 if (hw->forced_speed_duplex == e1000_100_full || |
|
1630 hw->forced_speed_duplex == e1000_10_full) { |
|
1631 /* We want to force full duplex so we SET the full duplex bits in the |
|
1632 * Device and MII Control Registers. |
|
1633 */ |
|
1634 ctrl |= E1000_CTRL_FD; |
|
1635 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; |
|
1636 e_dbg("Full Duplex\n"); |
|
1637 } else { |
|
1638 /* We want to force half duplex so we CLEAR the full duplex bits in |
|
1639 * the Device and MII Control Registers. |
|
1640 */ |
|
1641 ctrl &= ~E1000_CTRL_FD; |
|
1642 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; |
|
1643 e_dbg("Half Duplex\n"); |
|
1644 } |
|
1645 |
|
1646 /* Are we forcing 100Mbps??? */ |
|
1647 if (hw->forced_speed_duplex == e1000_100_full || |
|
1648 hw->forced_speed_duplex == e1000_100_half) { |
|
1649 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ |
|
1650 ctrl |= E1000_CTRL_SPD_100; |
|
1651 mii_ctrl_reg |= MII_CR_SPEED_100; |
|
1652 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
|
1653 e_dbg("Forcing 100mb "); |
|
1654 } else { |
|
1655 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ |
|
1656 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
|
1657 mii_ctrl_reg |= MII_CR_SPEED_10; |
|
1658 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
|
1659 e_dbg("Forcing 10mb "); |
|
1660 } |
|
1661 |
|
1662 e1000_config_collision_dist(hw); |
|
1663 |
|
1664 /* Write the configured values back to the Device Control Reg. */ |
|
1665 ew32(CTRL, ctrl); |
|
1666 |
|
1667 if (hw->phy_type == e1000_phy_m88) { |
|
1668 ret_val = |
|
1669 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1670 if (ret_val) |
|
1671 return ret_val; |
|
1672 |
|
1673 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
|
1674 * forced whenever speed are duplex are forced. |
|
1675 */ |
|
1676 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
1677 ret_val = |
|
1678 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1679 if (ret_val) |
|
1680 return ret_val; |
|
1681 |
|
1682 e_dbg("M88E1000 PSCR: %x\n", phy_data); |
|
1683 |
|
1684 /* Need to reset the PHY or these changes will be ignored */ |
|
1685 mii_ctrl_reg |= MII_CR_RESET; |
|
1686 |
|
1687 /* Disable MDI-X support for 10/100 */ |
|
1688 } else { |
|
1689 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
|
1690 * forced whenever speed or duplex are forced. |
|
1691 */ |
|
1692 ret_val = |
|
1693 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
1694 if (ret_val) |
|
1695 return ret_val; |
|
1696 |
|
1697 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
1698 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1699 |
|
1700 ret_val = |
|
1701 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
1702 if (ret_val) |
|
1703 return ret_val; |
|
1704 } |
|
1705 |
|
1706 /* Write back the modified PHY MII control register. */ |
|
1707 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); |
|
1708 if (ret_val) |
|
1709 return ret_val; |
|
1710 |
|
1711 udelay(1); |
|
1712 |
|
1713 /* The wait_autoneg_complete flag may be a little misleading here. |
|
1714 * Since we are forcing speed and duplex, Auto-Neg is not enabled. |
|
1715 * But we do want to delay for a period while forcing only so we |
|
1716 * don't generate false No Link messages. So we will wait here |
|
1717 * only if the user has set wait_autoneg_complete to 1, which is |
|
1718 * the default. |
|
1719 */ |
|
1720 if (hw->wait_autoneg_complete) { |
|
1721 /* We will wait for autoneg to complete. */ |
|
1722 e_dbg("Waiting for forced speed/duplex link.\n"); |
|
1723 mii_status_reg = 0; |
|
1724 |
|
1725 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
|
1726 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
1727 /* Read the MII Status Register and wait for Auto-Neg Complete bit |
|
1728 * to be set. |
|
1729 */ |
|
1730 ret_val = |
|
1731 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
1732 if (ret_val) |
|
1733 return ret_val; |
|
1734 |
|
1735 ret_val = |
|
1736 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
1737 if (ret_val) |
|
1738 return ret_val; |
|
1739 |
|
1740 if (mii_status_reg & MII_SR_LINK_STATUS) |
|
1741 break; |
|
1742 msleep(100); |
|
1743 } |
|
1744 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { |
|
1745 /* We didn't get link. Reset the DSP and wait again for link. */ |
|
1746 ret_val = e1000_phy_reset_dsp(hw); |
|
1747 if (ret_val) { |
|
1748 e_dbg("Error Resetting PHY DSP\n"); |
|
1749 return ret_val; |
|
1750 } |
|
1751 } |
|
1752 /* This loop will early-out if the link condition has been met. */ |
|
1753 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
1754 if (mii_status_reg & MII_SR_LINK_STATUS) |
|
1755 break; |
|
1756 msleep(100); |
|
1757 /* Read the MII Status Register and wait for Auto-Neg Complete bit |
|
1758 * to be set. |
|
1759 */ |
|
1760 ret_val = |
|
1761 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
1762 if (ret_val) |
|
1763 return ret_val; |
|
1764 |
|
1765 ret_val = |
|
1766 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
1767 if (ret_val) |
|
1768 return ret_val; |
|
1769 } |
|
1770 } |
|
1771 |
|
1772 if (hw->phy_type == e1000_phy_m88) { |
|
1773 /* Because we reset the PHY above, we need to re-force TX_CLK in the |
|
1774 * Extended PHY Specific Control Register to 25MHz clock. This value |
|
1775 * defaults back to a 2.5MHz clock when the PHY is reset. |
|
1776 */ |
|
1777 ret_val = |
|
1778 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
|
1779 &phy_data); |
|
1780 if (ret_val) |
|
1781 return ret_val; |
|
1782 |
|
1783 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
1784 ret_val = |
|
1785 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
|
1786 phy_data); |
|
1787 if (ret_val) |
|
1788 return ret_val; |
|
1789 |
|
1790 /* In addition, because of the s/w reset above, we need to enable CRS on |
|
1791 * TX. This must be set for both full and half duplex operation. |
|
1792 */ |
|
1793 ret_val = |
|
1794 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1795 if (ret_val) |
|
1796 return ret_val; |
|
1797 |
|
1798 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
1799 ret_val = |
|
1800 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1801 if (ret_val) |
|
1802 return ret_val; |
|
1803 |
|
1804 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) |
|
1805 && (!hw->autoneg) |
|
1806 && (hw->forced_speed_duplex == e1000_10_full |
|
1807 || hw->forced_speed_duplex == e1000_10_half)) { |
|
1808 ret_val = e1000_polarity_reversal_workaround(hw); |
|
1809 if (ret_val) |
|
1810 return ret_val; |
|
1811 } |
|
1812 } |
|
1813 return E1000_SUCCESS; |
|
1814 } |
|
1815 |
|
1816 /** |
|
1817 * e1000_config_collision_dist - set collision distance register |
|
1818 * @hw: Struct containing variables accessed by shared code |
|
1819 * |
|
1820 * Sets the collision distance in the Transmit Control register. |
|
1821 * Link should have been established previously. Reads the speed and duplex |
|
1822 * information from the Device Status register. |
|
1823 */ |
|
1824 void e1000_config_collision_dist(struct e1000_hw *hw) |
|
1825 { |
|
1826 u32 tctl, coll_dist; |
|
1827 |
|
1828 e_dbg("e1000_config_collision_dist"); |
|
1829 |
|
1830 if (hw->mac_type < e1000_82543) |
|
1831 coll_dist = E1000_COLLISION_DISTANCE_82542; |
|
1832 else |
|
1833 coll_dist = E1000_COLLISION_DISTANCE; |
|
1834 |
|
1835 tctl = er32(TCTL); |
|
1836 |
|
1837 tctl &= ~E1000_TCTL_COLD; |
|
1838 tctl |= coll_dist << E1000_COLD_SHIFT; |
|
1839 |
|
1840 ew32(TCTL, tctl); |
|
1841 E1000_WRITE_FLUSH(); |
|
1842 } |
|
1843 |
|
1844 /** |
|
1845 * e1000_config_mac_to_phy - sync phy and mac settings |
|
1846 * @hw: Struct containing variables accessed by shared code |
|
1847 * @mii_reg: data to write to the MII control register |
|
1848 * |
|
1849 * Sets MAC speed and duplex settings to reflect the those in the PHY |
|
1850 * The contents of the PHY register containing the needed information need to |
|
1851 * be passed in. |
|
1852 */ |
|
1853 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) |
|
1854 { |
|
1855 u32 ctrl; |
|
1856 s32 ret_val; |
|
1857 u16 phy_data; |
|
1858 |
|
1859 e_dbg("e1000_config_mac_to_phy"); |
|
1860 |
|
1861 /* 82544 or newer MAC, Auto Speed Detection takes care of |
|
1862 * MAC speed/duplex configuration.*/ |
|
1863 if (hw->mac_type >= e1000_82544) |
|
1864 return E1000_SUCCESS; |
|
1865 |
|
1866 /* Read the Device Control Register and set the bits to Force Speed |
|
1867 * and Duplex. |
|
1868 */ |
|
1869 ctrl = er32(CTRL); |
|
1870 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1871 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); |
|
1872 |
|
1873 /* Set up duplex in the Device Control and Transmit Control |
|
1874 * registers depending on negotiated values. |
|
1875 */ |
|
1876 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
1877 if (ret_val) |
|
1878 return ret_val; |
|
1879 |
|
1880 if (phy_data & M88E1000_PSSR_DPLX) |
|
1881 ctrl |= E1000_CTRL_FD; |
|
1882 else |
|
1883 ctrl &= ~E1000_CTRL_FD; |
|
1884 |
|
1885 e1000_config_collision_dist(hw); |
|
1886 |
|
1887 /* Set up speed in the Device Control register depending on |
|
1888 * negotiated values. |
|
1889 */ |
|
1890 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
|
1891 ctrl |= E1000_CTRL_SPD_1000; |
|
1892 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) |
|
1893 ctrl |= E1000_CTRL_SPD_100; |
|
1894 |
|
1895 /* Write the configured values back to the Device Control Reg. */ |
|
1896 ew32(CTRL, ctrl); |
|
1897 return E1000_SUCCESS; |
|
1898 } |
|
1899 |
|
1900 /** |
|
1901 * e1000_force_mac_fc - force flow control settings |
|
1902 * @hw: Struct containing variables accessed by shared code |
|
1903 * |
|
1904 * Forces the MAC's flow control settings. |
|
1905 * Sets the TFCE and RFCE bits in the device control register to reflect |
|
1906 * the adapter settings. TFCE and RFCE need to be explicitly set by |
|
1907 * software when a Copper PHY is used because autonegotiation is managed |
|
1908 * by the PHY rather than the MAC. Software must also configure these |
|
1909 * bits when link is forced on a fiber connection. |
|
1910 */ |
|
1911 s32 e1000_force_mac_fc(struct e1000_hw *hw) |
|
1912 { |
|
1913 u32 ctrl; |
|
1914 |
|
1915 e_dbg("e1000_force_mac_fc"); |
|
1916 |
|
1917 /* Get the current configuration of the Device Control Register */ |
|
1918 ctrl = er32(CTRL); |
|
1919 |
|
1920 /* Because we didn't get link via the internal auto-negotiation |
|
1921 * mechanism (we either forced link or we got link via PHY |
|
1922 * auto-neg), we have to manually enable/disable transmit an |
|
1923 * receive flow control. |
|
1924 * |
|
1925 * The "Case" statement below enables/disable flow control |
|
1926 * according to the "hw->fc" parameter. |
|
1927 * |
|
1928 * The possible values of the "fc" parameter are: |
|
1929 * 0: Flow control is completely disabled |
|
1930 * 1: Rx flow control is enabled (we can receive pause |
|
1931 * frames but not send pause frames). |
|
1932 * 2: Tx flow control is enabled (we can send pause frames |
|
1933 * frames but we do not receive pause frames). |
|
1934 * 3: Both Rx and TX flow control (symmetric) is enabled. |
|
1935 * other: No other values should be possible at this point. |
|
1936 */ |
|
1937 |
|
1938 switch (hw->fc) { |
|
1939 case E1000_FC_NONE: |
|
1940 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
|
1941 break; |
|
1942 case E1000_FC_RX_PAUSE: |
|
1943 ctrl &= (~E1000_CTRL_TFCE); |
|
1944 ctrl |= E1000_CTRL_RFCE; |
|
1945 break; |
|
1946 case E1000_FC_TX_PAUSE: |
|
1947 ctrl &= (~E1000_CTRL_RFCE); |
|
1948 ctrl |= E1000_CTRL_TFCE; |
|
1949 break; |
|
1950 case E1000_FC_FULL: |
|
1951 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
|
1952 break; |
|
1953 default: |
|
1954 e_dbg("Flow control param set incorrectly\n"); |
|
1955 return -E1000_ERR_CONFIG; |
|
1956 } |
|
1957 |
|
1958 /* Disable TX Flow Control for 82542 (rev 2.0) */ |
|
1959 if (hw->mac_type == e1000_82542_rev2_0) |
|
1960 ctrl &= (~E1000_CTRL_TFCE); |
|
1961 |
|
1962 ew32(CTRL, ctrl); |
|
1963 return E1000_SUCCESS; |
|
1964 } |
|
1965 |
|
1966 /** |
|
1967 * e1000_config_fc_after_link_up - configure flow control after autoneg |
|
1968 * @hw: Struct containing variables accessed by shared code |
|
1969 * |
|
1970 * Configures flow control settings after link is established |
|
1971 * Should be called immediately after a valid link has been established. |
|
1972 * Forces MAC flow control settings if link was forced. When in MII/GMII mode |
|
1973 * and autonegotiation is enabled, the MAC flow control settings will be set |
|
1974 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE |
|
1975 * and RFCE bits will be automatically set to the negotiated flow control mode. |
|
1976 */ |
|
1977 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) |
|
1978 { |
|
1979 s32 ret_val; |
|
1980 u16 mii_status_reg; |
|
1981 u16 mii_nway_adv_reg; |
|
1982 u16 mii_nway_lp_ability_reg; |
|
1983 u16 speed; |
|
1984 u16 duplex; |
|
1985 |
|
1986 e_dbg("e1000_config_fc_after_link_up"); |
|
1987 |
|
1988 /* Check for the case where we have fiber media and auto-neg failed |
|
1989 * so we had to force link. In this case, we need to force the |
|
1990 * configuration of the MAC to match the "fc" parameter. |
|
1991 */ |
|
1992 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) |
|
1993 || ((hw->media_type == e1000_media_type_internal_serdes) |
|
1994 && (hw->autoneg_failed)) |
|
1995 || ((hw->media_type == e1000_media_type_copper) |
|
1996 && (!hw->autoneg))) { |
|
1997 ret_val = e1000_force_mac_fc(hw); |
|
1998 if (ret_val) { |
|
1999 e_dbg("Error forcing flow control settings\n"); |
|
2000 return ret_val; |
|
2001 } |
|
2002 } |
|
2003 |
|
2004 /* Check for the case where we have copper media and auto-neg is |
|
2005 * enabled. In this case, we need to check and see if Auto-Neg |
|
2006 * has completed, and if so, how the PHY and link partner has |
|
2007 * flow control configured. |
|
2008 */ |
|
2009 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { |
|
2010 /* Read the MII Status Register and check to see if AutoNeg |
|
2011 * has completed. We read this twice because this reg has |
|
2012 * some "sticky" (latched) bits. |
|
2013 */ |
|
2014 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2015 if (ret_val) |
|
2016 return ret_val; |
|
2017 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2018 if (ret_val) |
|
2019 return ret_val; |
|
2020 |
|
2021 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
|
2022 /* The AutoNeg process has completed, so we now need to |
|
2023 * read both the Auto Negotiation Advertisement Register |
|
2024 * (Address 4) and the Auto_Negotiation Base Page Ability |
|
2025 * Register (Address 5) to determine how flow control was |
|
2026 * negotiated. |
|
2027 */ |
|
2028 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, |
|
2029 &mii_nway_adv_reg); |
|
2030 if (ret_val) |
|
2031 return ret_val; |
|
2032 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, |
|
2033 &mii_nway_lp_ability_reg); |
|
2034 if (ret_val) |
|
2035 return ret_val; |
|
2036 |
|
2037 /* Two bits in the Auto Negotiation Advertisement Register |
|
2038 * (Address 4) and two bits in the Auto Negotiation Base |
|
2039 * Page Ability Register (Address 5) determine flow control |
|
2040 * for both the PHY and the link partner. The following |
|
2041 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
|
2042 * 1999, describes these PAUSE resolution bits and how flow |
|
2043 * control is determined based upon these settings. |
|
2044 * NOTE: DC = Don't Care |
|
2045 * |
|
2046 * LOCAL DEVICE | LINK PARTNER |
|
2047 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
|
2048 *-------|---------|-------|---------|-------------------- |
|
2049 * 0 | 0 | DC | DC | E1000_FC_NONE |
|
2050 * 0 | 1 | 0 | DC | E1000_FC_NONE |
|
2051 * 0 | 1 | 1 | 0 | E1000_FC_NONE |
|
2052 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
|
2053 * 1 | 0 | 0 | DC | E1000_FC_NONE |
|
2054 * 1 | DC | 1 | DC | E1000_FC_FULL |
|
2055 * 1 | 1 | 0 | 0 | E1000_FC_NONE |
|
2056 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
|
2057 * |
|
2058 */ |
|
2059 /* Are both PAUSE bits set to 1? If so, this implies |
|
2060 * Symmetric Flow Control is enabled at both ends. The |
|
2061 * ASM_DIR bits are irrelevant per the spec. |
|
2062 * |
|
2063 * For Symmetric Flow Control: |
|
2064 * |
|
2065 * LOCAL DEVICE | LINK PARTNER |
|
2066 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2067 *-------|---------|-------|---------|-------------------- |
|
2068 * 1 | DC | 1 | DC | E1000_FC_FULL |
|
2069 * |
|
2070 */ |
|
2071 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2072 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
|
2073 /* Now we need to check if the user selected RX ONLY |
|
2074 * of pause frames. In this case, we had to advertise |
|
2075 * FULL flow control because we could not advertise RX |
|
2076 * ONLY. Hence, we must now check to see if we need to |
|
2077 * turn OFF the TRANSMISSION of PAUSE frames. |
|
2078 */ |
|
2079 if (hw->original_fc == E1000_FC_FULL) { |
|
2080 hw->fc = E1000_FC_FULL; |
|
2081 e_dbg("Flow Control = FULL.\n"); |
|
2082 } else { |
|
2083 hw->fc = E1000_FC_RX_PAUSE; |
|
2084 e_dbg |
|
2085 ("Flow Control = RX PAUSE frames only.\n"); |
|
2086 } |
|
2087 } |
|
2088 /* For receiving PAUSE frames ONLY. |
|
2089 * |
|
2090 * LOCAL DEVICE | LINK PARTNER |
|
2091 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2092 *-------|---------|-------|---------|-------------------- |
|
2093 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
|
2094 * |
|
2095 */ |
|
2096 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2097 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
2098 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
2099 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) |
|
2100 { |
|
2101 hw->fc = E1000_FC_TX_PAUSE; |
|
2102 e_dbg |
|
2103 ("Flow Control = TX PAUSE frames only.\n"); |
|
2104 } |
|
2105 /* For transmitting PAUSE frames ONLY. |
|
2106 * |
|
2107 * LOCAL DEVICE | LINK PARTNER |
|
2108 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2109 *-------|---------|-------|---------|-------------------- |
|
2110 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
|
2111 * |
|
2112 */ |
|
2113 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2114 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
2115 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
2116 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) |
|
2117 { |
|
2118 hw->fc = E1000_FC_RX_PAUSE; |
|
2119 e_dbg |
|
2120 ("Flow Control = RX PAUSE frames only.\n"); |
|
2121 } |
|
2122 /* Per the IEEE spec, at this point flow control should be |
|
2123 * disabled. However, we want to consider that we could |
|
2124 * be connected to a legacy switch that doesn't advertise |
|
2125 * desired flow control, but can be forced on the link |
|
2126 * partner. So if we advertised no flow control, that is |
|
2127 * what we will resolve to. If we advertised some kind of |
|
2128 * receive capability (Rx Pause Only or Full Flow Control) |
|
2129 * and the link partner advertised none, we will configure |
|
2130 * ourselves to enable Rx Flow Control only. We can do |
|
2131 * this safely for two reasons: If the link partner really |
|
2132 * didn't want flow control enabled, and we enable Rx, no |
|
2133 * harm done since we won't be receiving any PAUSE frames |
|
2134 * anyway. If the intent on the link partner was to have |
|
2135 * flow control enabled, then by us enabling RX only, we |
|
2136 * can at least receive pause frames and process them. |
|
2137 * This is a good idea because in most cases, since we are |
|
2138 * predominantly a server NIC, more times than not we will |
|
2139 * be asked to delay transmission of packets than asking |
|
2140 * our link partner to pause transmission of frames. |
|
2141 */ |
|
2142 else if ((hw->original_fc == E1000_FC_NONE || |
|
2143 hw->original_fc == E1000_FC_TX_PAUSE) || |
|
2144 hw->fc_strict_ieee) { |
|
2145 hw->fc = E1000_FC_NONE; |
|
2146 e_dbg("Flow Control = NONE.\n"); |
|
2147 } else { |
|
2148 hw->fc = E1000_FC_RX_PAUSE; |
|
2149 e_dbg |
|
2150 ("Flow Control = RX PAUSE frames only.\n"); |
|
2151 } |
|
2152 |
|
2153 /* Now we need to do one last check... If we auto- |
|
2154 * negotiated to HALF DUPLEX, flow control should not be |
|
2155 * enabled per IEEE 802.3 spec. |
|
2156 */ |
|
2157 ret_val = |
|
2158 e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
2159 if (ret_val) { |
|
2160 e_dbg |
|
2161 ("Error getting link speed and duplex\n"); |
|
2162 return ret_val; |
|
2163 } |
|
2164 |
|
2165 if (duplex == HALF_DUPLEX) |
|
2166 hw->fc = E1000_FC_NONE; |
|
2167 |
|
2168 /* Now we call a subroutine to actually force the MAC |
|
2169 * controller to use the correct flow control settings. |
|
2170 */ |
|
2171 ret_val = e1000_force_mac_fc(hw); |
|
2172 if (ret_val) { |
|
2173 e_dbg |
|
2174 ("Error forcing flow control settings\n"); |
|
2175 return ret_val; |
|
2176 } |
|
2177 } else { |
|
2178 e_dbg |
|
2179 ("Copper PHY and Auto Neg has not completed.\n"); |
|
2180 } |
|
2181 } |
|
2182 return E1000_SUCCESS; |
|
2183 } |
|
2184 |
|
2185 /** |
|
2186 * e1000_check_for_serdes_link_generic - Check for link (Serdes) |
|
2187 * @hw: pointer to the HW structure |
|
2188 * |
|
2189 * Checks for link up on the hardware. If link is not up and we have |
|
2190 * a signal, then we need to force link up. |
|
2191 */ |
|
2192 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) |
|
2193 { |
|
2194 u32 rxcw; |
|
2195 u32 ctrl; |
|
2196 u32 status; |
|
2197 s32 ret_val = E1000_SUCCESS; |
|
2198 |
|
2199 e_dbg("e1000_check_for_serdes_link_generic"); |
|
2200 |
|
2201 ctrl = er32(CTRL); |
|
2202 status = er32(STATUS); |
|
2203 rxcw = er32(RXCW); |
|
2204 |
|
2205 /* |
|
2206 * If we don't have link (auto-negotiation failed or link partner |
|
2207 * cannot auto-negotiate), and our link partner is not trying to |
|
2208 * auto-negotiate with us (we are receiving idles or data), |
|
2209 * we need to force link up. We also need to give auto-negotiation |
|
2210 * time to complete. |
|
2211 */ |
|
2212 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ |
|
2213 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { |
|
2214 if (hw->autoneg_failed == 0) { |
|
2215 hw->autoneg_failed = 1; |
|
2216 goto out; |
|
2217 } |
|
2218 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); |
|
2219 |
|
2220 /* Disable auto-negotiation in the TXCW register */ |
|
2221 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); |
|
2222 |
|
2223 /* Force link-up and also force full-duplex. */ |
|
2224 ctrl = er32(CTRL); |
|
2225 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
|
2226 ew32(CTRL, ctrl); |
|
2227 |
|
2228 /* Configure Flow Control after forcing link up. */ |
|
2229 ret_val = e1000_config_fc_after_link_up(hw); |
|
2230 if (ret_val) { |
|
2231 e_dbg("Error configuring flow control\n"); |
|
2232 goto out; |
|
2233 } |
|
2234 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
|
2235 /* |
|
2236 * If we are forcing link and we are receiving /C/ ordered |
|
2237 * sets, re-enable auto-negotiation in the TXCW register |
|
2238 * and disable forced link in the Device Control register |
|
2239 * in an attempt to auto-negotiate with our link partner. |
|
2240 */ |
|
2241 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
|
2242 ew32(TXCW, hw->txcw); |
|
2243 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
2244 |
|
2245 hw->serdes_has_link = true; |
|
2246 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { |
|
2247 /* |
|
2248 * If we force link for non-auto-negotiation switch, check |
|
2249 * link status based on MAC synchronization for internal |
|
2250 * serdes media type. |
|
2251 */ |
|
2252 /* SYNCH bit and IV bit are sticky. */ |
|
2253 udelay(10); |
|
2254 rxcw = er32(RXCW); |
|
2255 if (rxcw & E1000_RXCW_SYNCH) { |
|
2256 if (!(rxcw & E1000_RXCW_IV)) { |
|
2257 hw->serdes_has_link = true; |
|
2258 e_dbg("SERDES: Link up - forced.\n"); |
|
2259 } |
|
2260 } else { |
|
2261 hw->serdes_has_link = false; |
|
2262 e_dbg("SERDES: Link down - force failed.\n"); |
|
2263 } |
|
2264 } |
|
2265 |
|
2266 if (E1000_TXCW_ANE & er32(TXCW)) { |
|
2267 status = er32(STATUS); |
|
2268 if (status & E1000_STATUS_LU) { |
|
2269 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ |
|
2270 udelay(10); |
|
2271 rxcw = er32(RXCW); |
|
2272 if (rxcw & E1000_RXCW_SYNCH) { |
|
2273 if (!(rxcw & E1000_RXCW_IV)) { |
|
2274 hw->serdes_has_link = true; |
|
2275 e_dbg("SERDES: Link up - autoneg " |
|
2276 "completed successfully.\n"); |
|
2277 } else { |
|
2278 hw->serdes_has_link = false; |
|
2279 e_dbg("SERDES: Link down - invalid" |
|
2280 "codewords detected in autoneg.\n"); |
|
2281 } |
|
2282 } else { |
|
2283 hw->serdes_has_link = false; |
|
2284 e_dbg("SERDES: Link down - no sync.\n"); |
|
2285 } |
|
2286 } else { |
|
2287 hw->serdes_has_link = false; |
|
2288 e_dbg("SERDES: Link down - autoneg failed\n"); |
|
2289 } |
|
2290 } |
|
2291 |
|
2292 out: |
|
2293 return ret_val; |
|
2294 } |
|
2295 |
|
2296 /** |
|
2297 * e1000_check_for_link |
|
2298 * @hw: Struct containing variables accessed by shared code |
|
2299 * |
|
2300 * Checks to see if the link status of the hardware has changed. |
|
2301 * Called by any function that needs to check the link status of the adapter. |
|
2302 */ |
|
2303 s32 e1000_check_for_link(struct e1000_hw *hw) |
|
2304 { |
|
2305 u32 rxcw = 0; |
|
2306 u32 ctrl; |
|
2307 u32 status; |
|
2308 u32 rctl; |
|
2309 u32 icr; |
|
2310 u32 signal = 0; |
|
2311 s32 ret_val; |
|
2312 u16 phy_data; |
|
2313 |
|
2314 e_dbg("e1000_check_for_link"); |
|
2315 |
|
2316 ctrl = er32(CTRL); |
|
2317 status = er32(STATUS); |
|
2318 |
|
2319 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be |
|
2320 * set when the optics detect a signal. On older adapters, it will be |
|
2321 * cleared when there is a signal. This applies to fiber media only. |
|
2322 */ |
|
2323 if ((hw->media_type == e1000_media_type_fiber) || |
|
2324 (hw->media_type == e1000_media_type_internal_serdes)) { |
|
2325 rxcw = er32(RXCW); |
|
2326 |
|
2327 if (hw->media_type == e1000_media_type_fiber) { |
|
2328 signal = |
|
2329 (hw->mac_type > |
|
2330 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
|
2331 if (status & E1000_STATUS_LU) |
|
2332 hw->get_link_status = false; |
|
2333 } |
|
2334 } |
|
2335 |
|
2336 /* If we have a copper PHY then we only want to go out to the PHY |
|
2337 * registers to see if Auto-Neg has completed and/or if our link |
|
2338 * status has changed. The get_link_status flag will be set if we |
|
2339 * receive a Link Status Change interrupt or we have Rx Sequence |
|
2340 * Errors. |
|
2341 */ |
|
2342 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { |
|
2343 /* First we want to see if the MII Status Register reports |
|
2344 * link. If so, then we want to get the current speed/duplex |
|
2345 * of the PHY. |
|
2346 * Read the register twice since the link bit is sticky. |
|
2347 */ |
|
2348 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2349 if (ret_val) |
|
2350 return ret_val; |
|
2351 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2352 if (ret_val) |
|
2353 return ret_val; |
|
2354 |
|
2355 if (phy_data & MII_SR_LINK_STATUS) { |
|
2356 hw->get_link_status = false; |
|
2357 /* Check if there was DownShift, must be checked immediately after |
|
2358 * link-up */ |
|
2359 e1000_check_downshift(hw); |
|
2360 |
|
2361 /* If we are on 82544 or 82543 silicon and speed/duplex |
|
2362 * are forced to 10H or 10F, then we will implement the polarity |
|
2363 * reversal workaround. We disable interrupts first, and upon |
|
2364 * returning, place the devices interrupt state to its previous |
|
2365 * value except for the link status change interrupt which will |
|
2366 * happen due to the execution of this workaround. |
|
2367 */ |
|
2368 |
|
2369 if ((hw->mac_type == e1000_82544 |
|
2370 || hw->mac_type == e1000_82543) && (!hw->autoneg) |
|
2371 && (hw->forced_speed_duplex == e1000_10_full |
|
2372 || hw->forced_speed_duplex == e1000_10_half)) { |
|
2373 ew32(IMC, 0xffffffff); |
|
2374 ret_val = |
|
2375 e1000_polarity_reversal_workaround(hw); |
|
2376 icr = er32(ICR); |
|
2377 ew32(ICS, (icr & ~E1000_ICS_LSC)); |
|
2378 ew32(IMS, IMS_ENABLE_MASK); |
|
2379 } |
|
2380 |
|
2381 } else { |
|
2382 /* No link detected */ |
|
2383 e1000_config_dsp_after_link_change(hw, false); |
|
2384 return 0; |
|
2385 } |
|
2386 |
|
2387 /* If we are forcing speed/duplex, then we simply return since |
|
2388 * we have already determined whether we have link or not. |
|
2389 */ |
|
2390 if (!hw->autoneg) |
|
2391 return -E1000_ERR_CONFIG; |
|
2392 |
|
2393 /* optimize the dsp settings for the igp phy */ |
|
2394 e1000_config_dsp_after_link_change(hw, true); |
|
2395 |
|
2396 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we |
|
2397 * have Si on board that is 82544 or newer, Auto |
|
2398 * Speed Detection takes care of MAC speed/duplex |
|
2399 * configuration. So we only need to configure Collision |
|
2400 * Distance in the MAC. Otherwise, we need to force |
|
2401 * speed/duplex on the MAC to the current PHY speed/duplex |
|
2402 * settings. |
|
2403 */ |
|
2404 if (hw->mac_type >= e1000_82544) |
|
2405 e1000_config_collision_dist(hw); |
|
2406 else { |
|
2407 ret_val = e1000_config_mac_to_phy(hw); |
|
2408 if (ret_val) { |
|
2409 e_dbg |
|
2410 ("Error configuring MAC to PHY settings\n"); |
|
2411 return ret_val; |
|
2412 } |
|
2413 } |
|
2414 |
|
2415 /* Configure Flow Control now that Auto-Neg has completed. First, we |
|
2416 * need to restore the desired flow control settings because we may |
|
2417 * have had to re-autoneg with a different link partner. |
|
2418 */ |
|
2419 ret_val = e1000_config_fc_after_link_up(hw); |
|
2420 if (ret_val) { |
|
2421 e_dbg("Error configuring flow control\n"); |
|
2422 return ret_val; |
|
2423 } |
|
2424 |
|
2425 /* At this point we know that we are on copper and we have |
|
2426 * auto-negotiated link. These are conditions for checking the link |
|
2427 * partner capability register. We use the link speed to determine if |
|
2428 * TBI compatibility needs to be turned on or off. If the link is not |
|
2429 * at gigabit speed, then TBI compatibility is not needed. If we are |
|
2430 * at gigabit speed, we turn on TBI compatibility. |
|
2431 */ |
|
2432 if (hw->tbi_compatibility_en) { |
|
2433 u16 speed, duplex; |
|
2434 ret_val = |
|
2435 e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
2436 if (ret_val) { |
|
2437 e_dbg |
|
2438 ("Error getting link speed and duplex\n"); |
|
2439 return ret_val; |
|
2440 } |
|
2441 if (speed != SPEED_1000) { |
|
2442 /* If link speed is not set to gigabit speed, we do not need |
|
2443 * to enable TBI compatibility. |
|
2444 */ |
|
2445 if (hw->tbi_compatibility_on) { |
|
2446 /* If we previously were in the mode, turn it off. */ |
|
2447 rctl = er32(RCTL); |
|
2448 rctl &= ~E1000_RCTL_SBP; |
|
2449 ew32(RCTL, rctl); |
|
2450 hw->tbi_compatibility_on = false; |
|
2451 } |
|
2452 } else { |
|
2453 /* If TBI compatibility is was previously off, turn it on. For |
|
2454 * compatibility with a TBI link partner, we will store bad |
|
2455 * packets. Some frames have an additional byte on the end and |
|
2456 * will look like CRC errors to to the hardware. |
|
2457 */ |
|
2458 if (!hw->tbi_compatibility_on) { |
|
2459 hw->tbi_compatibility_on = true; |
|
2460 rctl = er32(RCTL); |
|
2461 rctl |= E1000_RCTL_SBP; |
|
2462 ew32(RCTL, rctl); |
|
2463 } |
|
2464 } |
|
2465 } |
|
2466 } |
|
2467 |
|
2468 if ((hw->media_type == e1000_media_type_fiber) || |
|
2469 (hw->media_type == e1000_media_type_internal_serdes)) |
|
2470 e1000_check_for_serdes_link_generic(hw); |
|
2471 |
|
2472 return E1000_SUCCESS; |
|
2473 } |
|
2474 |
|
2475 /** |
|
2476 * e1000_get_speed_and_duplex |
|
2477 * @hw: Struct containing variables accessed by shared code |
|
2478 * @speed: Speed of the connection |
|
2479 * @duplex: Duplex setting of the connection |
|
2480 |
|
2481 * Detects the current speed and duplex settings of the hardware. |
|
2482 */ |
|
2483 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) |
|
2484 { |
|
2485 u32 status; |
|
2486 s32 ret_val; |
|
2487 u16 phy_data; |
|
2488 |
|
2489 e_dbg("e1000_get_speed_and_duplex"); |
|
2490 |
|
2491 if (hw->mac_type >= e1000_82543) { |
|
2492 status = er32(STATUS); |
|
2493 if (status & E1000_STATUS_SPEED_1000) { |
|
2494 *speed = SPEED_1000; |
|
2495 e_dbg("1000 Mbs, "); |
|
2496 } else if (status & E1000_STATUS_SPEED_100) { |
|
2497 *speed = SPEED_100; |
|
2498 e_dbg("100 Mbs, "); |
|
2499 } else { |
|
2500 *speed = SPEED_10; |
|
2501 e_dbg("10 Mbs, "); |
|
2502 } |
|
2503 |
|
2504 if (status & E1000_STATUS_FD) { |
|
2505 *duplex = FULL_DUPLEX; |
|
2506 e_dbg("Full Duplex\n"); |
|
2507 } else { |
|
2508 *duplex = HALF_DUPLEX; |
|
2509 e_dbg(" Half Duplex\n"); |
|
2510 } |
|
2511 } else { |
|
2512 e_dbg("1000 Mbs, Full Duplex\n"); |
|
2513 *speed = SPEED_1000; |
|
2514 *duplex = FULL_DUPLEX; |
|
2515 } |
|
2516 |
|
2517 /* IGP01 PHY may advertise full duplex operation after speed downgrade even |
|
2518 * if it is operating at half duplex. Here we set the duplex settings to |
|
2519 * match the duplex in the link partner's capabilities. |
|
2520 */ |
|
2521 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { |
|
2522 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
|
2523 if (ret_val) |
|
2524 return ret_val; |
|
2525 |
|
2526 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
|
2527 *duplex = HALF_DUPLEX; |
|
2528 else { |
|
2529 ret_val = |
|
2530 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); |
|
2531 if (ret_val) |
|
2532 return ret_val; |
|
2533 if ((*speed == SPEED_100 |
|
2534 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) |
|
2535 || (*speed == SPEED_10 |
|
2536 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
|
2537 *duplex = HALF_DUPLEX; |
|
2538 } |
|
2539 } |
|
2540 |
|
2541 return E1000_SUCCESS; |
|
2542 } |
|
2543 |
|
2544 /** |
|
2545 * e1000_wait_autoneg |
|
2546 * @hw: Struct containing variables accessed by shared code |
|
2547 * |
|
2548 * Blocks until autoneg completes or times out (~4.5 seconds) |
|
2549 */ |
|
2550 static s32 e1000_wait_autoneg(struct e1000_hw *hw) |
|
2551 { |
|
2552 s32 ret_val; |
|
2553 u16 i; |
|
2554 u16 phy_data; |
|
2555 |
|
2556 e_dbg("e1000_wait_autoneg"); |
|
2557 e_dbg("Waiting for Auto-Neg to complete.\n"); |
|
2558 |
|
2559 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
|
2560 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
|
2561 /* Read the MII Status Register and wait for Auto-Neg |
|
2562 * Complete bit to be set. |
|
2563 */ |
|
2564 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2565 if (ret_val) |
|
2566 return ret_val; |
|
2567 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2568 if (ret_val) |
|
2569 return ret_val; |
|
2570 if (phy_data & MII_SR_AUTONEG_COMPLETE) { |
|
2571 return E1000_SUCCESS; |
|
2572 } |
|
2573 msleep(100); |
|
2574 } |
|
2575 return E1000_SUCCESS; |
|
2576 } |
|
2577 |
|
2578 /** |
|
2579 * e1000_raise_mdi_clk - Raises the Management Data Clock |
|
2580 * @hw: Struct containing variables accessed by shared code |
|
2581 * @ctrl: Device control register's current value |
|
2582 */ |
|
2583 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) |
|
2584 { |
|
2585 /* Raise the clock input to the Management Data Clock (by setting the MDC |
|
2586 * bit), and then delay 10 microseconds. |
|
2587 */ |
|
2588 ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); |
|
2589 E1000_WRITE_FLUSH(); |
|
2590 udelay(10); |
|
2591 } |
|
2592 |
|
2593 /** |
|
2594 * e1000_lower_mdi_clk - Lowers the Management Data Clock |
|
2595 * @hw: Struct containing variables accessed by shared code |
|
2596 * @ctrl: Device control register's current value |
|
2597 */ |
|
2598 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) |
|
2599 { |
|
2600 /* Lower the clock input to the Management Data Clock (by clearing the MDC |
|
2601 * bit), and then delay 10 microseconds. |
|
2602 */ |
|
2603 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); |
|
2604 E1000_WRITE_FLUSH(); |
|
2605 udelay(10); |
|
2606 } |
|
2607 |
|
2608 /** |
|
2609 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY |
|
2610 * @hw: Struct containing variables accessed by shared code |
|
2611 * @data: Data to send out to the PHY |
|
2612 * @count: Number of bits to shift out |
|
2613 * |
|
2614 * Bits are shifted out in MSB to LSB order. |
|
2615 */ |
|
2616 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) |
|
2617 { |
|
2618 u32 ctrl; |
|
2619 u32 mask; |
|
2620 |
|
2621 /* We need to shift "count" number of bits out to the PHY. So, the value |
|
2622 * in the "data" parameter will be shifted out to the PHY one bit at a |
|
2623 * time. In order to do this, "data" must be broken down into bits. |
|
2624 */ |
|
2625 mask = 0x01; |
|
2626 mask <<= (count - 1); |
|
2627 |
|
2628 ctrl = er32(CTRL); |
|
2629 |
|
2630 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ |
|
2631 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); |
|
2632 |
|
2633 while (mask) { |
|
2634 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and |
|
2635 * then raising and lowering the Management Data Clock. A "0" is |
|
2636 * shifted out to the PHY by setting the MDIO bit to "0" and then |
|
2637 * raising and lowering the clock. |
|
2638 */ |
|
2639 if (data & mask) |
|
2640 ctrl |= E1000_CTRL_MDIO; |
|
2641 else |
|
2642 ctrl &= ~E1000_CTRL_MDIO; |
|
2643 |
|
2644 ew32(CTRL, ctrl); |
|
2645 E1000_WRITE_FLUSH(); |
|
2646 |
|
2647 udelay(10); |
|
2648 |
|
2649 e1000_raise_mdi_clk(hw, &ctrl); |
|
2650 e1000_lower_mdi_clk(hw, &ctrl); |
|
2651 |
|
2652 mask = mask >> 1; |
|
2653 } |
|
2654 } |
|
2655 |
|
2656 /** |
|
2657 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY |
|
2658 * @hw: Struct containing variables accessed by shared code |
|
2659 * |
|
2660 * Bits are shifted in in MSB to LSB order. |
|
2661 */ |
|
2662 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) |
|
2663 { |
|
2664 u32 ctrl; |
|
2665 u16 data = 0; |
|
2666 u8 i; |
|
2667 |
|
2668 /* In order to read a register from the PHY, we need to shift in a total |
|
2669 * of 18 bits from the PHY. The first two bit (turnaround) times are used |
|
2670 * to avoid contention on the MDIO pin when a read operation is performed. |
|
2671 * These two bits are ignored by us and thrown away. Bits are "shifted in" |
|
2672 * by raising the input to the Management Data Clock (setting the MDC bit), |
|
2673 * and then reading the value of the MDIO bit. |
|
2674 */ |
|
2675 ctrl = er32(CTRL); |
|
2676 |
|
2677 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ |
|
2678 ctrl &= ~E1000_CTRL_MDIO_DIR; |
|
2679 ctrl &= ~E1000_CTRL_MDIO; |
|
2680 |
|
2681 ew32(CTRL, ctrl); |
|
2682 E1000_WRITE_FLUSH(); |
|
2683 |
|
2684 /* Raise and Lower the clock before reading in the data. This accounts for |
|
2685 * the turnaround bits. The first clock occurred when we clocked out the |
|
2686 * last bit of the Register Address. |
|
2687 */ |
|
2688 e1000_raise_mdi_clk(hw, &ctrl); |
|
2689 e1000_lower_mdi_clk(hw, &ctrl); |
|
2690 |
|
2691 for (data = 0, i = 0; i < 16; i++) { |
|
2692 data = data << 1; |
|
2693 e1000_raise_mdi_clk(hw, &ctrl); |
|
2694 ctrl = er32(CTRL); |
|
2695 /* Check to see if we shifted in a "1". */ |
|
2696 if (ctrl & E1000_CTRL_MDIO) |
|
2697 data |= 1; |
|
2698 e1000_lower_mdi_clk(hw, &ctrl); |
|
2699 } |
|
2700 |
|
2701 e1000_raise_mdi_clk(hw, &ctrl); |
|
2702 e1000_lower_mdi_clk(hw, &ctrl); |
|
2703 |
|
2704 return data; |
|
2705 } |
|
2706 |
|
2707 |
|
2708 /** |
|
2709 * e1000_read_phy_reg - read a phy register |
|
2710 * @hw: Struct containing variables accessed by shared code |
|
2711 * @reg_addr: address of the PHY register to read |
|
2712 * |
|
2713 * Reads the value from a PHY register, if the value is on a specific non zero |
|
2714 * page, sets the page first. |
|
2715 */ |
|
2716 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) |
|
2717 { |
|
2718 u32 ret_val; |
|
2719 |
|
2720 e_dbg("e1000_read_phy_reg"); |
|
2721 |
|
2722 if ((hw->phy_type == e1000_phy_igp) && |
|
2723 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
|
2724 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
2725 (u16) reg_addr); |
|
2726 if (ret_val) |
|
2727 return ret_val; |
|
2728 } |
|
2729 |
|
2730 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
|
2731 phy_data); |
|
2732 |
|
2733 return ret_val; |
|
2734 } |
|
2735 |
|
2736 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
|
2737 u16 *phy_data) |
|
2738 { |
|
2739 u32 i; |
|
2740 u32 mdic = 0; |
|
2741 const u32 phy_addr = 1; |
|
2742 |
|
2743 e_dbg("e1000_read_phy_reg_ex"); |
|
2744 |
|
2745 if (reg_addr > MAX_PHY_REG_ADDRESS) { |
|
2746 e_dbg("PHY Address %d is out of range\n", reg_addr); |
|
2747 return -E1000_ERR_PARAM; |
|
2748 } |
|
2749 |
|
2750 if (hw->mac_type > e1000_82543) { |
|
2751 /* Set up Op-code, Phy Address, and register address in the MDI |
|
2752 * Control register. The MAC will take care of interfacing with the |
|
2753 * PHY to retrieve the desired data. |
|
2754 */ |
|
2755 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | |
|
2756 (phy_addr << E1000_MDIC_PHY_SHIFT) | |
|
2757 (E1000_MDIC_OP_READ)); |
|
2758 |
|
2759 ew32(MDIC, mdic); |
|
2760 |
|
2761 /* Poll the ready bit to see if the MDI read completed */ |
|
2762 for (i = 0; i < 64; i++) { |
|
2763 udelay(50); |
|
2764 mdic = er32(MDIC); |
|
2765 if (mdic & E1000_MDIC_READY) |
|
2766 break; |
|
2767 } |
|
2768 if (!(mdic & E1000_MDIC_READY)) { |
|
2769 e_dbg("MDI Read did not complete\n"); |
|
2770 return -E1000_ERR_PHY; |
|
2771 } |
|
2772 if (mdic & E1000_MDIC_ERROR) { |
|
2773 e_dbg("MDI Error\n"); |
|
2774 return -E1000_ERR_PHY; |
|
2775 } |
|
2776 *phy_data = (u16) mdic; |
|
2777 } else { |
|
2778 /* We must first send a preamble through the MDIO pin to signal the |
|
2779 * beginning of an MII instruction. This is done by sending 32 |
|
2780 * consecutive "1" bits. |
|
2781 */ |
|
2782 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
|
2783 |
|
2784 /* Now combine the next few fields that are required for a read |
|
2785 * operation. We use this method instead of calling the |
|
2786 * e1000_shift_out_mdi_bits routine five different times. The format of |
|
2787 * a MII read instruction consists of a shift out of 14 bits and is |
|
2788 * defined as follows: |
|
2789 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> |
|
2790 * followed by a shift in of 18 bits. This first two bits shifted in |
|
2791 * are TurnAround bits used to avoid contention on the MDIO pin when a |
|
2792 * READ operation is performed. These two bits are thrown away |
|
2793 * followed by a shift in of 16 bits which contains the desired data. |
|
2794 */ |
|
2795 mdic = ((reg_addr) | (phy_addr << 5) | |
|
2796 (PHY_OP_READ << 10) | (PHY_SOF << 12)); |
|
2797 |
|
2798 e1000_shift_out_mdi_bits(hw, mdic, 14); |
|
2799 |
|
2800 /* Now that we've shifted out the read command to the MII, we need to |
|
2801 * "shift in" the 16-bit value (18 total bits) of the requested PHY |
|
2802 * register address. |
|
2803 */ |
|
2804 *phy_data = e1000_shift_in_mdi_bits(hw); |
|
2805 } |
|
2806 return E1000_SUCCESS; |
|
2807 } |
|
2808 |
|
2809 /** |
|
2810 * e1000_write_phy_reg - write a phy register |
|
2811 * |
|
2812 * @hw: Struct containing variables accessed by shared code |
|
2813 * @reg_addr: address of the PHY register to write |
|
2814 * @data: data to write to the PHY |
|
2815 |
|
2816 * Writes a value to a PHY register |
|
2817 */ |
|
2818 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) |
|
2819 { |
|
2820 u32 ret_val; |
|
2821 |
|
2822 e_dbg("e1000_write_phy_reg"); |
|
2823 |
|
2824 if ((hw->phy_type == e1000_phy_igp) && |
|
2825 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
|
2826 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
2827 (u16) reg_addr); |
|
2828 if (ret_val) |
|
2829 return ret_val; |
|
2830 } |
|
2831 |
|
2832 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
|
2833 phy_data); |
|
2834 |
|
2835 return ret_val; |
|
2836 } |
|
2837 |
|
2838 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
|
2839 u16 phy_data) |
|
2840 { |
|
2841 u32 i; |
|
2842 u32 mdic = 0; |
|
2843 const u32 phy_addr = 1; |
|
2844 |
|
2845 e_dbg("e1000_write_phy_reg_ex"); |
|
2846 |
|
2847 if (reg_addr > MAX_PHY_REG_ADDRESS) { |
|
2848 e_dbg("PHY Address %d is out of range\n", reg_addr); |
|
2849 return -E1000_ERR_PARAM; |
|
2850 } |
|
2851 |
|
2852 if (hw->mac_type > e1000_82543) { |
|
2853 /* Set up Op-code, Phy Address, register address, and data intended |
|
2854 * for the PHY register in the MDI Control register. The MAC will take |
|
2855 * care of interfacing with the PHY to send the desired data. |
|
2856 */ |
|
2857 mdic = (((u32) phy_data) | |
|
2858 (reg_addr << E1000_MDIC_REG_SHIFT) | |
|
2859 (phy_addr << E1000_MDIC_PHY_SHIFT) | |
|
2860 (E1000_MDIC_OP_WRITE)); |
|
2861 |
|
2862 ew32(MDIC, mdic); |
|
2863 |
|
2864 /* Poll the ready bit to see if the MDI read completed */ |
|
2865 for (i = 0; i < 641; i++) { |
|
2866 udelay(5); |
|
2867 mdic = er32(MDIC); |
|
2868 if (mdic & E1000_MDIC_READY) |
|
2869 break; |
|
2870 } |
|
2871 if (!(mdic & E1000_MDIC_READY)) { |
|
2872 e_dbg("MDI Write did not complete\n"); |
|
2873 return -E1000_ERR_PHY; |
|
2874 } |
|
2875 } else { |
|
2876 /* We'll need to use the SW defined pins to shift the write command |
|
2877 * out to the PHY. We first send a preamble to the PHY to signal the |
|
2878 * beginning of the MII instruction. This is done by sending 32 |
|
2879 * consecutive "1" bits. |
|
2880 */ |
|
2881 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
|
2882 |
|
2883 /* Now combine the remaining required fields that will indicate a |
|
2884 * write operation. We use this method instead of calling the |
|
2885 * e1000_shift_out_mdi_bits routine for each field in the command. The |
|
2886 * format of a MII write instruction is as follows: |
|
2887 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. |
|
2888 */ |
|
2889 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | |
|
2890 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); |
|
2891 mdic <<= 16; |
|
2892 mdic |= (u32) phy_data; |
|
2893 |
|
2894 e1000_shift_out_mdi_bits(hw, mdic, 32); |
|
2895 } |
|
2896 |
|
2897 return E1000_SUCCESS; |
|
2898 } |
|
2899 |
|
2900 /** |
|
2901 * e1000_phy_hw_reset - reset the phy, hardware style |
|
2902 * @hw: Struct containing variables accessed by shared code |
|
2903 * |
|
2904 * Returns the PHY to the power-on reset state |
|
2905 */ |
|
2906 s32 e1000_phy_hw_reset(struct e1000_hw *hw) |
|
2907 { |
|
2908 u32 ctrl, ctrl_ext; |
|
2909 u32 led_ctrl; |
|
2910 s32 ret_val; |
|
2911 |
|
2912 e_dbg("e1000_phy_hw_reset"); |
|
2913 |
|
2914 e_dbg("Resetting Phy...\n"); |
|
2915 |
|
2916 if (hw->mac_type > e1000_82543) { |
|
2917 /* Read the device control register and assert the E1000_CTRL_PHY_RST |
|
2918 * bit. Then, take it out of reset. |
|
2919 * For e1000 hardware, we delay for 10ms between the assert |
|
2920 * and deassert. |
|
2921 */ |
|
2922 ctrl = er32(CTRL); |
|
2923 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); |
|
2924 E1000_WRITE_FLUSH(); |
|
2925 |
|
2926 msleep(10); |
|
2927 |
|
2928 ew32(CTRL, ctrl); |
|
2929 E1000_WRITE_FLUSH(); |
|
2930 |
|
2931 } else { |
|
2932 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR |
|
2933 * bit to put the PHY into reset. Then, take it out of reset. |
|
2934 */ |
|
2935 ctrl_ext = er32(CTRL_EXT); |
|
2936 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; |
|
2937 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; |
|
2938 ew32(CTRL_EXT, ctrl_ext); |
|
2939 E1000_WRITE_FLUSH(); |
|
2940 msleep(10); |
|
2941 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
|
2942 ew32(CTRL_EXT, ctrl_ext); |
|
2943 E1000_WRITE_FLUSH(); |
|
2944 } |
|
2945 udelay(150); |
|
2946 |
|
2947 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
2948 /* Configure activity LED after PHY reset */ |
|
2949 led_ctrl = er32(LEDCTL); |
|
2950 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
2951 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
2952 ew32(LEDCTL, led_ctrl); |
|
2953 } |
|
2954 |
|
2955 /* Wait for FW to finish PHY configuration. */ |
|
2956 ret_val = e1000_get_phy_cfg_done(hw); |
|
2957 if (ret_val != E1000_SUCCESS) |
|
2958 return ret_val; |
|
2959 |
|
2960 return ret_val; |
|
2961 } |
|
2962 |
|
2963 /** |
|
2964 * e1000_phy_reset - reset the phy to commit settings |
|
2965 * @hw: Struct containing variables accessed by shared code |
|
2966 * |
|
2967 * Resets the PHY |
|
2968 * Sets bit 15 of the MII Control register |
|
2969 */ |
|
2970 s32 e1000_phy_reset(struct e1000_hw *hw) |
|
2971 { |
|
2972 s32 ret_val; |
|
2973 u16 phy_data; |
|
2974 |
|
2975 e_dbg("e1000_phy_reset"); |
|
2976 |
|
2977 switch (hw->phy_type) { |
|
2978 case e1000_phy_igp: |
|
2979 ret_val = e1000_phy_hw_reset(hw); |
|
2980 if (ret_val) |
|
2981 return ret_val; |
|
2982 break; |
|
2983 default: |
|
2984 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
|
2985 if (ret_val) |
|
2986 return ret_val; |
|
2987 |
|
2988 phy_data |= MII_CR_RESET; |
|
2989 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
|
2990 if (ret_val) |
|
2991 return ret_val; |
|
2992 |
|
2993 udelay(1); |
|
2994 break; |
|
2995 } |
|
2996 |
|
2997 if (hw->phy_type == e1000_phy_igp) |
|
2998 e1000_phy_init_script(hw); |
|
2999 |
|
3000 return E1000_SUCCESS; |
|
3001 } |
|
3002 |
|
3003 /** |
|
3004 * e1000_detect_gig_phy - check the phy type |
|
3005 * @hw: Struct containing variables accessed by shared code |
|
3006 * |
|
3007 * Probes the expected PHY address for known PHY IDs |
|
3008 */ |
|
3009 static s32 e1000_detect_gig_phy(struct e1000_hw *hw) |
|
3010 { |
|
3011 s32 phy_init_status, ret_val; |
|
3012 u16 phy_id_high, phy_id_low; |
|
3013 bool match = false; |
|
3014 |
|
3015 e_dbg("e1000_detect_gig_phy"); |
|
3016 |
|
3017 if (hw->phy_id != 0) |
|
3018 return E1000_SUCCESS; |
|
3019 |
|
3020 /* Read the PHY ID Registers to identify which PHY is onboard. */ |
|
3021 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); |
|
3022 if (ret_val) |
|
3023 return ret_val; |
|
3024 |
|
3025 hw->phy_id = (u32) (phy_id_high << 16); |
|
3026 udelay(20); |
|
3027 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); |
|
3028 if (ret_val) |
|
3029 return ret_val; |
|
3030 |
|
3031 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); |
|
3032 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; |
|
3033 |
|
3034 switch (hw->mac_type) { |
|
3035 case e1000_82543: |
|
3036 if (hw->phy_id == M88E1000_E_PHY_ID) |
|
3037 match = true; |
|
3038 break; |
|
3039 case e1000_82544: |
|
3040 if (hw->phy_id == M88E1000_I_PHY_ID) |
|
3041 match = true; |
|
3042 break; |
|
3043 case e1000_82540: |
|
3044 case e1000_82545: |
|
3045 case e1000_82545_rev_3: |
|
3046 case e1000_82546: |
|
3047 case e1000_82546_rev_3: |
|
3048 if (hw->phy_id == M88E1011_I_PHY_ID) |
|
3049 match = true; |
|
3050 break; |
|
3051 case e1000_82541: |
|
3052 case e1000_82541_rev_2: |
|
3053 case e1000_82547: |
|
3054 case e1000_82547_rev_2: |
|
3055 if (hw->phy_id == IGP01E1000_I_PHY_ID) |
|
3056 match = true; |
|
3057 break; |
|
3058 default: |
|
3059 e_dbg("Invalid MAC type %d\n", hw->mac_type); |
|
3060 return -E1000_ERR_CONFIG; |
|
3061 } |
|
3062 phy_init_status = e1000_set_phy_type(hw); |
|
3063 |
|
3064 if ((match) && (phy_init_status == E1000_SUCCESS)) { |
|
3065 e_dbg("PHY ID 0x%X detected\n", hw->phy_id); |
|
3066 return E1000_SUCCESS; |
|
3067 } |
|
3068 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id); |
|
3069 return -E1000_ERR_PHY; |
|
3070 } |
|
3071 |
|
3072 /** |
|
3073 * e1000_phy_reset_dsp - reset DSP |
|
3074 * @hw: Struct containing variables accessed by shared code |
|
3075 * |
|
3076 * Resets the PHY's DSP |
|
3077 */ |
|
3078 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) |
|
3079 { |
|
3080 s32 ret_val; |
|
3081 e_dbg("e1000_phy_reset_dsp"); |
|
3082 |
|
3083 do { |
|
3084 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); |
|
3085 if (ret_val) |
|
3086 break; |
|
3087 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); |
|
3088 if (ret_val) |
|
3089 break; |
|
3090 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); |
|
3091 if (ret_val) |
|
3092 break; |
|
3093 ret_val = E1000_SUCCESS; |
|
3094 } while (0); |
|
3095 |
|
3096 return ret_val; |
|
3097 } |
|
3098 |
|
3099 /** |
|
3100 * e1000_phy_igp_get_info - get igp specific registers |
|
3101 * @hw: Struct containing variables accessed by shared code |
|
3102 * @phy_info: PHY information structure |
|
3103 * |
|
3104 * Get PHY information from various PHY registers for igp PHY only. |
|
3105 */ |
|
3106 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, |
|
3107 struct e1000_phy_info *phy_info) |
|
3108 { |
|
3109 s32 ret_val; |
|
3110 u16 phy_data, min_length, max_length, average; |
|
3111 e1000_rev_polarity polarity; |
|
3112 |
|
3113 e_dbg("e1000_phy_igp_get_info"); |
|
3114 |
|
3115 /* The downshift status is checked only once, after link is established, |
|
3116 * and it stored in the hw->speed_downgraded parameter. */ |
|
3117 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; |
|
3118 |
|
3119 /* IGP01E1000 does not need to support it. */ |
|
3120 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
|
3121 |
|
3122 /* IGP01E1000 always correct polarity reversal */ |
|
3123 phy_info->polarity_correction = e1000_polarity_reversal_enabled; |
|
3124 |
|
3125 /* Check polarity status */ |
|
3126 ret_val = e1000_check_polarity(hw, &polarity); |
|
3127 if (ret_val) |
|
3128 return ret_val; |
|
3129 |
|
3130 phy_info->cable_polarity = polarity; |
|
3131 |
|
3132 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); |
|
3133 if (ret_val) |
|
3134 return ret_val; |
|
3135 |
|
3136 phy_info->mdix_mode = |
|
3137 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> |
|
3138 IGP01E1000_PSSR_MDIX_SHIFT); |
|
3139 |
|
3140 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
|
3141 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
3142 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ |
|
3143 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
|
3144 if (ret_val) |
|
3145 return ret_val; |
|
3146 |
|
3147 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
|
3148 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? |
|
3149 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
3150 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
|
3151 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? |
|
3152 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
3153 |
|
3154 /* Get cable length */ |
|
3155 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
|
3156 if (ret_val) |
|
3157 return ret_val; |
|
3158 |
|
3159 /* Translate to old method */ |
|
3160 average = (max_length + min_length) / 2; |
|
3161 |
|
3162 if (average <= e1000_igp_cable_length_50) |
|
3163 phy_info->cable_length = e1000_cable_length_50; |
|
3164 else if (average <= e1000_igp_cable_length_80) |
|
3165 phy_info->cable_length = e1000_cable_length_50_80; |
|
3166 else if (average <= e1000_igp_cable_length_110) |
|
3167 phy_info->cable_length = e1000_cable_length_80_110; |
|
3168 else if (average <= e1000_igp_cable_length_140) |
|
3169 phy_info->cable_length = e1000_cable_length_110_140; |
|
3170 else |
|
3171 phy_info->cable_length = e1000_cable_length_140; |
|
3172 } |
|
3173 |
|
3174 return E1000_SUCCESS; |
|
3175 } |
|
3176 |
|
3177 /** |
|
3178 * e1000_phy_m88_get_info - get m88 specific registers |
|
3179 * @hw: Struct containing variables accessed by shared code |
|
3180 * @phy_info: PHY information structure |
|
3181 * |
|
3182 * Get PHY information from various PHY registers for m88 PHY only. |
|
3183 */ |
|
3184 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, |
|
3185 struct e1000_phy_info *phy_info) |
|
3186 { |
|
3187 s32 ret_val; |
|
3188 u16 phy_data; |
|
3189 e1000_rev_polarity polarity; |
|
3190 |
|
3191 e_dbg("e1000_phy_m88_get_info"); |
|
3192 |
|
3193 /* The downshift status is checked only once, after link is established, |
|
3194 * and it stored in the hw->speed_downgraded parameter. */ |
|
3195 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; |
|
3196 |
|
3197 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
3198 if (ret_val) |
|
3199 return ret_val; |
|
3200 |
|
3201 phy_info->extended_10bt_distance = |
|
3202 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> |
|
3203 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? |
|
3204 e1000_10bt_ext_dist_enable_lower : |
|
3205 e1000_10bt_ext_dist_enable_normal; |
|
3206 |
|
3207 phy_info->polarity_correction = |
|
3208 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> |
|
3209 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? |
|
3210 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; |
|
3211 |
|
3212 /* Check polarity status */ |
|
3213 ret_val = e1000_check_polarity(hw, &polarity); |
|
3214 if (ret_val) |
|
3215 return ret_val; |
|
3216 phy_info->cable_polarity = polarity; |
|
3217 |
|
3218 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
3219 if (ret_val) |
|
3220 return ret_val; |
|
3221 |
|
3222 phy_info->mdix_mode = |
|
3223 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> |
|
3224 M88E1000_PSSR_MDIX_SHIFT); |
|
3225 |
|
3226 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
|
3227 /* Cable Length Estimation and Local/Remote Receiver Information |
|
3228 * are only valid at 1000 Mbps. |
|
3229 */ |
|
3230 phy_info->cable_length = |
|
3231 (e1000_cable_length) ((phy_data & |
|
3232 M88E1000_PSSR_CABLE_LENGTH) >> |
|
3233 M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
|
3234 |
|
3235 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
|
3236 if (ret_val) |
|
3237 return ret_val; |
|
3238 |
|
3239 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
|
3240 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? |
|
3241 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
3242 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
|
3243 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? |
|
3244 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
3245 |
|
3246 } |
|
3247 |
|
3248 return E1000_SUCCESS; |
|
3249 } |
|
3250 |
|
3251 /** |
|
3252 * e1000_phy_get_info - request phy info |
|
3253 * @hw: Struct containing variables accessed by shared code |
|
3254 * @phy_info: PHY information structure |
|
3255 * |
|
3256 * Get PHY information from various PHY registers |
|
3257 */ |
|
3258 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) |
|
3259 { |
|
3260 s32 ret_val; |
|
3261 u16 phy_data; |
|
3262 |
|
3263 e_dbg("e1000_phy_get_info"); |
|
3264 |
|
3265 phy_info->cable_length = e1000_cable_length_undefined; |
|
3266 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; |
|
3267 phy_info->cable_polarity = e1000_rev_polarity_undefined; |
|
3268 phy_info->downshift = e1000_downshift_undefined; |
|
3269 phy_info->polarity_correction = e1000_polarity_reversal_undefined; |
|
3270 phy_info->mdix_mode = e1000_auto_x_mode_undefined; |
|
3271 phy_info->local_rx = e1000_1000t_rx_status_undefined; |
|
3272 phy_info->remote_rx = e1000_1000t_rx_status_undefined; |
|
3273 |
|
3274 if (hw->media_type != e1000_media_type_copper) { |
|
3275 e_dbg("PHY info is only valid for copper media\n"); |
|
3276 return -E1000_ERR_CONFIG; |
|
3277 } |
|
3278 |
|
3279 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
3280 if (ret_val) |
|
3281 return ret_val; |
|
3282 |
|
3283 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
3284 if (ret_val) |
|
3285 return ret_val; |
|
3286 |
|
3287 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { |
|
3288 e_dbg("PHY info is only valid if link is up\n"); |
|
3289 return -E1000_ERR_CONFIG; |
|
3290 } |
|
3291 |
|
3292 if (hw->phy_type == e1000_phy_igp) |
|
3293 return e1000_phy_igp_get_info(hw, phy_info); |
|
3294 else |
|
3295 return e1000_phy_m88_get_info(hw, phy_info); |
|
3296 } |
|
3297 |
|
3298 s32 e1000_validate_mdi_setting(struct e1000_hw *hw) |
|
3299 { |
|
3300 e_dbg("e1000_validate_mdi_settings"); |
|
3301 |
|
3302 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { |
|
3303 e_dbg("Invalid MDI setting detected\n"); |
|
3304 hw->mdix = 1; |
|
3305 return -E1000_ERR_CONFIG; |
|
3306 } |
|
3307 return E1000_SUCCESS; |
|
3308 } |
|
3309 |
|
3310 /** |
|
3311 * e1000_init_eeprom_params - initialize sw eeprom vars |
|
3312 * @hw: Struct containing variables accessed by shared code |
|
3313 * |
|
3314 * Sets up eeprom variables in the hw struct. Must be called after mac_type |
|
3315 * is configured. |
|
3316 */ |
|
3317 s32 e1000_init_eeprom_params(struct e1000_hw *hw) |
|
3318 { |
|
3319 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3320 u32 eecd = er32(EECD); |
|
3321 s32 ret_val = E1000_SUCCESS; |
|
3322 u16 eeprom_size; |
|
3323 |
|
3324 e_dbg("e1000_init_eeprom_params"); |
|
3325 |
|
3326 switch (hw->mac_type) { |
|
3327 case e1000_82542_rev2_0: |
|
3328 case e1000_82542_rev2_1: |
|
3329 case e1000_82543: |
|
3330 case e1000_82544: |
|
3331 eeprom->type = e1000_eeprom_microwire; |
|
3332 eeprom->word_size = 64; |
|
3333 eeprom->opcode_bits = 3; |
|
3334 eeprom->address_bits = 6; |
|
3335 eeprom->delay_usec = 50; |
|
3336 break; |
|
3337 case e1000_82540: |
|
3338 case e1000_82545: |
|
3339 case e1000_82545_rev_3: |
|
3340 case e1000_82546: |
|
3341 case e1000_82546_rev_3: |
|
3342 eeprom->type = e1000_eeprom_microwire; |
|
3343 eeprom->opcode_bits = 3; |
|
3344 eeprom->delay_usec = 50; |
|
3345 if (eecd & E1000_EECD_SIZE) { |
|
3346 eeprom->word_size = 256; |
|
3347 eeprom->address_bits = 8; |
|
3348 } else { |
|
3349 eeprom->word_size = 64; |
|
3350 eeprom->address_bits = 6; |
|
3351 } |
|
3352 break; |
|
3353 case e1000_82541: |
|
3354 case e1000_82541_rev_2: |
|
3355 case e1000_82547: |
|
3356 case e1000_82547_rev_2: |
|
3357 if (eecd & E1000_EECD_TYPE) { |
|
3358 eeprom->type = e1000_eeprom_spi; |
|
3359 eeprom->opcode_bits = 8; |
|
3360 eeprom->delay_usec = 1; |
|
3361 if (eecd & E1000_EECD_ADDR_BITS) { |
|
3362 eeprom->page_size = 32; |
|
3363 eeprom->address_bits = 16; |
|
3364 } else { |
|
3365 eeprom->page_size = 8; |
|
3366 eeprom->address_bits = 8; |
|
3367 } |
|
3368 } else { |
|
3369 eeprom->type = e1000_eeprom_microwire; |
|
3370 eeprom->opcode_bits = 3; |
|
3371 eeprom->delay_usec = 50; |
|
3372 if (eecd & E1000_EECD_ADDR_BITS) { |
|
3373 eeprom->word_size = 256; |
|
3374 eeprom->address_bits = 8; |
|
3375 } else { |
|
3376 eeprom->word_size = 64; |
|
3377 eeprom->address_bits = 6; |
|
3378 } |
|
3379 } |
|
3380 break; |
|
3381 default: |
|
3382 break; |
|
3383 } |
|
3384 |
|
3385 if (eeprom->type == e1000_eeprom_spi) { |
|
3386 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
|
3387 * 32KB (incremented by powers of 2). |
|
3388 */ |
|
3389 /* Set to default value for initial eeprom read. */ |
|
3390 eeprom->word_size = 64; |
|
3391 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); |
|
3392 if (ret_val) |
|
3393 return ret_val; |
|
3394 eeprom_size = |
|
3395 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; |
|
3396 /* 256B eeprom size was not supported in earlier hardware, so we |
|
3397 * bump eeprom_size up one to ensure that "1" (which maps to 256B) |
|
3398 * is never the result used in the shifting logic below. */ |
|
3399 if (eeprom_size) |
|
3400 eeprom_size++; |
|
3401 |
|
3402 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); |
|
3403 } |
|
3404 return ret_val; |
|
3405 } |
|
3406 |
|
3407 /** |
|
3408 * e1000_raise_ee_clk - Raises the EEPROM's clock input. |
|
3409 * @hw: Struct containing variables accessed by shared code |
|
3410 * @eecd: EECD's current value |
|
3411 */ |
|
3412 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) |
|
3413 { |
|
3414 /* Raise the clock input to the EEPROM (by setting the SK bit), and then |
|
3415 * wait <delay> microseconds. |
|
3416 */ |
|
3417 *eecd = *eecd | E1000_EECD_SK; |
|
3418 ew32(EECD, *eecd); |
|
3419 E1000_WRITE_FLUSH(); |
|
3420 udelay(hw->eeprom.delay_usec); |
|
3421 } |
|
3422 |
|
3423 /** |
|
3424 * e1000_lower_ee_clk - Lowers the EEPROM's clock input. |
|
3425 * @hw: Struct containing variables accessed by shared code |
|
3426 * @eecd: EECD's current value |
|
3427 */ |
|
3428 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) |
|
3429 { |
|
3430 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then |
|
3431 * wait 50 microseconds. |
|
3432 */ |
|
3433 *eecd = *eecd & ~E1000_EECD_SK; |
|
3434 ew32(EECD, *eecd); |
|
3435 E1000_WRITE_FLUSH(); |
|
3436 udelay(hw->eeprom.delay_usec); |
|
3437 } |
|
3438 |
|
3439 /** |
|
3440 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM. |
|
3441 * @hw: Struct containing variables accessed by shared code |
|
3442 * @data: data to send to the EEPROM |
|
3443 * @count: number of bits to shift out |
|
3444 */ |
|
3445 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) |
|
3446 { |
|
3447 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3448 u32 eecd; |
|
3449 u32 mask; |
|
3450 |
|
3451 /* We need to shift "count" bits out to the EEPROM. So, value in the |
|
3452 * "data" parameter will be shifted out to the EEPROM one bit at a time. |
|
3453 * In order to do this, "data" must be broken down into bits. |
|
3454 */ |
|
3455 mask = 0x01 << (count - 1); |
|
3456 eecd = er32(EECD); |
|
3457 if (eeprom->type == e1000_eeprom_microwire) { |
|
3458 eecd &= ~E1000_EECD_DO; |
|
3459 } else if (eeprom->type == e1000_eeprom_spi) { |
|
3460 eecd |= E1000_EECD_DO; |
|
3461 } |
|
3462 do { |
|
3463 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", |
|
3464 * and then raising and then lowering the clock (the SK bit controls |
|
3465 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM |
|
3466 * by setting "DI" to "0" and then raising and then lowering the clock. |
|
3467 */ |
|
3468 eecd &= ~E1000_EECD_DI; |
|
3469 |
|
3470 if (data & mask) |
|
3471 eecd |= E1000_EECD_DI; |
|
3472 |
|
3473 ew32(EECD, eecd); |
|
3474 E1000_WRITE_FLUSH(); |
|
3475 |
|
3476 udelay(eeprom->delay_usec); |
|
3477 |
|
3478 e1000_raise_ee_clk(hw, &eecd); |
|
3479 e1000_lower_ee_clk(hw, &eecd); |
|
3480 |
|
3481 mask = mask >> 1; |
|
3482 |
|
3483 } while (mask); |
|
3484 |
|
3485 /* We leave the "DI" bit set to "0" when we leave this routine. */ |
|
3486 eecd &= ~E1000_EECD_DI; |
|
3487 ew32(EECD, eecd); |
|
3488 } |
|
3489 |
|
3490 /** |
|
3491 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM |
|
3492 * @hw: Struct containing variables accessed by shared code |
|
3493 * @count: number of bits to shift in |
|
3494 */ |
|
3495 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) |
|
3496 { |
|
3497 u32 eecd; |
|
3498 u32 i; |
|
3499 u16 data; |
|
3500 |
|
3501 /* In order to read a register from the EEPROM, we need to shift 'count' |
|
3502 * bits in from the EEPROM. Bits are "shifted in" by raising the clock |
|
3503 * input to the EEPROM (setting the SK bit), and then reading the value of |
|
3504 * the "DO" bit. During this "shifting in" process the "DI" bit should |
|
3505 * always be clear. |
|
3506 */ |
|
3507 |
|
3508 eecd = er32(EECD); |
|
3509 |
|
3510 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
|
3511 data = 0; |
|
3512 |
|
3513 for (i = 0; i < count; i++) { |
|
3514 data = data << 1; |
|
3515 e1000_raise_ee_clk(hw, &eecd); |
|
3516 |
|
3517 eecd = er32(EECD); |
|
3518 |
|
3519 eecd &= ~(E1000_EECD_DI); |
|
3520 if (eecd & E1000_EECD_DO) |
|
3521 data |= 1; |
|
3522 |
|
3523 e1000_lower_ee_clk(hw, &eecd); |
|
3524 } |
|
3525 |
|
3526 return data; |
|
3527 } |
|
3528 |
|
3529 /** |
|
3530 * e1000_acquire_eeprom - Prepares EEPROM for access |
|
3531 * @hw: Struct containing variables accessed by shared code |
|
3532 * |
|
3533 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This |
|
3534 * function should be called before issuing a command to the EEPROM. |
|
3535 */ |
|
3536 static s32 e1000_acquire_eeprom(struct e1000_hw *hw) |
|
3537 { |
|
3538 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3539 u32 eecd, i = 0; |
|
3540 |
|
3541 e_dbg("e1000_acquire_eeprom"); |
|
3542 |
|
3543 eecd = er32(EECD); |
|
3544 |
|
3545 /* Request EEPROM Access */ |
|
3546 if (hw->mac_type > e1000_82544) { |
|
3547 eecd |= E1000_EECD_REQ; |
|
3548 ew32(EECD, eecd); |
|
3549 eecd = er32(EECD); |
|
3550 while ((!(eecd & E1000_EECD_GNT)) && |
|
3551 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
|
3552 i++; |
|
3553 udelay(5); |
|
3554 eecd = er32(EECD); |
|
3555 } |
|
3556 if (!(eecd & E1000_EECD_GNT)) { |
|
3557 eecd &= ~E1000_EECD_REQ; |
|
3558 ew32(EECD, eecd); |
|
3559 e_dbg("Could not acquire EEPROM grant\n"); |
|
3560 return -E1000_ERR_EEPROM; |
|
3561 } |
|
3562 } |
|
3563 |
|
3564 /* Setup EEPROM for Read/Write */ |
|
3565 |
|
3566 if (eeprom->type == e1000_eeprom_microwire) { |
|
3567 /* Clear SK and DI */ |
|
3568 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); |
|
3569 ew32(EECD, eecd); |
|
3570 |
|
3571 /* Set CS */ |
|
3572 eecd |= E1000_EECD_CS; |
|
3573 ew32(EECD, eecd); |
|
3574 } else if (eeprom->type == e1000_eeprom_spi) { |
|
3575 /* Clear SK and CS */ |
|
3576 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
|
3577 ew32(EECD, eecd); |
|
3578 udelay(1); |
|
3579 } |
|
3580 |
|
3581 return E1000_SUCCESS; |
|
3582 } |
|
3583 |
|
3584 /** |
|
3585 * e1000_standby_eeprom - Returns EEPROM to a "standby" state |
|
3586 * @hw: Struct containing variables accessed by shared code |
|
3587 */ |
|
3588 static void e1000_standby_eeprom(struct e1000_hw *hw) |
|
3589 { |
|
3590 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3591 u32 eecd; |
|
3592 |
|
3593 eecd = er32(EECD); |
|
3594 |
|
3595 if (eeprom->type == e1000_eeprom_microwire) { |
|
3596 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
|
3597 ew32(EECD, eecd); |
|
3598 E1000_WRITE_FLUSH(); |
|
3599 udelay(eeprom->delay_usec); |
|
3600 |
|
3601 /* Clock high */ |
|
3602 eecd |= E1000_EECD_SK; |
|
3603 ew32(EECD, eecd); |
|
3604 E1000_WRITE_FLUSH(); |
|
3605 udelay(eeprom->delay_usec); |
|
3606 |
|
3607 /* Select EEPROM */ |
|
3608 eecd |= E1000_EECD_CS; |
|
3609 ew32(EECD, eecd); |
|
3610 E1000_WRITE_FLUSH(); |
|
3611 udelay(eeprom->delay_usec); |
|
3612 |
|
3613 /* Clock low */ |
|
3614 eecd &= ~E1000_EECD_SK; |
|
3615 ew32(EECD, eecd); |
|
3616 E1000_WRITE_FLUSH(); |
|
3617 udelay(eeprom->delay_usec); |
|
3618 } else if (eeprom->type == e1000_eeprom_spi) { |
|
3619 /* Toggle CS to flush commands */ |
|
3620 eecd |= E1000_EECD_CS; |
|
3621 ew32(EECD, eecd); |
|
3622 E1000_WRITE_FLUSH(); |
|
3623 udelay(eeprom->delay_usec); |
|
3624 eecd &= ~E1000_EECD_CS; |
|
3625 ew32(EECD, eecd); |
|
3626 E1000_WRITE_FLUSH(); |
|
3627 udelay(eeprom->delay_usec); |
|
3628 } |
|
3629 } |
|
3630 |
|
3631 /** |
|
3632 * e1000_release_eeprom - drop chip select |
|
3633 * @hw: Struct containing variables accessed by shared code |
|
3634 * |
|
3635 * Terminates a command by inverting the EEPROM's chip select pin |
|
3636 */ |
|
3637 static void e1000_release_eeprom(struct e1000_hw *hw) |
|
3638 { |
|
3639 u32 eecd; |
|
3640 |
|
3641 e_dbg("e1000_release_eeprom"); |
|
3642 |
|
3643 eecd = er32(EECD); |
|
3644 |
|
3645 if (hw->eeprom.type == e1000_eeprom_spi) { |
|
3646 eecd |= E1000_EECD_CS; /* Pull CS high */ |
|
3647 eecd &= ~E1000_EECD_SK; /* Lower SCK */ |
|
3648 |
|
3649 ew32(EECD, eecd); |
|
3650 |
|
3651 udelay(hw->eeprom.delay_usec); |
|
3652 } else if (hw->eeprom.type == e1000_eeprom_microwire) { |
|
3653 /* cleanup eeprom */ |
|
3654 |
|
3655 /* CS on Microwire is active-high */ |
|
3656 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); |
|
3657 |
|
3658 ew32(EECD, eecd); |
|
3659 |
|
3660 /* Rising edge of clock */ |
|
3661 eecd |= E1000_EECD_SK; |
|
3662 ew32(EECD, eecd); |
|
3663 E1000_WRITE_FLUSH(); |
|
3664 udelay(hw->eeprom.delay_usec); |
|
3665 |
|
3666 /* Falling edge of clock */ |
|
3667 eecd &= ~E1000_EECD_SK; |
|
3668 ew32(EECD, eecd); |
|
3669 E1000_WRITE_FLUSH(); |
|
3670 udelay(hw->eeprom.delay_usec); |
|
3671 } |
|
3672 |
|
3673 /* Stop requesting EEPROM access */ |
|
3674 if (hw->mac_type > e1000_82544) { |
|
3675 eecd &= ~E1000_EECD_REQ; |
|
3676 ew32(EECD, eecd); |
|
3677 } |
|
3678 } |
|
3679 |
|
3680 /** |
|
3681 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM. |
|
3682 * @hw: Struct containing variables accessed by shared code |
|
3683 */ |
|
3684 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) |
|
3685 { |
|
3686 u16 retry_count = 0; |
|
3687 u8 spi_stat_reg; |
|
3688 |
|
3689 e_dbg("e1000_spi_eeprom_ready"); |
|
3690 |
|
3691 /* Read "Status Register" repeatedly until the LSB is cleared. The |
|
3692 * EEPROM will signal that the command has been completed by clearing |
|
3693 * bit 0 of the internal status register. If it's not cleared within |
|
3694 * 5 milliseconds, then error out. |
|
3695 */ |
|
3696 retry_count = 0; |
|
3697 do { |
|
3698 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, |
|
3699 hw->eeprom.opcode_bits); |
|
3700 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8); |
|
3701 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) |
|
3702 break; |
|
3703 |
|
3704 udelay(5); |
|
3705 retry_count += 5; |
|
3706 |
|
3707 e1000_standby_eeprom(hw); |
|
3708 } while (retry_count < EEPROM_MAX_RETRY_SPI); |
|
3709 |
|
3710 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and |
|
3711 * only 0-5mSec on 5V devices) |
|
3712 */ |
|
3713 if (retry_count >= EEPROM_MAX_RETRY_SPI) { |
|
3714 e_dbg("SPI EEPROM Status error\n"); |
|
3715 return -E1000_ERR_EEPROM; |
|
3716 } |
|
3717 |
|
3718 return E1000_SUCCESS; |
|
3719 } |
|
3720 |
|
3721 /** |
|
3722 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM. |
|
3723 * @hw: Struct containing variables accessed by shared code |
|
3724 * @offset: offset of word in the EEPROM to read |
|
3725 * @data: word read from the EEPROM |
|
3726 * @words: number of words to read |
|
3727 */ |
|
3728 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
|
3729 { |
|
3730 s32 ret; |
|
3731 spin_lock(&e1000_eeprom_lock); |
|
3732 ret = e1000_do_read_eeprom(hw, offset, words, data); |
|
3733 spin_unlock(&e1000_eeprom_lock); |
|
3734 return ret; |
|
3735 } |
|
3736 |
|
3737 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
|
3738 u16 *data) |
|
3739 { |
|
3740 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3741 u32 i = 0; |
|
3742 |
|
3743 e_dbg("e1000_read_eeprom"); |
|
3744 |
|
3745 /* If eeprom is not yet detected, do so now */ |
|
3746 if (eeprom->word_size == 0) |
|
3747 e1000_init_eeprom_params(hw); |
|
3748 |
|
3749 /* A check for invalid values: offset too large, too many words, and not |
|
3750 * enough words. |
|
3751 */ |
|
3752 if ((offset >= eeprom->word_size) |
|
3753 || (words > eeprom->word_size - offset) || (words == 0)) { |
|
3754 e_dbg("\"words\" parameter out of bounds. Words = %d," |
|
3755 "size = %d\n", offset, eeprom->word_size); |
|
3756 return -E1000_ERR_EEPROM; |
|
3757 } |
|
3758 |
|
3759 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI |
|
3760 * directly. In this case, we need to acquire the EEPROM so that |
|
3761 * FW or other port software does not interrupt. |
|
3762 */ |
|
3763 /* Prepare the EEPROM for bit-bang reading */ |
|
3764 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
|
3765 return -E1000_ERR_EEPROM; |
|
3766 |
|
3767 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have |
|
3768 * acquired the EEPROM at this point, so any returns should release it */ |
|
3769 if (eeprom->type == e1000_eeprom_spi) { |
|
3770 u16 word_in; |
|
3771 u8 read_opcode = EEPROM_READ_OPCODE_SPI; |
|
3772 |
|
3773 if (e1000_spi_eeprom_ready(hw)) { |
|
3774 e1000_release_eeprom(hw); |
|
3775 return -E1000_ERR_EEPROM; |
|
3776 } |
|
3777 |
|
3778 e1000_standby_eeprom(hw); |
|
3779 |
|
3780 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
|
3781 if ((eeprom->address_bits == 8) && (offset >= 128)) |
|
3782 read_opcode |= EEPROM_A8_OPCODE_SPI; |
|
3783 |
|
3784 /* Send the READ command (opcode + addr) */ |
|
3785 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); |
|
3786 e1000_shift_out_ee_bits(hw, (u16) (offset * 2), |
|
3787 eeprom->address_bits); |
|
3788 |
|
3789 /* Read the data. The address of the eeprom internally increments with |
|
3790 * each byte (spi) being read, saving on the overhead of eeprom setup |
|
3791 * and tear-down. The address counter will roll over if reading beyond |
|
3792 * the size of the eeprom, thus allowing the entire memory to be read |
|
3793 * starting from any offset. */ |
|
3794 for (i = 0; i < words; i++) { |
|
3795 word_in = e1000_shift_in_ee_bits(hw, 16); |
|
3796 data[i] = (word_in >> 8) | (word_in << 8); |
|
3797 } |
|
3798 } else if (eeprom->type == e1000_eeprom_microwire) { |
|
3799 for (i = 0; i < words; i++) { |
|
3800 /* Send the READ command (opcode + addr) */ |
|
3801 e1000_shift_out_ee_bits(hw, |
|
3802 EEPROM_READ_OPCODE_MICROWIRE, |
|
3803 eeprom->opcode_bits); |
|
3804 e1000_shift_out_ee_bits(hw, (u16) (offset + i), |
|
3805 eeprom->address_bits); |
|
3806 |
|
3807 /* Read the data. For microwire, each word requires the overhead |
|
3808 * of eeprom setup and tear-down. */ |
|
3809 data[i] = e1000_shift_in_ee_bits(hw, 16); |
|
3810 e1000_standby_eeprom(hw); |
|
3811 } |
|
3812 } |
|
3813 |
|
3814 /* End this read operation */ |
|
3815 e1000_release_eeprom(hw); |
|
3816 |
|
3817 return E1000_SUCCESS; |
|
3818 } |
|
3819 |
|
3820 /** |
|
3821 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum |
|
3822 * @hw: Struct containing variables accessed by shared code |
|
3823 * |
|
3824 * Reads the first 64 16 bit words of the EEPROM and sums the values read. |
|
3825 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is |
|
3826 * valid. |
|
3827 */ |
|
3828 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
|
3829 { |
|
3830 u16 checksum = 0; |
|
3831 u16 i, eeprom_data; |
|
3832 |
|
3833 e_dbg("e1000_validate_eeprom_checksum"); |
|
3834 |
|
3835 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { |
|
3836 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
|
3837 e_dbg("EEPROM Read Error\n"); |
|
3838 return -E1000_ERR_EEPROM; |
|
3839 } |
|
3840 checksum += eeprom_data; |
|
3841 } |
|
3842 |
|
3843 if (checksum == (u16) EEPROM_SUM) |
|
3844 return E1000_SUCCESS; |
|
3845 else { |
|
3846 e_dbg("EEPROM Checksum Invalid\n"); |
|
3847 return -E1000_ERR_EEPROM; |
|
3848 } |
|
3849 } |
|
3850 |
|
3851 /** |
|
3852 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum |
|
3853 * @hw: Struct containing variables accessed by shared code |
|
3854 * |
|
3855 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. |
|
3856 * Writes the difference to word offset 63 of the EEPROM. |
|
3857 */ |
|
3858 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) |
|
3859 { |
|
3860 u16 checksum = 0; |
|
3861 u16 i, eeprom_data; |
|
3862 |
|
3863 e_dbg("e1000_update_eeprom_checksum"); |
|
3864 |
|
3865 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { |
|
3866 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
|
3867 e_dbg("EEPROM Read Error\n"); |
|
3868 return -E1000_ERR_EEPROM; |
|
3869 } |
|
3870 checksum += eeprom_data; |
|
3871 } |
|
3872 checksum = (u16) EEPROM_SUM - checksum; |
|
3873 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
|
3874 e_dbg("EEPROM Write Error\n"); |
|
3875 return -E1000_ERR_EEPROM; |
|
3876 } |
|
3877 return E1000_SUCCESS; |
|
3878 } |
|
3879 |
|
3880 /** |
|
3881 * e1000_write_eeprom - write words to the different EEPROM types. |
|
3882 * @hw: Struct containing variables accessed by shared code |
|
3883 * @offset: offset within the EEPROM to be written to |
|
3884 * @words: number of words to write |
|
3885 * @data: 16 bit word to be written to the EEPROM |
|
3886 * |
|
3887 * If e1000_update_eeprom_checksum is not called after this function, the |
|
3888 * EEPROM will most likely contain an invalid checksum. |
|
3889 */ |
|
3890 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
|
3891 { |
|
3892 s32 ret; |
|
3893 spin_lock(&e1000_eeprom_lock); |
|
3894 ret = e1000_do_write_eeprom(hw, offset, words, data); |
|
3895 spin_unlock(&e1000_eeprom_lock); |
|
3896 return ret; |
|
3897 } |
|
3898 |
|
3899 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
|
3900 u16 *data) |
|
3901 { |
|
3902 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3903 s32 status = 0; |
|
3904 |
|
3905 e_dbg("e1000_write_eeprom"); |
|
3906 |
|
3907 /* If eeprom is not yet detected, do so now */ |
|
3908 if (eeprom->word_size == 0) |
|
3909 e1000_init_eeprom_params(hw); |
|
3910 |
|
3911 /* A check for invalid values: offset too large, too many words, and not |
|
3912 * enough words. |
|
3913 */ |
|
3914 if ((offset >= eeprom->word_size) |
|
3915 || (words > eeprom->word_size - offset) || (words == 0)) { |
|
3916 e_dbg("\"words\" parameter out of bounds\n"); |
|
3917 return -E1000_ERR_EEPROM; |
|
3918 } |
|
3919 |
|
3920 /* Prepare the EEPROM for writing */ |
|
3921 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
|
3922 return -E1000_ERR_EEPROM; |
|
3923 |
|
3924 if (eeprom->type == e1000_eeprom_microwire) { |
|
3925 status = e1000_write_eeprom_microwire(hw, offset, words, data); |
|
3926 } else { |
|
3927 status = e1000_write_eeprom_spi(hw, offset, words, data); |
|
3928 msleep(10); |
|
3929 } |
|
3930 |
|
3931 /* Done with writing */ |
|
3932 e1000_release_eeprom(hw); |
|
3933 |
|
3934 return status; |
|
3935 } |
|
3936 |
|
3937 /** |
|
3938 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM. |
|
3939 * @hw: Struct containing variables accessed by shared code |
|
3940 * @offset: offset within the EEPROM to be written to |
|
3941 * @words: number of words to write |
|
3942 * @data: pointer to array of 8 bit words to be written to the EEPROM |
|
3943 */ |
|
3944 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, |
|
3945 u16 *data) |
|
3946 { |
|
3947 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3948 u16 widx = 0; |
|
3949 |
|
3950 e_dbg("e1000_write_eeprom_spi"); |
|
3951 |
|
3952 while (widx < words) { |
|
3953 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; |
|
3954 |
|
3955 if (e1000_spi_eeprom_ready(hw)) |
|
3956 return -E1000_ERR_EEPROM; |
|
3957 |
|
3958 e1000_standby_eeprom(hw); |
|
3959 |
|
3960 /* Send the WRITE ENABLE command (8 bit opcode ) */ |
|
3961 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, |
|
3962 eeprom->opcode_bits); |
|
3963 |
|
3964 e1000_standby_eeprom(hw); |
|
3965 |
|
3966 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
|
3967 if ((eeprom->address_bits == 8) && (offset >= 128)) |
|
3968 write_opcode |= EEPROM_A8_OPCODE_SPI; |
|
3969 |
|
3970 /* Send the Write command (8-bit opcode + addr) */ |
|
3971 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); |
|
3972 |
|
3973 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2), |
|
3974 eeprom->address_bits); |
|
3975 |
|
3976 /* Send the data */ |
|
3977 |
|
3978 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ |
|
3979 while (widx < words) { |
|
3980 u16 word_out = data[widx]; |
|
3981 word_out = (word_out >> 8) | (word_out << 8); |
|
3982 e1000_shift_out_ee_bits(hw, word_out, 16); |
|
3983 widx++; |
|
3984 |
|
3985 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE |
|
3986 * operation, while the smaller eeproms are capable of an 8-byte |
|
3987 * PAGE WRITE operation. Break the inner loop to pass new address |
|
3988 */ |
|
3989 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { |
|
3990 e1000_standby_eeprom(hw); |
|
3991 break; |
|
3992 } |
|
3993 } |
|
3994 } |
|
3995 |
|
3996 return E1000_SUCCESS; |
|
3997 } |
|
3998 |
|
3999 /** |
|
4000 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM. |
|
4001 * @hw: Struct containing variables accessed by shared code |
|
4002 * @offset: offset within the EEPROM to be written to |
|
4003 * @words: number of words to write |
|
4004 * @data: pointer to array of 8 bit words to be written to the EEPROM |
|
4005 */ |
|
4006 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, |
|
4007 u16 words, u16 *data) |
|
4008 { |
|
4009 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4010 u32 eecd; |
|
4011 u16 words_written = 0; |
|
4012 u16 i = 0; |
|
4013 |
|
4014 e_dbg("e1000_write_eeprom_microwire"); |
|
4015 |
|
4016 /* Send the write enable command to the EEPROM (3-bit opcode plus |
|
4017 * 6/8-bit dummy address beginning with 11). It's less work to include |
|
4018 * the 11 of the dummy address as part of the opcode than it is to shift |
|
4019 * it over the correct number of bits for the address. This puts the |
|
4020 * EEPROM into write/erase mode. |
|
4021 */ |
|
4022 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, |
|
4023 (u16) (eeprom->opcode_bits + 2)); |
|
4024 |
|
4025 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); |
|
4026 |
|
4027 /* Prepare the EEPROM */ |
|
4028 e1000_standby_eeprom(hw); |
|
4029 |
|
4030 while (words_written < words) { |
|
4031 /* Send the Write command (3-bit opcode + addr) */ |
|
4032 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, |
|
4033 eeprom->opcode_bits); |
|
4034 |
|
4035 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written), |
|
4036 eeprom->address_bits); |
|
4037 |
|
4038 /* Send the data */ |
|
4039 e1000_shift_out_ee_bits(hw, data[words_written], 16); |
|
4040 |
|
4041 /* Toggle the CS line. This in effect tells the EEPROM to execute |
|
4042 * the previous command. |
|
4043 */ |
|
4044 e1000_standby_eeprom(hw); |
|
4045 |
|
4046 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will |
|
4047 * signal that the command has been completed by raising the DO signal. |
|
4048 * If DO does not go high in 10 milliseconds, then error out. |
|
4049 */ |
|
4050 for (i = 0; i < 200; i++) { |
|
4051 eecd = er32(EECD); |
|
4052 if (eecd & E1000_EECD_DO) |
|
4053 break; |
|
4054 udelay(50); |
|
4055 } |
|
4056 if (i == 200) { |
|
4057 e_dbg("EEPROM Write did not complete\n"); |
|
4058 return -E1000_ERR_EEPROM; |
|
4059 } |
|
4060 |
|
4061 /* Recover from write */ |
|
4062 e1000_standby_eeprom(hw); |
|
4063 |
|
4064 words_written++; |
|
4065 } |
|
4066 |
|
4067 /* Send the write disable command to the EEPROM (3-bit opcode plus |
|
4068 * 6/8-bit dummy address beginning with 10). It's less work to include |
|
4069 * the 10 of the dummy address as part of the opcode than it is to shift |
|
4070 * it over the correct number of bits for the address. This takes the |
|
4071 * EEPROM out of write/erase mode. |
|
4072 */ |
|
4073 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, |
|
4074 (u16) (eeprom->opcode_bits + 2)); |
|
4075 |
|
4076 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); |
|
4077 |
|
4078 return E1000_SUCCESS; |
|
4079 } |
|
4080 |
|
4081 /** |
|
4082 * e1000_read_mac_addr - read the adapters MAC from eeprom |
|
4083 * @hw: Struct containing variables accessed by shared code |
|
4084 * |
|
4085 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the |
|
4086 * second function of dual function devices |
|
4087 */ |
|
4088 s32 e1000_read_mac_addr(struct e1000_hw *hw) |
|
4089 { |
|
4090 u16 offset; |
|
4091 u16 eeprom_data, i; |
|
4092 |
|
4093 e_dbg("e1000_read_mac_addr"); |
|
4094 |
|
4095 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
|
4096 offset = i >> 1; |
|
4097 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
|
4098 e_dbg("EEPROM Read Error\n"); |
|
4099 return -E1000_ERR_EEPROM; |
|
4100 } |
|
4101 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); |
|
4102 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8); |
|
4103 } |
|
4104 |
|
4105 switch (hw->mac_type) { |
|
4106 default: |
|
4107 break; |
|
4108 case e1000_82546: |
|
4109 case e1000_82546_rev_3: |
|
4110 if (er32(STATUS) & E1000_STATUS_FUNC_1) |
|
4111 hw->perm_mac_addr[5] ^= 0x01; |
|
4112 break; |
|
4113 } |
|
4114 |
|
4115 for (i = 0; i < NODE_ADDRESS_SIZE; i++) |
|
4116 hw->mac_addr[i] = hw->perm_mac_addr[i]; |
|
4117 return E1000_SUCCESS; |
|
4118 } |
|
4119 |
|
4120 /** |
|
4121 * e1000_init_rx_addrs - Initializes receive address filters. |
|
4122 * @hw: Struct containing variables accessed by shared code |
|
4123 * |
|
4124 * Places the MAC address in receive address register 0 and clears the rest |
|
4125 * of the receive address registers. Clears the multicast table. Assumes |
|
4126 * the receiver is in reset when the routine is called. |
|
4127 */ |
|
4128 static void e1000_init_rx_addrs(struct e1000_hw *hw) |
|
4129 { |
|
4130 u32 i; |
|
4131 u32 rar_num; |
|
4132 |
|
4133 e_dbg("e1000_init_rx_addrs"); |
|
4134 |
|
4135 /* Setup the receive address. */ |
|
4136 e_dbg("Programming MAC Address into RAR[0]\n"); |
|
4137 |
|
4138 e1000_rar_set(hw, hw->mac_addr, 0); |
|
4139 |
|
4140 rar_num = E1000_RAR_ENTRIES; |
|
4141 |
|
4142 /* Zero out the other 15 receive addresses. */ |
|
4143 e_dbg("Clearing RAR[1-15]\n"); |
|
4144 for (i = 1; i < rar_num; i++) { |
|
4145 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
|
4146 E1000_WRITE_FLUSH(); |
|
4147 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
|
4148 E1000_WRITE_FLUSH(); |
|
4149 } |
|
4150 } |
|
4151 |
|
4152 /** |
|
4153 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table |
|
4154 * @hw: Struct containing variables accessed by shared code |
|
4155 * @mc_addr: the multicast address to hash |
|
4156 */ |
|
4157 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
|
4158 { |
|
4159 u32 hash_value = 0; |
|
4160 |
|
4161 /* The portion of the address that is used for the hash table is |
|
4162 * determined by the mc_filter_type setting. |
|
4163 */ |
|
4164 switch (hw->mc_filter_type) { |
|
4165 /* [0] [1] [2] [3] [4] [5] |
|
4166 * 01 AA 00 12 34 56 |
|
4167 * LSB MSB |
|
4168 */ |
|
4169 case 0: |
|
4170 /* [47:36] i.e. 0x563 for above example address */ |
|
4171 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); |
|
4172 break; |
|
4173 case 1: |
|
4174 /* [46:35] i.e. 0xAC6 for above example address */ |
|
4175 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); |
|
4176 break; |
|
4177 case 2: |
|
4178 /* [45:34] i.e. 0x5D8 for above example address */ |
|
4179 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); |
|
4180 break; |
|
4181 case 3: |
|
4182 /* [43:32] i.e. 0x634 for above example address */ |
|
4183 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); |
|
4184 break; |
|
4185 } |
|
4186 |
|
4187 hash_value &= 0xFFF; |
|
4188 return hash_value; |
|
4189 } |
|
4190 |
|
4191 /** |
|
4192 * e1000_rar_set - Puts an ethernet address into a receive address register. |
|
4193 * @hw: Struct containing variables accessed by shared code |
|
4194 * @addr: Address to put into receive address register |
|
4195 * @index: Receive address register to write |
|
4196 */ |
|
4197 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) |
|
4198 { |
|
4199 u32 rar_low, rar_high; |
|
4200 |
|
4201 /* HW expects these in little endian so we reverse the byte order |
|
4202 * from network order (big endian) to little endian |
|
4203 */ |
|
4204 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | |
|
4205 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
|
4206 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
|
4207 |
|
4208 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx |
|
4209 * unit hang. |
|
4210 * |
|
4211 * Description: |
|
4212 * If there are any Rx frames queued up or otherwise present in the HW |
|
4213 * before RSS is enabled, and then we enable RSS, the HW Rx unit will |
|
4214 * hang. To work around this issue, we have to disable receives and |
|
4215 * flush out all Rx frames before we enable RSS. To do so, we modify we |
|
4216 * redirect all Rx traffic to manageability and then reset the HW. |
|
4217 * This flushes away Rx frames, and (since the redirections to |
|
4218 * manageability persists across resets) keeps new ones from coming in |
|
4219 * while we work. Then, we clear the Address Valid AV bit for all MAC |
|
4220 * addresses and undo the re-direction to manageability. |
|
4221 * Now, frames are coming in again, but the MAC won't accept them, so |
|
4222 * far so good. We now proceed to initialize RSS (if necessary) and |
|
4223 * configure the Rx unit. Last, we re-enable the AV bits and continue |
|
4224 * on our merry way. |
|
4225 */ |
|
4226 switch (hw->mac_type) { |
|
4227 default: |
|
4228 /* Indicate to hardware the Address is Valid. */ |
|
4229 rar_high |= E1000_RAH_AV; |
|
4230 break; |
|
4231 } |
|
4232 |
|
4233 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); |
|
4234 E1000_WRITE_FLUSH(); |
|
4235 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); |
|
4236 E1000_WRITE_FLUSH(); |
|
4237 } |
|
4238 |
|
4239 /** |
|
4240 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table. |
|
4241 * @hw: Struct containing variables accessed by shared code |
|
4242 * @offset: Offset in VLAN filer table to write |
|
4243 * @value: Value to write into VLAN filter table |
|
4244 */ |
|
4245 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) |
|
4246 { |
|
4247 u32 temp; |
|
4248 |
|
4249 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { |
|
4250 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); |
|
4251 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
|
4252 E1000_WRITE_FLUSH(); |
|
4253 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); |
|
4254 E1000_WRITE_FLUSH(); |
|
4255 } else { |
|
4256 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
|
4257 E1000_WRITE_FLUSH(); |
|
4258 } |
|
4259 } |
|
4260 |
|
4261 /** |
|
4262 * e1000_clear_vfta - Clears the VLAN filer table |
|
4263 * @hw: Struct containing variables accessed by shared code |
|
4264 */ |
|
4265 static void e1000_clear_vfta(struct e1000_hw *hw) |
|
4266 { |
|
4267 u32 offset; |
|
4268 u32 vfta_value = 0; |
|
4269 u32 vfta_offset = 0; |
|
4270 u32 vfta_bit_in_reg = 0; |
|
4271 |
|
4272 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
|
4273 /* If the offset we want to clear is the same offset of the |
|
4274 * manageability VLAN ID, then clear all bits except that of the |
|
4275 * manageability unit */ |
|
4276 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; |
|
4277 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); |
|
4278 E1000_WRITE_FLUSH(); |
|
4279 } |
|
4280 } |
|
4281 |
|
4282 static s32 e1000_id_led_init(struct e1000_hw *hw) |
|
4283 { |
|
4284 u32 ledctl; |
|
4285 const u32 ledctl_mask = 0x000000FF; |
|
4286 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
|
4287 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
|
4288 u16 eeprom_data, i, temp; |
|
4289 const u16 led_mask = 0x0F; |
|
4290 |
|
4291 e_dbg("e1000_id_led_init"); |
|
4292 |
|
4293 if (hw->mac_type < e1000_82540) { |
|
4294 /* Nothing to do */ |
|
4295 return E1000_SUCCESS; |
|
4296 } |
|
4297 |
|
4298 ledctl = er32(LEDCTL); |
|
4299 hw->ledctl_default = ledctl; |
|
4300 hw->ledctl_mode1 = hw->ledctl_default; |
|
4301 hw->ledctl_mode2 = hw->ledctl_default; |
|
4302 |
|
4303 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { |
|
4304 e_dbg("EEPROM Read Error\n"); |
|
4305 return -E1000_ERR_EEPROM; |
|
4306 } |
|
4307 |
|
4308 if ((eeprom_data == ID_LED_RESERVED_0000) || |
|
4309 (eeprom_data == ID_LED_RESERVED_FFFF)) { |
|
4310 eeprom_data = ID_LED_DEFAULT; |
|
4311 } |
|
4312 |
|
4313 for (i = 0; i < 4; i++) { |
|
4314 temp = (eeprom_data >> (i << 2)) & led_mask; |
|
4315 switch (temp) { |
|
4316 case ID_LED_ON1_DEF2: |
|
4317 case ID_LED_ON1_ON2: |
|
4318 case ID_LED_ON1_OFF2: |
|
4319 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
4320 hw->ledctl_mode1 |= ledctl_on << (i << 3); |
|
4321 break; |
|
4322 case ID_LED_OFF1_DEF2: |
|
4323 case ID_LED_OFF1_ON2: |
|
4324 case ID_LED_OFF1_OFF2: |
|
4325 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
4326 hw->ledctl_mode1 |= ledctl_off << (i << 3); |
|
4327 break; |
|
4328 default: |
|
4329 /* Do nothing */ |
|
4330 break; |
|
4331 } |
|
4332 switch (temp) { |
|
4333 case ID_LED_DEF1_ON2: |
|
4334 case ID_LED_ON1_ON2: |
|
4335 case ID_LED_OFF1_ON2: |
|
4336 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
4337 hw->ledctl_mode2 |= ledctl_on << (i << 3); |
|
4338 break; |
|
4339 case ID_LED_DEF1_OFF2: |
|
4340 case ID_LED_ON1_OFF2: |
|
4341 case ID_LED_OFF1_OFF2: |
|
4342 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
4343 hw->ledctl_mode2 |= ledctl_off << (i << 3); |
|
4344 break; |
|
4345 default: |
|
4346 /* Do nothing */ |
|
4347 break; |
|
4348 } |
|
4349 } |
|
4350 return E1000_SUCCESS; |
|
4351 } |
|
4352 |
|
4353 /** |
|
4354 * e1000_setup_led |
|
4355 * @hw: Struct containing variables accessed by shared code |
|
4356 * |
|
4357 * Prepares SW controlable LED for use and saves the current state of the LED. |
|
4358 */ |
|
4359 s32 e1000_setup_led(struct e1000_hw *hw) |
|
4360 { |
|
4361 u32 ledctl; |
|
4362 s32 ret_val = E1000_SUCCESS; |
|
4363 |
|
4364 e_dbg("e1000_setup_led"); |
|
4365 |
|
4366 switch (hw->mac_type) { |
|
4367 case e1000_82542_rev2_0: |
|
4368 case e1000_82542_rev2_1: |
|
4369 case e1000_82543: |
|
4370 case e1000_82544: |
|
4371 /* No setup necessary */ |
|
4372 break; |
|
4373 case e1000_82541: |
|
4374 case e1000_82547: |
|
4375 case e1000_82541_rev_2: |
|
4376 case e1000_82547_rev_2: |
|
4377 /* Turn off PHY Smart Power Down (if enabled) */ |
|
4378 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
4379 &hw->phy_spd_default); |
|
4380 if (ret_val) |
|
4381 return ret_val; |
|
4382 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
4383 (u16) (hw->phy_spd_default & |
|
4384 ~IGP01E1000_GMII_SPD)); |
|
4385 if (ret_val) |
|
4386 return ret_val; |
|
4387 /* Fall Through */ |
|
4388 default: |
|
4389 if (hw->media_type == e1000_media_type_fiber) { |
|
4390 ledctl = er32(LEDCTL); |
|
4391 /* Save current LEDCTL settings */ |
|
4392 hw->ledctl_default = ledctl; |
|
4393 /* Turn off LED0 */ |
|
4394 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | |
|
4395 E1000_LEDCTL_LED0_BLINK | |
|
4396 E1000_LEDCTL_LED0_MODE_MASK); |
|
4397 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << |
|
4398 E1000_LEDCTL_LED0_MODE_SHIFT); |
|
4399 ew32(LEDCTL, ledctl); |
|
4400 } else if (hw->media_type == e1000_media_type_copper) |
|
4401 ew32(LEDCTL, hw->ledctl_mode1); |
|
4402 break; |
|
4403 } |
|
4404 |
|
4405 return E1000_SUCCESS; |
|
4406 } |
|
4407 |
|
4408 /** |
|
4409 * e1000_cleanup_led - Restores the saved state of the SW controlable LED. |
|
4410 * @hw: Struct containing variables accessed by shared code |
|
4411 */ |
|
4412 s32 e1000_cleanup_led(struct e1000_hw *hw) |
|
4413 { |
|
4414 s32 ret_val = E1000_SUCCESS; |
|
4415 |
|
4416 e_dbg("e1000_cleanup_led"); |
|
4417 |
|
4418 switch (hw->mac_type) { |
|
4419 case e1000_82542_rev2_0: |
|
4420 case e1000_82542_rev2_1: |
|
4421 case e1000_82543: |
|
4422 case e1000_82544: |
|
4423 /* No cleanup necessary */ |
|
4424 break; |
|
4425 case e1000_82541: |
|
4426 case e1000_82547: |
|
4427 case e1000_82541_rev_2: |
|
4428 case e1000_82547_rev_2: |
|
4429 /* Turn on PHY Smart Power Down (if previously enabled) */ |
|
4430 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
4431 hw->phy_spd_default); |
|
4432 if (ret_val) |
|
4433 return ret_val; |
|
4434 /* Fall Through */ |
|
4435 default: |
|
4436 /* Restore LEDCTL settings */ |
|
4437 ew32(LEDCTL, hw->ledctl_default); |
|
4438 break; |
|
4439 } |
|
4440 |
|
4441 return E1000_SUCCESS; |
|
4442 } |
|
4443 |
|
4444 /** |
|
4445 * e1000_led_on - Turns on the software controllable LED |
|
4446 * @hw: Struct containing variables accessed by shared code |
|
4447 */ |
|
4448 s32 e1000_led_on(struct e1000_hw *hw) |
|
4449 { |
|
4450 u32 ctrl = er32(CTRL); |
|
4451 |
|
4452 e_dbg("e1000_led_on"); |
|
4453 |
|
4454 switch (hw->mac_type) { |
|
4455 case e1000_82542_rev2_0: |
|
4456 case e1000_82542_rev2_1: |
|
4457 case e1000_82543: |
|
4458 /* Set SW Defineable Pin 0 to turn on the LED */ |
|
4459 ctrl |= E1000_CTRL_SWDPIN0; |
|
4460 ctrl |= E1000_CTRL_SWDPIO0; |
|
4461 break; |
|
4462 case e1000_82544: |
|
4463 if (hw->media_type == e1000_media_type_fiber) { |
|
4464 /* Set SW Defineable Pin 0 to turn on the LED */ |
|
4465 ctrl |= E1000_CTRL_SWDPIN0; |
|
4466 ctrl |= E1000_CTRL_SWDPIO0; |
|
4467 } else { |
|
4468 /* Clear SW Defineable Pin 0 to turn on the LED */ |
|
4469 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
4470 ctrl |= E1000_CTRL_SWDPIO0; |
|
4471 } |
|
4472 break; |
|
4473 default: |
|
4474 if (hw->media_type == e1000_media_type_fiber) { |
|
4475 /* Clear SW Defineable Pin 0 to turn on the LED */ |
|
4476 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
4477 ctrl |= E1000_CTRL_SWDPIO0; |
|
4478 } else if (hw->media_type == e1000_media_type_copper) { |
|
4479 ew32(LEDCTL, hw->ledctl_mode2); |
|
4480 return E1000_SUCCESS; |
|
4481 } |
|
4482 break; |
|
4483 } |
|
4484 |
|
4485 ew32(CTRL, ctrl); |
|
4486 |
|
4487 return E1000_SUCCESS; |
|
4488 } |
|
4489 |
|
4490 /** |
|
4491 * e1000_led_off - Turns off the software controllable LED |
|
4492 * @hw: Struct containing variables accessed by shared code |
|
4493 */ |
|
4494 s32 e1000_led_off(struct e1000_hw *hw) |
|
4495 { |
|
4496 u32 ctrl = er32(CTRL); |
|
4497 |
|
4498 e_dbg("e1000_led_off"); |
|
4499 |
|
4500 switch (hw->mac_type) { |
|
4501 case e1000_82542_rev2_0: |
|
4502 case e1000_82542_rev2_1: |
|
4503 case e1000_82543: |
|
4504 /* Clear SW Defineable Pin 0 to turn off the LED */ |
|
4505 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
4506 ctrl |= E1000_CTRL_SWDPIO0; |
|
4507 break; |
|
4508 case e1000_82544: |
|
4509 if (hw->media_type == e1000_media_type_fiber) { |
|
4510 /* Clear SW Defineable Pin 0 to turn off the LED */ |
|
4511 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
4512 ctrl |= E1000_CTRL_SWDPIO0; |
|
4513 } else { |
|
4514 /* Set SW Defineable Pin 0 to turn off the LED */ |
|
4515 ctrl |= E1000_CTRL_SWDPIN0; |
|
4516 ctrl |= E1000_CTRL_SWDPIO0; |
|
4517 } |
|
4518 break; |
|
4519 default: |
|
4520 if (hw->media_type == e1000_media_type_fiber) { |
|
4521 /* Set SW Defineable Pin 0 to turn off the LED */ |
|
4522 ctrl |= E1000_CTRL_SWDPIN0; |
|
4523 ctrl |= E1000_CTRL_SWDPIO0; |
|
4524 } else if (hw->media_type == e1000_media_type_copper) { |
|
4525 ew32(LEDCTL, hw->ledctl_mode1); |
|
4526 return E1000_SUCCESS; |
|
4527 } |
|
4528 break; |
|
4529 } |
|
4530 |
|
4531 ew32(CTRL, ctrl); |
|
4532 |
|
4533 return E1000_SUCCESS; |
|
4534 } |
|
4535 |
|
4536 /** |
|
4537 * e1000_clear_hw_cntrs - Clears all hardware statistics counters. |
|
4538 * @hw: Struct containing variables accessed by shared code |
|
4539 */ |
|
4540 static void e1000_clear_hw_cntrs(struct e1000_hw *hw) |
|
4541 { |
|
4542 volatile u32 temp; |
|
4543 |
|
4544 temp = er32(CRCERRS); |
|
4545 temp = er32(SYMERRS); |
|
4546 temp = er32(MPC); |
|
4547 temp = er32(SCC); |
|
4548 temp = er32(ECOL); |
|
4549 temp = er32(MCC); |
|
4550 temp = er32(LATECOL); |
|
4551 temp = er32(COLC); |
|
4552 temp = er32(DC); |
|
4553 temp = er32(SEC); |
|
4554 temp = er32(RLEC); |
|
4555 temp = er32(XONRXC); |
|
4556 temp = er32(XONTXC); |
|
4557 temp = er32(XOFFRXC); |
|
4558 temp = er32(XOFFTXC); |
|
4559 temp = er32(FCRUC); |
|
4560 |
|
4561 temp = er32(PRC64); |
|
4562 temp = er32(PRC127); |
|
4563 temp = er32(PRC255); |
|
4564 temp = er32(PRC511); |
|
4565 temp = er32(PRC1023); |
|
4566 temp = er32(PRC1522); |
|
4567 |
|
4568 temp = er32(GPRC); |
|
4569 temp = er32(BPRC); |
|
4570 temp = er32(MPRC); |
|
4571 temp = er32(GPTC); |
|
4572 temp = er32(GORCL); |
|
4573 temp = er32(GORCH); |
|
4574 temp = er32(GOTCL); |
|
4575 temp = er32(GOTCH); |
|
4576 temp = er32(RNBC); |
|
4577 temp = er32(RUC); |
|
4578 temp = er32(RFC); |
|
4579 temp = er32(ROC); |
|
4580 temp = er32(RJC); |
|
4581 temp = er32(TORL); |
|
4582 temp = er32(TORH); |
|
4583 temp = er32(TOTL); |
|
4584 temp = er32(TOTH); |
|
4585 temp = er32(TPR); |
|
4586 temp = er32(TPT); |
|
4587 |
|
4588 temp = er32(PTC64); |
|
4589 temp = er32(PTC127); |
|
4590 temp = er32(PTC255); |
|
4591 temp = er32(PTC511); |
|
4592 temp = er32(PTC1023); |
|
4593 temp = er32(PTC1522); |
|
4594 |
|
4595 temp = er32(MPTC); |
|
4596 temp = er32(BPTC); |
|
4597 |
|
4598 if (hw->mac_type < e1000_82543) |
|
4599 return; |
|
4600 |
|
4601 temp = er32(ALGNERRC); |
|
4602 temp = er32(RXERRC); |
|
4603 temp = er32(TNCRS); |
|
4604 temp = er32(CEXTERR); |
|
4605 temp = er32(TSCTC); |
|
4606 temp = er32(TSCTFC); |
|
4607 |
|
4608 if (hw->mac_type <= e1000_82544) |
|
4609 return; |
|
4610 |
|
4611 temp = er32(MGTPRC); |
|
4612 temp = er32(MGTPDC); |
|
4613 temp = er32(MGTPTC); |
|
4614 } |
|
4615 |
|
4616 /** |
|
4617 * e1000_reset_adaptive - Resets Adaptive IFS to its default state. |
|
4618 * @hw: Struct containing variables accessed by shared code |
|
4619 * |
|
4620 * Call this after e1000_init_hw. You may override the IFS defaults by setting |
|
4621 * hw->ifs_params_forced to true. However, you must initialize hw-> |
|
4622 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio |
|
4623 * before calling this function. |
|
4624 */ |
|
4625 void e1000_reset_adaptive(struct e1000_hw *hw) |
|
4626 { |
|
4627 e_dbg("e1000_reset_adaptive"); |
|
4628 |
|
4629 if (hw->adaptive_ifs) { |
|
4630 if (!hw->ifs_params_forced) { |
|
4631 hw->current_ifs_val = 0; |
|
4632 hw->ifs_min_val = IFS_MIN; |
|
4633 hw->ifs_max_val = IFS_MAX; |
|
4634 hw->ifs_step_size = IFS_STEP; |
|
4635 hw->ifs_ratio = IFS_RATIO; |
|
4636 } |
|
4637 hw->in_ifs_mode = false; |
|
4638 ew32(AIT, 0); |
|
4639 } else { |
|
4640 e_dbg("Not in Adaptive IFS mode!\n"); |
|
4641 } |
|
4642 } |
|
4643 |
|
4644 /** |
|
4645 * e1000_update_adaptive - update adaptive IFS |
|
4646 * @hw: Struct containing variables accessed by shared code |
|
4647 * @tx_packets: Number of transmits since last callback |
|
4648 * @total_collisions: Number of collisions since last callback |
|
4649 * |
|
4650 * Called during the callback/watchdog routine to update IFS value based on |
|
4651 * the ratio of transmits to collisions. |
|
4652 */ |
|
4653 void e1000_update_adaptive(struct e1000_hw *hw) |
|
4654 { |
|
4655 e_dbg("e1000_update_adaptive"); |
|
4656 |
|
4657 if (hw->adaptive_ifs) { |
|
4658 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { |
|
4659 if (hw->tx_packet_delta > MIN_NUM_XMITS) { |
|
4660 hw->in_ifs_mode = true; |
|
4661 if (hw->current_ifs_val < hw->ifs_max_val) { |
|
4662 if (hw->current_ifs_val == 0) |
|
4663 hw->current_ifs_val = |
|
4664 hw->ifs_min_val; |
|
4665 else |
|
4666 hw->current_ifs_val += |
|
4667 hw->ifs_step_size; |
|
4668 ew32(AIT, hw->current_ifs_val); |
|
4669 } |
|
4670 } |
|
4671 } else { |
|
4672 if (hw->in_ifs_mode |
|
4673 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { |
|
4674 hw->current_ifs_val = 0; |
|
4675 hw->in_ifs_mode = false; |
|
4676 ew32(AIT, 0); |
|
4677 } |
|
4678 } |
|
4679 } else { |
|
4680 e_dbg("Not in Adaptive IFS mode!\n"); |
|
4681 } |
|
4682 } |
|
4683 |
|
4684 /** |
|
4685 * e1000_tbi_adjust_stats |
|
4686 * @hw: Struct containing variables accessed by shared code |
|
4687 * @frame_len: The length of the frame in question |
|
4688 * @mac_addr: The Ethernet destination address of the frame in question |
|
4689 * |
|
4690 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT |
|
4691 */ |
|
4692 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, |
|
4693 u32 frame_len, u8 *mac_addr) |
|
4694 { |
|
4695 u64 carry_bit; |
|
4696 |
|
4697 /* First adjust the frame length. */ |
|
4698 frame_len--; |
|
4699 /* We need to adjust the statistics counters, since the hardware |
|
4700 * counters overcount this packet as a CRC error and undercount |
|
4701 * the packet as a good packet |
|
4702 */ |
|
4703 /* This packet should not be counted as a CRC error. */ |
|
4704 stats->crcerrs--; |
|
4705 /* This packet does count as a Good Packet Received. */ |
|
4706 stats->gprc++; |
|
4707 |
|
4708 /* Adjust the Good Octets received counters */ |
|
4709 carry_bit = 0x80000000 & stats->gorcl; |
|
4710 stats->gorcl += frame_len; |
|
4711 /* If the high bit of Gorcl (the low 32 bits of the Good Octets |
|
4712 * Received Count) was one before the addition, |
|
4713 * AND it is zero after, then we lost the carry out, |
|
4714 * need to add one to Gorch (Good Octets Received Count High). |
|
4715 * This could be simplified if all environments supported |
|
4716 * 64-bit integers. |
|
4717 */ |
|
4718 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) |
|
4719 stats->gorch++; |
|
4720 /* Is this a broadcast or multicast? Check broadcast first, |
|
4721 * since the test for a multicast frame will test positive on |
|
4722 * a broadcast frame. |
|
4723 */ |
|
4724 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff)) |
|
4725 /* Broadcast packet */ |
|
4726 stats->bprc++; |
|
4727 else if (*mac_addr & 0x01) |
|
4728 /* Multicast packet */ |
|
4729 stats->mprc++; |
|
4730 |
|
4731 if (frame_len == hw->max_frame_size) { |
|
4732 /* In this case, the hardware has overcounted the number of |
|
4733 * oversize frames. |
|
4734 */ |
|
4735 if (stats->roc > 0) |
|
4736 stats->roc--; |
|
4737 } |
|
4738 |
|
4739 /* Adjust the bin counters when the extra byte put the frame in the |
|
4740 * wrong bin. Remember that the frame_len was adjusted above. |
|
4741 */ |
|
4742 if (frame_len == 64) { |
|
4743 stats->prc64++; |
|
4744 stats->prc127--; |
|
4745 } else if (frame_len == 127) { |
|
4746 stats->prc127++; |
|
4747 stats->prc255--; |
|
4748 } else if (frame_len == 255) { |
|
4749 stats->prc255++; |
|
4750 stats->prc511--; |
|
4751 } else if (frame_len == 511) { |
|
4752 stats->prc511++; |
|
4753 stats->prc1023--; |
|
4754 } else if (frame_len == 1023) { |
|
4755 stats->prc1023++; |
|
4756 stats->prc1522--; |
|
4757 } else if (frame_len == 1522) { |
|
4758 stats->prc1522++; |
|
4759 } |
|
4760 } |
|
4761 |
|
4762 /** |
|
4763 * e1000_get_bus_info |
|
4764 * @hw: Struct containing variables accessed by shared code |
|
4765 * |
|
4766 * Gets the current PCI bus type, speed, and width of the hardware |
|
4767 */ |
|
4768 void e1000_get_bus_info(struct e1000_hw *hw) |
|
4769 { |
|
4770 u32 status; |
|
4771 |
|
4772 switch (hw->mac_type) { |
|
4773 case e1000_82542_rev2_0: |
|
4774 case e1000_82542_rev2_1: |
|
4775 hw->bus_type = e1000_bus_type_pci; |
|
4776 hw->bus_speed = e1000_bus_speed_unknown; |
|
4777 hw->bus_width = e1000_bus_width_unknown; |
|
4778 break; |
|
4779 default: |
|
4780 status = er32(STATUS); |
|
4781 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
|
4782 e1000_bus_type_pcix : e1000_bus_type_pci; |
|
4783 |
|
4784 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { |
|
4785 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? |
|
4786 e1000_bus_speed_66 : e1000_bus_speed_120; |
|
4787 } else if (hw->bus_type == e1000_bus_type_pci) { |
|
4788 hw->bus_speed = (status & E1000_STATUS_PCI66) ? |
|
4789 e1000_bus_speed_66 : e1000_bus_speed_33; |
|
4790 } else { |
|
4791 switch (status & E1000_STATUS_PCIX_SPEED) { |
|
4792 case E1000_STATUS_PCIX_SPEED_66: |
|
4793 hw->bus_speed = e1000_bus_speed_66; |
|
4794 break; |
|
4795 case E1000_STATUS_PCIX_SPEED_100: |
|
4796 hw->bus_speed = e1000_bus_speed_100; |
|
4797 break; |
|
4798 case E1000_STATUS_PCIX_SPEED_133: |
|
4799 hw->bus_speed = e1000_bus_speed_133; |
|
4800 break; |
|
4801 default: |
|
4802 hw->bus_speed = e1000_bus_speed_reserved; |
|
4803 break; |
|
4804 } |
|
4805 } |
|
4806 hw->bus_width = (status & E1000_STATUS_BUS64) ? |
|
4807 e1000_bus_width_64 : e1000_bus_width_32; |
|
4808 break; |
|
4809 } |
|
4810 } |
|
4811 |
|
4812 /** |
|
4813 * e1000_write_reg_io |
|
4814 * @hw: Struct containing variables accessed by shared code |
|
4815 * @offset: offset to write to |
|
4816 * @value: value to write |
|
4817 * |
|
4818 * Writes a value to one of the devices registers using port I/O (as opposed to |
|
4819 * memory mapped I/O). Only 82544 and newer devices support port I/O. |
|
4820 */ |
|
4821 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) |
|
4822 { |
|
4823 unsigned long io_addr = hw->io_base; |
|
4824 unsigned long io_data = hw->io_base + 4; |
|
4825 |
|
4826 e1000_io_write(hw, io_addr, offset); |
|
4827 e1000_io_write(hw, io_data, value); |
|
4828 } |
|
4829 |
|
4830 /** |
|
4831 * e1000_get_cable_length - Estimates the cable length. |
|
4832 * @hw: Struct containing variables accessed by shared code |
|
4833 * @min_length: The estimated minimum length |
|
4834 * @max_length: The estimated maximum length |
|
4835 * |
|
4836 * returns: - E1000_ERR_XXX |
|
4837 * E1000_SUCCESS |
|
4838 * |
|
4839 * This function always returns a ranged length (minimum & maximum). |
|
4840 * So for M88 phy's, this function interprets the one value returned from the |
|
4841 * register to the minimum and maximum range. |
|
4842 * For IGP phy's, the function calculates the range by the AGC registers. |
|
4843 */ |
|
4844 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, |
|
4845 u16 *max_length) |
|
4846 { |
|
4847 s32 ret_val; |
|
4848 u16 agc_value = 0; |
|
4849 u16 i, phy_data; |
|
4850 u16 cable_length; |
|
4851 |
|
4852 e_dbg("e1000_get_cable_length"); |
|
4853 |
|
4854 *min_length = *max_length = 0; |
|
4855 |
|
4856 /* Use old method for Phy older than IGP */ |
|
4857 if (hw->phy_type == e1000_phy_m88) { |
|
4858 |
|
4859 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
4860 &phy_data); |
|
4861 if (ret_val) |
|
4862 return ret_val; |
|
4863 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
|
4864 M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
|
4865 |
|
4866 /* Convert the enum value to ranged values */ |
|
4867 switch (cable_length) { |
|
4868 case e1000_cable_length_50: |
|
4869 *min_length = 0; |
|
4870 *max_length = e1000_igp_cable_length_50; |
|
4871 break; |
|
4872 case e1000_cable_length_50_80: |
|
4873 *min_length = e1000_igp_cable_length_50; |
|
4874 *max_length = e1000_igp_cable_length_80; |
|
4875 break; |
|
4876 case e1000_cable_length_80_110: |
|
4877 *min_length = e1000_igp_cable_length_80; |
|
4878 *max_length = e1000_igp_cable_length_110; |
|
4879 break; |
|
4880 case e1000_cable_length_110_140: |
|
4881 *min_length = e1000_igp_cable_length_110; |
|
4882 *max_length = e1000_igp_cable_length_140; |
|
4883 break; |
|
4884 case e1000_cable_length_140: |
|
4885 *min_length = e1000_igp_cable_length_140; |
|
4886 *max_length = e1000_igp_cable_length_170; |
|
4887 break; |
|
4888 default: |
|
4889 return -E1000_ERR_PHY; |
|
4890 break; |
|
4891 } |
|
4892 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
|
4893 u16 cur_agc_value; |
|
4894 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; |
|
4895 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
|
4896 { IGP01E1000_PHY_AGC_A, |
|
4897 IGP01E1000_PHY_AGC_B, |
|
4898 IGP01E1000_PHY_AGC_C, |
|
4899 IGP01E1000_PHY_AGC_D |
|
4900 }; |
|
4901 /* Read the AGC registers for all channels */ |
|
4902 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
4903 |
|
4904 ret_val = |
|
4905 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
|
4906 if (ret_val) |
|
4907 return ret_val; |
|
4908 |
|
4909 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; |
|
4910 |
|
4911 /* Value bound check. */ |
|
4912 if ((cur_agc_value >= |
|
4913 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) |
|
4914 || (cur_agc_value == 0)) |
|
4915 return -E1000_ERR_PHY; |
|
4916 |
|
4917 agc_value += cur_agc_value; |
|
4918 |
|
4919 /* Update minimal AGC value. */ |
|
4920 if (min_agc_value > cur_agc_value) |
|
4921 min_agc_value = cur_agc_value; |
|
4922 } |
|
4923 |
|
4924 /* Remove the minimal AGC result for length < 50m */ |
|
4925 if (agc_value < |
|
4926 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { |
|
4927 agc_value -= min_agc_value; |
|
4928 |
|
4929 /* Get the average length of the remaining 3 channels */ |
|
4930 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); |
|
4931 } else { |
|
4932 /* Get the average length of all the 4 channels. */ |
|
4933 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; |
|
4934 } |
|
4935 |
|
4936 /* Set the range of the calculated length. */ |
|
4937 *min_length = ((e1000_igp_cable_length_table[agc_value] - |
|
4938 IGP01E1000_AGC_RANGE) > 0) ? |
|
4939 (e1000_igp_cable_length_table[agc_value] - |
|
4940 IGP01E1000_AGC_RANGE) : 0; |
|
4941 *max_length = e1000_igp_cable_length_table[agc_value] + |
|
4942 IGP01E1000_AGC_RANGE; |
|
4943 } |
|
4944 |
|
4945 return E1000_SUCCESS; |
|
4946 } |
|
4947 |
|
4948 /** |
|
4949 * e1000_check_polarity - Check the cable polarity |
|
4950 * @hw: Struct containing variables accessed by shared code |
|
4951 * @polarity: output parameter : 0 - Polarity is not reversed |
|
4952 * 1 - Polarity is reversed. |
|
4953 * |
|
4954 * returns: - E1000_ERR_XXX |
|
4955 * E1000_SUCCESS |
|
4956 * |
|
4957 * For phy's older than IGP, this function simply reads the polarity bit in the |
|
4958 * Phy Status register. For IGP phy's, this bit is valid only if link speed is |
|
4959 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will |
|
4960 * return 0. If the link speed is 1000 Mbps the polarity status is in the |
|
4961 * IGP01E1000_PHY_PCS_INIT_REG. |
|
4962 */ |
|
4963 static s32 e1000_check_polarity(struct e1000_hw *hw, |
|
4964 e1000_rev_polarity *polarity) |
|
4965 { |
|
4966 s32 ret_val; |
|
4967 u16 phy_data; |
|
4968 |
|
4969 e_dbg("e1000_check_polarity"); |
|
4970 |
|
4971 if (hw->phy_type == e1000_phy_m88) { |
|
4972 /* return the Polarity bit in the Status register. */ |
|
4973 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
4974 &phy_data); |
|
4975 if (ret_val) |
|
4976 return ret_val; |
|
4977 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> |
|
4978 M88E1000_PSSR_REV_POLARITY_SHIFT) ? |
|
4979 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
|
4980 |
|
4981 } else if (hw->phy_type == e1000_phy_igp) { |
|
4982 /* Read the Status register to check the speed */ |
|
4983 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, |
|
4984 &phy_data); |
|
4985 if (ret_val) |
|
4986 return ret_val; |
|
4987 |
|
4988 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to |
|
4989 * find the polarity status */ |
|
4990 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
|
4991 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
4992 |
|
4993 /* Read the GIG initialization PCS register (0x00B4) */ |
|
4994 ret_val = |
|
4995 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, |
|
4996 &phy_data); |
|
4997 if (ret_val) |
|
4998 return ret_val; |
|
4999 |
|
5000 /* Check the polarity bits */ |
|
5001 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? |
|
5002 e1000_rev_polarity_reversed : |
|
5003 e1000_rev_polarity_normal; |
|
5004 } else { |
|
5005 /* For 10 Mbps, read the polarity bit in the status register. (for |
|
5006 * 100 Mbps this bit is always 0) */ |
|
5007 *polarity = |
|
5008 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? |
|
5009 e1000_rev_polarity_reversed : |
|
5010 e1000_rev_polarity_normal; |
|
5011 } |
|
5012 } |
|
5013 return E1000_SUCCESS; |
|
5014 } |
|
5015 |
|
5016 /** |
|
5017 * e1000_check_downshift - Check if Downshift occurred |
|
5018 * @hw: Struct containing variables accessed by shared code |
|
5019 * @downshift: output parameter : 0 - No Downshift occurred. |
|
5020 * 1 - Downshift occurred. |
|
5021 * |
|
5022 * returns: - E1000_ERR_XXX |
|
5023 * E1000_SUCCESS |
|
5024 * |
|
5025 * For phy's older than IGP, this function reads the Downshift bit in the Phy |
|
5026 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the |
|
5027 * Link Health register. In IGP this bit is latched high, so the driver must |
|
5028 * read it immediately after link is established. |
|
5029 */ |
|
5030 static s32 e1000_check_downshift(struct e1000_hw *hw) |
|
5031 { |
|
5032 s32 ret_val; |
|
5033 u16 phy_data; |
|
5034 |
|
5035 e_dbg("e1000_check_downshift"); |
|
5036 |
|
5037 if (hw->phy_type == e1000_phy_igp) { |
|
5038 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
|
5039 &phy_data); |
|
5040 if (ret_val) |
|
5041 return ret_val; |
|
5042 |
|
5043 hw->speed_downgraded = |
|
5044 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; |
|
5045 } else if (hw->phy_type == e1000_phy_m88) { |
|
5046 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
5047 &phy_data); |
|
5048 if (ret_val) |
|
5049 return ret_val; |
|
5050 |
|
5051 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> |
|
5052 M88E1000_PSSR_DOWNSHIFT_SHIFT; |
|
5053 } |
|
5054 |
|
5055 return E1000_SUCCESS; |
|
5056 } |
|
5057 |
|
5058 /** |
|
5059 * e1000_config_dsp_after_link_change |
|
5060 * @hw: Struct containing variables accessed by shared code |
|
5061 * @link_up: was link up at the time this was called |
|
5062 * |
|
5063 * returns: - E1000_ERR_PHY if fail to read/write the PHY |
|
5064 * E1000_SUCCESS at any other case. |
|
5065 * |
|
5066 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a |
|
5067 * gigabit link is achieved to improve link quality. |
|
5068 */ |
|
5069 |
|
5070 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) |
|
5071 { |
|
5072 s32 ret_val; |
|
5073 u16 phy_data, phy_saved_data, speed, duplex, i; |
|
5074 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
|
5075 { IGP01E1000_PHY_AGC_PARAM_A, |
|
5076 IGP01E1000_PHY_AGC_PARAM_B, |
|
5077 IGP01E1000_PHY_AGC_PARAM_C, |
|
5078 IGP01E1000_PHY_AGC_PARAM_D |
|
5079 }; |
|
5080 u16 min_length, max_length; |
|
5081 |
|
5082 e_dbg("e1000_config_dsp_after_link_change"); |
|
5083 |
|
5084 if (hw->phy_type != e1000_phy_igp) |
|
5085 return E1000_SUCCESS; |
|
5086 |
|
5087 if (link_up) { |
|
5088 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
5089 if (ret_val) { |
|
5090 e_dbg("Error getting link speed and duplex\n"); |
|
5091 return ret_val; |
|
5092 } |
|
5093 |
|
5094 if (speed == SPEED_1000) { |
|
5095 |
|
5096 ret_val = |
|
5097 e1000_get_cable_length(hw, &min_length, |
|
5098 &max_length); |
|
5099 if (ret_val) |
|
5100 return ret_val; |
|
5101 |
|
5102 if ((hw->dsp_config_state == e1000_dsp_config_enabled) |
|
5103 && min_length >= e1000_igp_cable_length_50) { |
|
5104 |
|
5105 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
5106 ret_val = |
|
5107 e1000_read_phy_reg(hw, |
|
5108 dsp_reg_array[i], |
|
5109 &phy_data); |
|
5110 if (ret_val) |
|
5111 return ret_val; |
|
5112 |
|
5113 phy_data &= |
|
5114 ~IGP01E1000_PHY_EDAC_MU_INDEX; |
|
5115 |
|
5116 ret_val = |
|
5117 e1000_write_phy_reg(hw, |
|
5118 dsp_reg_array |
|
5119 [i], phy_data); |
|
5120 if (ret_val) |
|
5121 return ret_val; |
|
5122 } |
|
5123 hw->dsp_config_state = |
|
5124 e1000_dsp_config_activated; |
|
5125 } |
|
5126 |
|
5127 if ((hw->ffe_config_state == e1000_ffe_config_enabled) |
|
5128 && (min_length < e1000_igp_cable_length_50)) { |
|
5129 |
|
5130 u16 ffe_idle_err_timeout = |
|
5131 FFE_IDLE_ERR_COUNT_TIMEOUT_20; |
|
5132 u32 idle_errs = 0; |
|
5133 |
|
5134 /* clear previous idle error counts */ |
|
5135 ret_val = |
|
5136 e1000_read_phy_reg(hw, PHY_1000T_STATUS, |
|
5137 &phy_data); |
|
5138 if (ret_val) |
|
5139 return ret_val; |
|
5140 |
|
5141 for (i = 0; i < ffe_idle_err_timeout; i++) { |
|
5142 udelay(1000); |
|
5143 ret_val = |
|
5144 e1000_read_phy_reg(hw, |
|
5145 PHY_1000T_STATUS, |
|
5146 &phy_data); |
|
5147 if (ret_val) |
|
5148 return ret_val; |
|
5149 |
|
5150 idle_errs += |
|
5151 (phy_data & |
|
5152 SR_1000T_IDLE_ERROR_CNT); |
|
5153 if (idle_errs > |
|
5154 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) |
|
5155 { |
|
5156 hw->ffe_config_state = |
|
5157 e1000_ffe_config_active; |
|
5158 |
|
5159 ret_val = |
|
5160 e1000_write_phy_reg(hw, |
|
5161 IGP01E1000_PHY_DSP_FFE, |
|
5162 IGP01E1000_PHY_DSP_FFE_CM_CP); |
|
5163 if (ret_val) |
|
5164 return ret_val; |
|
5165 break; |
|
5166 } |
|
5167 |
|
5168 if (idle_errs) |
|
5169 ffe_idle_err_timeout = |
|
5170 FFE_IDLE_ERR_COUNT_TIMEOUT_100; |
|
5171 } |
|
5172 } |
|
5173 } |
|
5174 } else { |
|
5175 if (hw->dsp_config_state == e1000_dsp_config_activated) { |
|
5176 /* Save off the current value of register 0x2F5B to be restored at |
|
5177 * the end of the routines. */ |
|
5178 ret_val = |
|
5179 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
|
5180 |
|
5181 if (ret_val) |
|
5182 return ret_val; |
|
5183 |
|
5184 /* Disable the PHY transmitter */ |
|
5185 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
|
5186 |
|
5187 if (ret_val) |
|
5188 return ret_val; |
|
5189 |
|
5190 mdelay(20); |
|
5191 |
|
5192 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
5193 IGP01E1000_IEEE_FORCE_GIGA); |
|
5194 if (ret_val) |
|
5195 return ret_val; |
|
5196 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
5197 ret_val = |
|
5198 e1000_read_phy_reg(hw, dsp_reg_array[i], |
|
5199 &phy_data); |
|
5200 if (ret_val) |
|
5201 return ret_val; |
|
5202 |
|
5203 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
|
5204 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; |
|
5205 |
|
5206 ret_val = |
|
5207 e1000_write_phy_reg(hw, dsp_reg_array[i], |
|
5208 phy_data); |
|
5209 if (ret_val) |
|
5210 return ret_val; |
|
5211 } |
|
5212 |
|
5213 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
5214 IGP01E1000_IEEE_RESTART_AUTONEG); |
|
5215 if (ret_val) |
|
5216 return ret_val; |
|
5217 |
|
5218 mdelay(20); |
|
5219 |
|
5220 /* Now enable the transmitter */ |
|
5221 ret_val = |
|
5222 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
|
5223 |
|
5224 if (ret_val) |
|
5225 return ret_val; |
|
5226 |
|
5227 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
5228 } |
|
5229 |
|
5230 if (hw->ffe_config_state == e1000_ffe_config_active) { |
|
5231 /* Save off the current value of register 0x2F5B to be restored at |
|
5232 * the end of the routines. */ |
|
5233 ret_val = |
|
5234 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
|
5235 |
|
5236 if (ret_val) |
|
5237 return ret_val; |
|
5238 |
|
5239 /* Disable the PHY transmitter */ |
|
5240 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
|
5241 |
|
5242 if (ret_val) |
|
5243 return ret_val; |
|
5244 |
|
5245 mdelay(20); |
|
5246 |
|
5247 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
5248 IGP01E1000_IEEE_FORCE_GIGA); |
|
5249 if (ret_val) |
|
5250 return ret_val; |
|
5251 ret_val = |
|
5252 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, |
|
5253 IGP01E1000_PHY_DSP_FFE_DEFAULT); |
|
5254 if (ret_val) |
|
5255 return ret_val; |
|
5256 |
|
5257 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
5258 IGP01E1000_IEEE_RESTART_AUTONEG); |
|
5259 if (ret_val) |
|
5260 return ret_val; |
|
5261 |
|
5262 mdelay(20); |
|
5263 |
|
5264 /* Now enable the transmitter */ |
|
5265 ret_val = |
|
5266 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
|
5267 |
|
5268 if (ret_val) |
|
5269 return ret_val; |
|
5270 |
|
5271 hw->ffe_config_state = e1000_ffe_config_enabled; |
|
5272 } |
|
5273 } |
|
5274 return E1000_SUCCESS; |
|
5275 } |
|
5276 |
|
5277 /** |
|
5278 * e1000_set_phy_mode - Set PHY to class A mode |
|
5279 * @hw: Struct containing variables accessed by shared code |
|
5280 * |
|
5281 * Assumes the following operations will follow to enable the new class mode. |
|
5282 * 1. Do a PHY soft reset |
|
5283 * 2. Restart auto-negotiation or force link. |
|
5284 */ |
|
5285 static s32 e1000_set_phy_mode(struct e1000_hw *hw) |
|
5286 { |
|
5287 s32 ret_val; |
|
5288 u16 eeprom_data; |
|
5289 |
|
5290 e_dbg("e1000_set_phy_mode"); |
|
5291 |
|
5292 if ((hw->mac_type == e1000_82545_rev_3) && |
|
5293 (hw->media_type == e1000_media_type_copper)) { |
|
5294 ret_val = |
|
5295 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, |
|
5296 &eeprom_data); |
|
5297 if (ret_val) { |
|
5298 return ret_val; |
|
5299 } |
|
5300 |
|
5301 if ((eeprom_data != EEPROM_RESERVED_WORD) && |
|
5302 (eeprom_data & EEPROM_PHY_CLASS_A)) { |
|
5303 ret_val = |
|
5304 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, |
|
5305 0x000B); |
|
5306 if (ret_val) |
|
5307 return ret_val; |
|
5308 ret_val = |
|
5309 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, |
|
5310 0x8104); |
|
5311 if (ret_val) |
|
5312 return ret_val; |
|
5313 |
|
5314 hw->phy_reset_disable = false; |
|
5315 } |
|
5316 } |
|
5317 |
|
5318 return E1000_SUCCESS; |
|
5319 } |
|
5320 |
|
5321 /** |
|
5322 * e1000_set_d3_lplu_state - set d3 link power state |
|
5323 * @hw: Struct containing variables accessed by shared code |
|
5324 * @active: true to enable lplu false to disable lplu. |
|
5325 * |
|
5326 * This function sets the lplu state according to the active flag. When |
|
5327 * activating lplu this function also disables smart speed and vise versa. |
|
5328 * lplu will not be activated unless the device autonegotiation advertisement |
|
5329 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
|
5330 * |
|
5331 * returns: - E1000_ERR_PHY if fail to read/write the PHY |
|
5332 * E1000_SUCCESS at any other case. |
|
5333 */ |
|
5334 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
|
5335 { |
|
5336 s32 ret_val; |
|
5337 u16 phy_data; |
|
5338 e_dbg("e1000_set_d3_lplu_state"); |
|
5339 |
|
5340 if (hw->phy_type != e1000_phy_igp) |
|
5341 return E1000_SUCCESS; |
|
5342 |
|
5343 /* During driver activity LPLU should not be used or it will attain link |
|
5344 * from the lowest speeds starting from 10Mbps. The capability is used for |
|
5345 * Dx transitions and states */ |
|
5346 if (hw->mac_type == e1000_82541_rev_2 |
|
5347 || hw->mac_type == e1000_82547_rev_2) { |
|
5348 ret_val = |
|
5349 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); |
|
5350 if (ret_val) |
|
5351 return ret_val; |
|
5352 } |
|
5353 |
|
5354 if (!active) { |
|
5355 if (hw->mac_type == e1000_82541_rev_2 || |
|
5356 hw->mac_type == e1000_82547_rev_2) { |
|
5357 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; |
|
5358 ret_val = |
|
5359 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
5360 phy_data); |
|
5361 if (ret_val) |
|
5362 return ret_val; |
|
5363 } |
|
5364 |
|
5365 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
|
5366 * Dx states where the power conservation is most important. During |
|
5367 * driver activity we should enable SmartSpeed, so performance is |
|
5368 * maintained. */ |
|
5369 if (hw->smart_speed == e1000_smart_speed_on) { |
|
5370 ret_val = |
|
5371 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5372 &phy_data); |
|
5373 if (ret_val) |
|
5374 return ret_val; |
|
5375 |
|
5376 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
5377 ret_val = |
|
5378 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5379 phy_data); |
|
5380 if (ret_val) |
|
5381 return ret_val; |
|
5382 } else if (hw->smart_speed == e1000_smart_speed_off) { |
|
5383 ret_val = |
|
5384 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5385 &phy_data); |
|
5386 if (ret_val) |
|
5387 return ret_val; |
|
5388 |
|
5389 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
5390 ret_val = |
|
5391 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5392 phy_data); |
|
5393 if (ret_val) |
|
5394 return ret_val; |
|
5395 } |
|
5396 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) |
|
5397 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) |
|
5398 || (hw->autoneg_advertised == |
|
5399 AUTONEG_ADVERTISE_10_100_ALL)) { |
|
5400 |
|
5401 if (hw->mac_type == e1000_82541_rev_2 || |
|
5402 hw->mac_type == e1000_82547_rev_2) { |
|
5403 phy_data |= IGP01E1000_GMII_FLEX_SPD; |
|
5404 ret_val = |
|
5405 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
5406 phy_data); |
|
5407 if (ret_val) |
|
5408 return ret_val; |
|
5409 } |
|
5410 |
|
5411 /* When LPLU is enabled we should disable SmartSpeed */ |
|
5412 ret_val = |
|
5413 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5414 &phy_data); |
|
5415 if (ret_val) |
|
5416 return ret_val; |
|
5417 |
|
5418 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
5419 ret_val = |
|
5420 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5421 phy_data); |
|
5422 if (ret_val) |
|
5423 return ret_val; |
|
5424 |
|
5425 } |
|
5426 return E1000_SUCCESS; |
|
5427 } |
|
5428 |
|
5429 /** |
|
5430 * e1000_set_vco_speed |
|
5431 * @hw: Struct containing variables accessed by shared code |
|
5432 * |
|
5433 * Change VCO speed register to improve Bit Error Rate performance of SERDES. |
|
5434 */ |
|
5435 static s32 e1000_set_vco_speed(struct e1000_hw *hw) |
|
5436 { |
|
5437 s32 ret_val; |
|
5438 u16 default_page = 0; |
|
5439 u16 phy_data; |
|
5440 |
|
5441 e_dbg("e1000_set_vco_speed"); |
|
5442 |
|
5443 switch (hw->mac_type) { |
|
5444 case e1000_82545_rev_3: |
|
5445 case e1000_82546_rev_3: |
|
5446 break; |
|
5447 default: |
|
5448 return E1000_SUCCESS; |
|
5449 } |
|
5450 |
|
5451 /* Set PHY register 30, page 5, bit 8 to 0 */ |
|
5452 |
|
5453 ret_val = |
|
5454 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); |
|
5455 if (ret_val) |
|
5456 return ret_val; |
|
5457 |
|
5458 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); |
|
5459 if (ret_val) |
|
5460 return ret_val; |
|
5461 |
|
5462 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
|
5463 if (ret_val) |
|
5464 return ret_val; |
|
5465 |
|
5466 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; |
|
5467 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
|
5468 if (ret_val) |
|
5469 return ret_val; |
|
5470 |
|
5471 /* Set PHY register 30, page 4, bit 11 to 1 */ |
|
5472 |
|
5473 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); |
|
5474 if (ret_val) |
|
5475 return ret_val; |
|
5476 |
|
5477 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
|
5478 if (ret_val) |
|
5479 return ret_val; |
|
5480 |
|
5481 phy_data |= M88E1000_PHY_VCO_REG_BIT11; |
|
5482 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
|
5483 if (ret_val) |
|
5484 return ret_val; |
|
5485 |
|
5486 ret_val = |
|
5487 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); |
|
5488 if (ret_val) |
|
5489 return ret_val; |
|
5490 |
|
5491 return E1000_SUCCESS; |
|
5492 } |
|
5493 |
|
5494 |
|
5495 /** |
|
5496 * e1000_enable_mng_pass_thru - check for bmc pass through |
|
5497 * @hw: Struct containing variables accessed by shared code |
|
5498 * |
|
5499 * Verifies the hardware needs to allow ARPs to be processed by the host |
|
5500 * returns: - true/false |
|
5501 */ |
|
5502 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) |
|
5503 { |
|
5504 u32 manc; |
|
5505 |
|
5506 if (hw->asf_firmware_present) { |
|
5507 manc = er32(MANC); |
|
5508 |
|
5509 if (!(manc & E1000_MANC_RCV_TCO_EN) || |
|
5510 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
|
5511 return false; |
|
5512 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) |
|
5513 return true; |
|
5514 } |
|
5515 return false; |
|
5516 } |
|
5517 |
|
5518 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) |
|
5519 { |
|
5520 s32 ret_val; |
|
5521 u16 mii_status_reg; |
|
5522 u16 i; |
|
5523 |
|
5524 /* Polarity reversal workaround for forced 10F/10H links. */ |
|
5525 |
|
5526 /* Disable the transmitter on the PHY */ |
|
5527 |
|
5528 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
|
5529 if (ret_val) |
|
5530 return ret_val; |
|
5531 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); |
|
5532 if (ret_val) |
|
5533 return ret_val; |
|
5534 |
|
5535 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
|
5536 if (ret_val) |
|
5537 return ret_val; |
|
5538 |
|
5539 /* This loop will early-out if the NO link condition has been met. */ |
|
5540 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
5541 /* Read the MII Status Register and wait for Link Status bit |
|
5542 * to be clear. |
|
5543 */ |
|
5544 |
|
5545 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
5546 if (ret_val) |
|
5547 return ret_val; |
|
5548 |
|
5549 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
5550 if (ret_val) |
|
5551 return ret_val; |
|
5552 |
|
5553 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) |
|
5554 break; |
|
5555 mdelay(100); |
|
5556 } |
|
5557 |
|
5558 /* Recommended delay time after link has been lost */ |
|
5559 mdelay(1000); |
|
5560 |
|
5561 /* Now we will re-enable th transmitter on the PHY */ |
|
5562 |
|
5563 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
|
5564 if (ret_val) |
|
5565 return ret_val; |
|
5566 mdelay(50); |
|
5567 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); |
|
5568 if (ret_val) |
|
5569 return ret_val; |
|
5570 mdelay(50); |
|
5571 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); |
|
5572 if (ret_val) |
|
5573 return ret_val; |
|
5574 mdelay(50); |
|
5575 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); |
|
5576 if (ret_val) |
|
5577 return ret_val; |
|
5578 |
|
5579 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
|
5580 if (ret_val) |
|
5581 return ret_val; |
|
5582 |
|
5583 /* This loop will early-out if the link condition has been met. */ |
|
5584 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
5585 /* Read the MII Status Register and wait for Link Status bit |
|
5586 * to be set. |
|
5587 */ |
|
5588 |
|
5589 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
5590 if (ret_val) |
|
5591 return ret_val; |
|
5592 |
|
5593 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
5594 if (ret_val) |
|
5595 return ret_val; |
|
5596 |
|
5597 if (mii_status_reg & MII_SR_LINK_STATUS) |
|
5598 break; |
|
5599 mdelay(100); |
|
5600 } |
|
5601 return E1000_SUCCESS; |
|
5602 } |
|
5603 |
|
5604 /** |
|
5605 * e1000_get_auto_rd_done |
|
5606 * @hw: Struct containing variables accessed by shared code |
|
5607 * |
|
5608 * Check for EEPROM Auto Read bit done. |
|
5609 * returns: - E1000_ERR_RESET if fail to reset MAC |
|
5610 * E1000_SUCCESS at any other case. |
|
5611 */ |
|
5612 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) |
|
5613 { |
|
5614 e_dbg("e1000_get_auto_rd_done"); |
|
5615 msleep(5); |
|
5616 return E1000_SUCCESS; |
|
5617 } |
|
5618 |
|
5619 /** |
|
5620 * e1000_get_phy_cfg_done |
|
5621 * @hw: Struct containing variables accessed by shared code |
|
5622 * |
|
5623 * Checks if the PHY configuration is done |
|
5624 * returns: - E1000_ERR_RESET if fail to reset MAC |
|
5625 * E1000_SUCCESS at any other case. |
|
5626 */ |
|
5627 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) |
|
5628 { |
|
5629 e_dbg("e1000_get_phy_cfg_done"); |
|
5630 mdelay(10); |
|
5631 return E1000_SUCCESS; |
|
5632 } |