1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2006 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27  */

    28 

    29 /* e1000_hw.c

    30  * Shared functions for accessing and configuring the MAC

    31  */

    32 

    33 #include "e1000-2.6.35-ethercat.h"

    34 

    35 static s32 e1000_check_downshift(struct e1000_hw *hw);

    36 static s32 e1000_check_polarity(struct e1000_hw *hw,

    37 				e1000_rev_polarity *polarity);

    38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39 static void e1000_clear_vfta(struct e1000_hw *hw);

    40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41 					      bool link_up);

    42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46 				  u16 *max_length);

    47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48 static s32 e1000_id_led_init(struct e1000_hw *hw);

    49 static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51 				  struct e1000_phy_info *phy_info);

    52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53 				  struct e1000_phy_info *phy_info);

    54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55 static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57 static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58 static void e1000_phy_init_script(struct e1000_hw *hw);

    59 static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70 				  u16 words, u16 *data);

    71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72 					u16 words, u16 *data);

    73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78 				  u16 phy_data);

    79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    80 				 u16 *phy_data);

    81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83 static void e1000_release_eeprom(struct e1000_hw *hw);

    84 static void e1000_standby_eeprom(struct e1000_hw *hw);

    85 static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87 static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89 				u16 *data);

    90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91 				 u16 *data);

    92 

    93 /* IGP cable length table */

    94 static const

    95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96 	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    97 	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98 	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99 	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100 	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101 	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102 	    100,

   103 	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104 	    110, 110,

   105 	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106 	    120, 120

   107 };

   108 

   109 static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110 

   111 /**

   112  * e1000_set_phy_type - Set the phy type member in the hw struct.

   113  * @hw: Struct containing variables accessed by shared code

   114  */

   115 static s32 e1000_set_phy_type(struct e1000_hw *hw)

   116 {

   117 	e_dbg("e1000_set_phy_type");

   118 

   119 	if (hw->mac_type == e1000_undefined)

   120 		return -E1000_ERR_PHY_TYPE;

   121 

   122 	switch (hw->phy_id) {

   123 	case M88E1000_E_PHY_ID:

   124 	case M88E1000_I_PHY_ID:

   125 	case M88E1011_I_PHY_ID:

   126 	case M88E1111_I_PHY_ID:

   127 		hw->phy_type = e1000_phy_m88;

   128 		break;

   129 	case IGP01E1000_I_PHY_ID:

   130 		if (hw->mac_type == e1000_82541 ||

   131 		    hw->mac_type == e1000_82541_rev_2 ||

   132 		    hw->mac_type == e1000_82547 ||

   133 		    hw->mac_type == e1000_82547_rev_2) {

   134 			hw->phy_type = e1000_phy_igp;

   135 			break;

   136 		}

   137 	default:

   138 		/* Should never have loaded on this device */

   139 		hw->phy_type = e1000_phy_undefined;

   140 		return -E1000_ERR_PHY_TYPE;

   141 	}

   142 

   143 	return E1000_SUCCESS;

   144 }

   145 

   146 /**

   147  * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   148  * @hw: Struct containing variables accessed by shared code

   149  */

   150 static void e1000_phy_init_script(struct e1000_hw *hw)

   151 {

   152 	u32 ret_val __attribute__ ((unused));

   153 	u16 phy_saved_data;

   154 

   155 	e_dbg("e1000_phy_init_script");

   156 

   157 	if (hw->phy_init_script) {

   158 		msleep(20);

   159 

   160 		/* Save off the current value of register 0x2F5B to be restored at

   161 		 * the end of this routine. */

   162 		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   163 

   164 		/* Disabled the PHY transmitter */

   165 		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   166 		msleep(20);

   167 

   168 		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   169 		msleep(5);

   170 

   171 		switch (hw->mac_type) {

   172 		case e1000_82541:

   173 		case e1000_82547:

   174 			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   175 			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   176 			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   177 			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   178 			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   179 			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   180 			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   181 			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   182 			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   183 			break;

   184 

   185 		case e1000_82541_rev_2:

   186 		case e1000_82547_rev_2:

   187 			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   188 			break;

   189 		default:

   190 			break;

   191 		}

   192 

   193 		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   194 		msleep(20);

   195 

   196 		/* Now enable the transmitter */

   197 		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   198 

   199 		if (hw->mac_type == e1000_82547) {

   200 			u16 fused, fine, coarse;

   201 

   202 			/* Move to analog registers page */

   203 			e1000_read_phy_reg(hw,

   204 					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   205 					   &fused);

   206 

   207 			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   208 				e1000_read_phy_reg(hw,

   209 						   IGP01E1000_ANALOG_FUSE_STATUS,

   210 						   &fused);

   211 

   212 				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   213 				coarse =

   214 				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   215 

   216 				if (coarse >

   217 				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   218 					coarse -=

   219 					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   220 					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   221 				} else if (coarse ==

   222 					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   223 					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   224 

   225 				fused =

   226 				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   227 				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   228 				    (coarse &

   229 				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   230 

   231 				e1000_write_phy_reg(hw,

   232 						    IGP01E1000_ANALOG_FUSE_CONTROL,

   233 						    fused);

   234 				e1000_write_phy_reg(hw,

   235 						    IGP01E1000_ANALOG_FUSE_BYPASS,

   236 						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   237 			}

   238 		}

   239 	}

   240 }

   241 

   242 /**

   243  * e1000_set_mac_type - Set the mac type member in the hw struct.

   244  * @hw: Struct containing variables accessed by shared code

   245  */

   246 s32 e1000_set_mac_type(struct e1000_hw *hw)

   247 {

   248 	e_dbg("e1000_set_mac_type");

   249 

   250 	switch (hw->device_id) {

   251 	case E1000_DEV_ID_82542:

   252 		switch (hw->revision_id) {

   253 		case E1000_82542_2_0_REV_ID:

   254 			hw->mac_type = e1000_82542_rev2_0;

   255 			break;

   256 		case E1000_82542_2_1_REV_ID:

   257 			hw->mac_type = e1000_82542_rev2_1;

   258 			break;

   259 		default:

   260 			/* Invalid 82542 revision ID */

   261 			return -E1000_ERR_MAC_TYPE;

   262 		}

   263 		break;

   264 	case E1000_DEV_ID_82543GC_FIBER:

   265 	case E1000_DEV_ID_82543GC_COPPER:

   266 		hw->mac_type = e1000_82543;

   267 		break;

   268 	case E1000_DEV_ID_82544EI_COPPER:

   269 	case E1000_DEV_ID_82544EI_FIBER:

   270 	case E1000_DEV_ID_82544GC_COPPER:

   271 	case E1000_DEV_ID_82544GC_LOM:

   272 		hw->mac_type = e1000_82544;

   273 		break;

   274 	case E1000_DEV_ID_82540EM:

   275 	case E1000_DEV_ID_82540EM_LOM:

   276 	case E1000_DEV_ID_82540EP:

   277 	case E1000_DEV_ID_82540EP_LOM:

   278 	case E1000_DEV_ID_82540EP_LP:

   279 		hw->mac_type = e1000_82540;

   280 		break;

   281 	case E1000_DEV_ID_82545EM_COPPER:

   282 	case E1000_DEV_ID_82545EM_FIBER:

   283 		hw->mac_type = e1000_82545;

   284 		break;

   285 	case E1000_DEV_ID_82545GM_COPPER:

   286 	case E1000_DEV_ID_82545GM_FIBER:

   287 	case E1000_DEV_ID_82545GM_SERDES:

   288 		hw->mac_type = e1000_82545_rev_3;

   289 		break;

   290 	case E1000_DEV_ID_82546EB_COPPER:

   291 	case E1000_DEV_ID_82546EB_FIBER:

   292 	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   293 		hw->mac_type = e1000_82546;

   294 		break;

   295 	case E1000_DEV_ID_82546GB_COPPER:

   296 	case E1000_DEV_ID_82546GB_FIBER:

   297 	case E1000_DEV_ID_82546GB_SERDES:

   298 	case E1000_DEV_ID_82546GB_PCIE:

   299 	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   300 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   301 		hw->mac_type = e1000_82546_rev_3;

   302 		break;

   303 	case E1000_DEV_ID_82541EI:

   304 	case E1000_DEV_ID_82541EI_MOBILE:

   305 	case E1000_DEV_ID_82541ER_LOM:

   306 		hw->mac_type = e1000_82541;

   307 		break;

   308 	case E1000_DEV_ID_82541ER:

   309 	case E1000_DEV_ID_82541GI:

   310 	case E1000_DEV_ID_82541GI_LF:

   311 	case E1000_DEV_ID_82541GI_MOBILE:

   312 		hw->mac_type = e1000_82541_rev_2;

   313 		break;

   314 	case E1000_DEV_ID_82547EI:

   315 	case E1000_DEV_ID_82547EI_MOBILE:

   316 		hw->mac_type = e1000_82547;

   317 		break;

   318 	case E1000_DEV_ID_82547GI:

   319 		hw->mac_type = e1000_82547_rev_2;

   320 		break;

   321 	default:

   322 		/* Should never have loaded on this device */

   323 		return -E1000_ERR_MAC_TYPE;

   324 	}

   325 

   326 	switch (hw->mac_type) {

   327 	case e1000_82541:

   328 	case e1000_82547:

   329 	case e1000_82541_rev_2:

   330 	case e1000_82547_rev_2:

   331 		hw->asf_firmware_present = true;

   332 		break;

   333 	default:

   334 		break;

   335 	}

   336 

   337 	/* The 82543 chip does not count tx_carrier_errors properly in

   338 	 * FD mode

   339 	 */

   340 	if (hw->mac_type == e1000_82543)

   341 		hw->bad_tx_carr_stats_fd = true;

   342 

   343 	if (hw->mac_type > e1000_82544)

   344 		hw->has_smbus = true;

   345 

   346 	return E1000_SUCCESS;

   347 }

   348 

   349 /**

   350  * e1000_set_media_type - Set media type and TBI compatibility.

   351  * @hw: Struct containing variables accessed by shared code

   352  */

   353 void e1000_set_media_type(struct e1000_hw *hw)

   354 {

   355 	u32 status;

   356 

   357 	e_dbg("e1000_set_media_type");

   358 

   359 	if (hw->mac_type != e1000_82543) {

   360 		/* tbi_compatibility is only valid on 82543 */

   361 		hw->tbi_compatibility_en = false;

   362 	}

   363 

   364 	switch (hw->device_id) {

   365 	case E1000_DEV_ID_82545GM_SERDES:

   366 	case E1000_DEV_ID_82546GB_SERDES:

   367 		hw->media_type = e1000_media_type_internal_serdes;

   368 		break;

   369 	default:

   370 		switch (hw->mac_type) {

   371 		case e1000_82542_rev2_0:

   372 		case e1000_82542_rev2_1:

   373 			hw->media_type = e1000_media_type_fiber;

   374 			break;

   375 		default:

   376 			status = er32(STATUS);

   377 			if (status & E1000_STATUS_TBIMODE) {

   378 				hw->media_type = e1000_media_type_fiber;

   379 				/* tbi_compatibility not valid on fiber */

   380 				hw->tbi_compatibility_en = false;

   381 			} else {

   382 				hw->media_type = e1000_media_type_copper;

   383 			}

   384 			break;

   385 		}

   386 	}

   387 }

   388 

   389 /**

   390  * e1000_reset_hw: reset the hardware completely

   391  * @hw: Struct containing variables accessed by shared code

   392  *

   393  * Reset the transmit and receive units; mask and clear all interrupts.

   394  */

   395 s32 e1000_reset_hw(struct e1000_hw *hw)

   396 {

   397 	u32 ctrl;

   398 	u32 ctrl_ext;

   399 	u32 icr __attribute__ ((unused));

   400 	u32 manc;

   401 	u32 led_ctrl;

   402 	s32 ret_val;

   403 

   404 	e_dbg("e1000_reset_hw");

   405 

   406 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   407 	if (hw->mac_type == e1000_82542_rev2_0) {

   408 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   409 		e1000_pci_clear_mwi(hw);

   410 	}

   411 

   412 	/* Clear interrupt mask to stop board from generating interrupts */

   413 	e_dbg("Masking off all interrupts\n");

   414 	ew32(IMC, 0xffffffff);

   415 

   416 	/* Disable the Transmit and Receive units.  Then delay to allow

   417 	 * any pending transactions to complete before we hit the MAC with

   418 	 * the global reset.

   419 	 */

   420 	ew32(RCTL, 0);

   421 	ew32(TCTL, E1000_TCTL_PSP);

   422 	E1000_WRITE_FLUSH();

   423 

   424 	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   425 	hw->tbi_compatibility_on = false;

   426 

   427 	/* Delay to allow any outstanding PCI transactions to complete before

   428 	 * resetting the device

   429 	 */

   430 	msleep(10);

   431 

   432 	ctrl = er32(CTRL);

   433 

   434 	/* Must reset the PHY before resetting the MAC */

   435 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   436 		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   437 		msleep(5);

   438 	}

   439 

   440 	/* Issue a global reset to the MAC.  This will reset the chip's

   441 	 * transmit, receive, DMA, and link units.  It will not effect

   442 	 * the current PCI configuration.  The global reset bit is self-

   443 	 * clearing, and should clear within a microsecond.

   444 	 */

   445 	e_dbg("Issuing a global reset to MAC\n");

   446 

   447 	switch (hw->mac_type) {

   448 	case e1000_82544:

   449 	case e1000_82540:

   450 	case e1000_82545:

   451 	case e1000_82546:

   452 	case e1000_82541:

   453 	case e1000_82541_rev_2:

   454 		/* These controllers can't ack the 64-bit write when issuing the

   455 		 * reset, so use IO-mapping as a workaround to issue the reset */

   456 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   457 		break;

   458 	case e1000_82545_rev_3:

   459 	case e1000_82546_rev_3:

   460 		/* Reset is performed on a shadow of the control register */

   461 		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   462 		break;

   463 	default:

   464 		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   465 		break;

   466 	}

   467 

   468 	/* After MAC reset, force reload of EEPROM to restore power-on settings to

   469 	 * device.  Later controllers reload the EEPROM automatically, so just wait

   470 	 * for reload to complete.

   471 	 */

   472 	switch (hw->mac_type) {

   473 	case e1000_82542_rev2_0:

   474 	case e1000_82542_rev2_1:

   475 	case e1000_82543:

   476 	case e1000_82544:

   477 		/* Wait for reset to complete */

   478 		udelay(10);

   479 		ctrl_ext = er32(CTRL_EXT);

   480 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   481 		ew32(CTRL_EXT, ctrl_ext);

   482 		E1000_WRITE_FLUSH();

   483 		/* Wait for EEPROM reload */

   484 		msleep(2);

   485 		break;

   486 	case e1000_82541:

   487 	case e1000_82541_rev_2:

   488 	case e1000_82547:

   489 	case e1000_82547_rev_2:

   490 		/* Wait for EEPROM reload */

   491 		msleep(20);

   492 		break;

   493 	default:

   494 		/* Auto read done will delay 5ms or poll based on mac type */

   495 		ret_val = e1000_get_auto_rd_done(hw);

   496 		if (ret_val)

   497 			return ret_val;

   498 		break;

   499 	}

   500 

   501 	/* Disable HW ARPs on ASF enabled adapters */

   502 	if (hw->mac_type >= e1000_82540) {

   503 		manc = er32(MANC);

   504 		manc &= ~(E1000_MANC_ARP_EN);

   505 		ew32(MANC, manc);

   506 	}

   507 

   508 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   509 		e1000_phy_init_script(hw);

   510 

   511 		/* Configure activity LED after PHY reset */

   512 		led_ctrl = er32(LEDCTL);

   513 		led_ctrl &= IGP_ACTIVITY_LED_MASK;

   514 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   515 		ew32(LEDCTL, led_ctrl);

   516 	}

   517 

   518 	/* Clear interrupt mask to stop board from generating interrupts */

   519 	e_dbg("Masking off all interrupts\n");

   520 	ew32(IMC, 0xffffffff);

   521 

   522 	/* Clear any pending interrupt events. */

   523 	icr = er32(ICR);

   524 

   525 	/* If MWI was previously enabled, reenable it. */

   526 	if (hw->mac_type == e1000_82542_rev2_0) {

   527 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   528 			e1000_pci_set_mwi(hw);

   529 	}

   530 

   531 	return E1000_SUCCESS;

   532 }

   533 

   534 /**

   535  * e1000_init_hw: Performs basic configuration of the adapter.

   536  * @hw: Struct containing variables accessed by shared code

   537  *

   538  * Assumes that the controller has previously been reset and is in a

   539  * post-reset uninitialized state. Initializes the receive address registers,

   540  * multicast table, and VLAN filter table. Calls routines to setup link

   541  * configuration and flow control settings. Clears all on-chip counters. Leaves

   542  * the transmit and receive units disabled and uninitialized.

   543  */

   544 s32 e1000_init_hw(struct e1000_hw *hw)

   545 {

   546 	u32 ctrl;

   547 	u32 i;

   548 	s32 ret_val;

   549 	u32 mta_size;

   550 	u32 ctrl_ext;

   551 

   552 	e_dbg("e1000_init_hw");

   553 

   554 	/* Initialize Identification LED */

   555 	ret_val = e1000_id_led_init(hw);

   556 	if (ret_val) {

   557 		e_dbg("Error Initializing Identification LED\n");

   558 		return ret_val;

   559 	}

   560 

   561 	/* Set the media type and TBI compatibility */

   562 	e1000_set_media_type(hw);

   563 

   564 	/* Disabling VLAN filtering. */

   565 	e_dbg("Initializing the IEEE VLAN\n");

   566 	if (hw->mac_type < e1000_82545_rev_3)

   567 		ew32(VET, 0);

   568 	e1000_clear_vfta(hw);

   569 

   570 	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */

   571 	if (hw->mac_type == e1000_82542_rev2_0) {

   572 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   573 		e1000_pci_clear_mwi(hw);

   574 		ew32(RCTL, E1000_RCTL_RST);

   575 		E1000_WRITE_FLUSH();

   576 		msleep(5);

   577 	}

   578 

   579 	/* Setup the receive address. This involves initializing all of the Receive

   580 	 * Address Registers (RARs 0 - 15).

   581 	 */

   582 	e1000_init_rx_addrs(hw);

   583 

   584 	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */

   585 	if (hw->mac_type == e1000_82542_rev2_0) {

   586 		ew32(RCTL, 0);

   587 		E1000_WRITE_FLUSH();

   588 		msleep(1);

   589 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   590 			e1000_pci_set_mwi(hw);

   591 	}

   592 

   593 	/* Zero out the Multicast HASH table */

   594 	e_dbg("Zeroing the MTA\n");

   595 	mta_size = E1000_MC_TBL_SIZE;

   596 	for (i = 0; i < mta_size; i++) {

   597 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);

   598 		/* use write flush to prevent Memory Write Block (MWB) from

   599 		 * occurring when accessing our register space */

   600 		E1000_WRITE_FLUSH();

   601 	}

   602 

   603 	/* Set the PCI priority bit correctly in the CTRL register.  This

   604 	 * determines if the adapter gives priority to receives, or if it

   605 	 * gives equal priority to transmits and receives.  Valid only on

   606 	 * 82542 and 82543 silicon.

   607 	 */

   608 	if (hw->dma_fairness && hw->mac_type <= e1000_82543) {

   609 		ctrl = er32(CTRL);

   610 		ew32(CTRL, ctrl | E1000_CTRL_PRIOR);

   611 	}

   612 

   613 	switch (hw->mac_type) {

   614 	case e1000_82545_rev_3:

   615 	case e1000_82546_rev_3:

   616 		break;

   617 	default:

   618 		/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */

   619 		if (hw->bus_type == e1000_bus_type_pcix

   620 		    && e1000_pcix_get_mmrbc(hw) > 2048)

   621 			e1000_pcix_set_mmrbc(hw, 2048);

   622 		break;

   623 	}

   624 

   625 	/* Call a subroutine to configure the link and setup flow control. */

   626 	ret_val = e1000_setup_link(hw);

   627 

   628 	/* Set the transmit descriptor write-back policy */

   629 	if (hw->mac_type > e1000_82544) {

   630 		ctrl = er32(TXDCTL);

   631 		ctrl =

   632 		    (ctrl & ~E1000_TXDCTL_WTHRESH) |

   633 		    E1000_TXDCTL_FULL_TX_DESC_WB;

   634 		ew32(TXDCTL, ctrl);

   635 	}

   636 

   637 	/* Clear all of the statistics registers (clear on read).  It is

   638 	 * important that we do this after we have tried to establish link

   639 	 * because the symbol error count will increment wildly if there

   640 	 * is no link.

   641 	 */

   642 	e1000_clear_hw_cntrs(hw);

   643 

   644 	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||

   645 	    hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {

   646 		ctrl_ext = er32(CTRL_EXT);

   647 		/* Relaxed ordering must be disabled to avoid a parity

   648 		 * error crash in a PCI slot. */

   649 		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;

   650 		ew32(CTRL_EXT, ctrl_ext);

   651 	}

   652 

   653 	return ret_val;

   654 }

   655 

   656 /**

   657  * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.

   658  * @hw: Struct containing variables accessed by shared code.

   659  */

   660 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)

   661 {

   662 	u16 eeprom_data;

   663 	s32 ret_val;

   664 

   665 	e_dbg("e1000_adjust_serdes_amplitude");

   666 

   667 	if (hw->media_type != e1000_media_type_internal_serdes)

   668 		return E1000_SUCCESS;

   669 

   670 	switch (hw->mac_type) {

   671 	case e1000_82545_rev_3:

   672 	case e1000_82546_rev_3:

   673 		break;

   674 	default:

   675 		return E1000_SUCCESS;

   676 	}

   677 

   678 	ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,

   679 	                            &eeprom_data);

   680 	if (ret_val) {

   681 		return ret_val;

   682 	}

   683 

   684 	if (eeprom_data != EEPROM_RESERVED_WORD) {

   685 		/* Adjust SERDES output amplitude only. */

   686 		eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;

   687 		ret_val =

   688 		    e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);

   689 		if (ret_val)

   690 			return ret_val;

   691 	}

   692 

   693 	return E1000_SUCCESS;

   694 }

   695 

   696 /**

   697  * e1000_setup_link - Configures flow control and link settings.

   698  * @hw: Struct containing variables accessed by shared code

   699  *

   700  * Determines which flow control settings to use. Calls the appropriate media-

   701  * specific link configuration function. Configures the flow control settings.

   702  * Assuming the adapter has a valid link partner, a valid link should be

   703  * established. Assumes the hardware has previously been reset and the

   704  * transmitter and receiver are not enabled.

   705  */

   706 s32 e1000_setup_link(struct e1000_hw *hw)

   707 {

   708 	u32 ctrl_ext;

   709 	s32 ret_val;

   710 	u16 eeprom_data;

   711 

   712 	e_dbg("e1000_setup_link");

   713 

   714 	/* Read and store word 0x0F of the EEPROM. This word contains bits

   715 	 * that determine the hardware's default PAUSE (flow control) mode,

   716 	 * a bit that determines whether the HW defaults to enabling or

   717 	 * disabling auto-negotiation, and the direction of the

   718 	 * SW defined pins. If there is no SW over-ride of the flow

   719 	 * control setting, then the variable hw->fc will

   720 	 * be initialized based on a value in the EEPROM.

   721 	 */

   722 	if (hw->fc == E1000_FC_DEFAULT) {

   723 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   724 					    1, &eeprom_data);

   725 		if (ret_val) {

   726 			e_dbg("EEPROM Read Error\n");

   727 			return -E1000_ERR_EEPROM;

   728 		}

   729 		if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)

   730 			hw->fc = E1000_FC_NONE;

   731 		else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==

   732 			 EEPROM_WORD0F_ASM_DIR)

   733 			hw->fc = E1000_FC_TX_PAUSE;

   734 		else

   735 			hw->fc = E1000_FC_FULL;

   736 	}

   737 

   738 	/* We want to save off the original Flow Control configuration just

   739 	 * in case we get disconnected and then reconnected into a different

   740 	 * hub or switch with different Flow Control capabilities.

   741 	 */

   742 	if (hw->mac_type == e1000_82542_rev2_0)

   743 		hw->fc &= (~E1000_FC_TX_PAUSE);

   744 

   745 	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))

   746 		hw->fc &= (~E1000_FC_RX_PAUSE);

   747 

   748 	hw->original_fc = hw->fc;

   749 

   750 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);

   751 

   752 	/* Take the 4 bits from EEPROM word 0x0F that determine the initial

   753 	 * polarity value for the SW controlled pins, and setup the

   754 	 * Extended Device Control reg with that info.

   755 	 * This is needed because one of the SW controlled pins is used for

   756 	 * signal detection.  So this should be done before e1000_setup_pcs_link()

   757 	 * or e1000_phy_setup() is called.

   758 	 */

   759 	if (hw->mac_type == e1000_82543) {

   760 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   761 					    1, &eeprom_data);

   762 		if (ret_val) {

   763 			e_dbg("EEPROM Read Error\n");

   764 			return -E1000_ERR_EEPROM;

   765 		}

   766 		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<

   767 			    SWDPIO__EXT_SHIFT);

   768 		ew32(CTRL_EXT, ctrl_ext);

   769 	}

   770 

   771 	/* Call the necessary subroutine to configure the link. */

   772 	ret_val = (hw->media_type == e1000_media_type_copper) ?

   773 	    e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);

   774 

   775 	/* Initialize the flow control address, type, and PAUSE timer

   776 	 * registers to their default values.  This is done even if flow

   777 	 * control is disabled, because it does not hurt anything to

   778 	 * initialize these registers.

   779 	 */

   780 	e_dbg("Initializing the Flow Control address, type and timer regs\n");

   781 

   782 	ew32(FCT, FLOW_CONTROL_TYPE);

   783 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);

   784 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);

   785 

   786 	ew32(FCTTV, hw->fc_pause_time);

   787 

   788 	/* Set the flow control receive threshold registers.  Normally,

   789 	 * these registers will be set to a default threshold that may be

   790 	 * adjusted later by the driver's runtime code.  However, if the

   791 	 * ability to transmit pause frames in not enabled, then these

   792 	 * registers will be set to 0.

   793 	 */

   794 	if (!(hw->fc & E1000_FC_TX_PAUSE)) {

   795 		ew32(FCRTL, 0);

   796 		ew32(FCRTH, 0);

   797 	} else {

   798 		/* We need to set up the Receive Threshold high and low water marks

   799 		 * as well as (optionally) enabling the transmission of XON frames.

   800 		 */

   801 		if (hw->fc_send_xon) {

   802 			ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));

   803 			ew32(FCRTH, hw->fc_high_water);

   804 		} else {

   805 			ew32(FCRTL, hw->fc_low_water);

   806 			ew32(FCRTH, hw->fc_high_water);

   807 		}

   808 	}

   809 	return ret_val;

   810 }

   811 

   812 /**

   813  * e1000_setup_fiber_serdes_link - prepare fiber or serdes link

   814  * @hw: Struct containing variables accessed by shared code

   815  *

   816  * Manipulates Physical Coding Sublayer functions in order to configure

   817  * link. Assumes the hardware has been previously reset and the transmitter

   818  * and receiver are not enabled.

   819  */

   820 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)

   821 {

   822 	u32 ctrl;

   823 	u32 status;

   824 	u32 txcw = 0;

   825 	u32 i;

   826 	u32 signal = 0;

   827 	s32 ret_val;

   828 

   829 	e_dbg("e1000_setup_fiber_serdes_link");

   830 

   831 	/* On adapters with a MAC newer than 82544, SWDP 1 will be

   832 	 * set when the optics detect a signal. On older adapters, it will be

   833 	 * cleared when there is a signal.  This applies to fiber media only.

   834 	 * If we're on serdes media, adjust the output amplitude to value

   835 	 * set in the EEPROM.

   836 	 */

   837 	ctrl = er32(CTRL);

   838 	if (hw->media_type == e1000_media_type_fiber)

   839 		signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;

   840 

   841 	ret_val = e1000_adjust_serdes_amplitude(hw);

   842 	if (ret_val)

   843 		return ret_val;

   844 

   845 	/* Take the link out of reset */

   846 	ctrl &= ~(E1000_CTRL_LRST);

   847 

   848 	/* Adjust VCO speed to improve BER performance */

   849 	ret_val = e1000_set_vco_speed(hw);

   850 	if (ret_val)

   851 		return ret_val;

   852 

   853 	e1000_config_collision_dist(hw);

   854 

   855 	/* Check for a software override of the flow control settings, and setup

   856 	 * the device accordingly.  If auto-negotiation is enabled, then software

   857 	 * will have to set the "PAUSE" bits to the correct value in the Tranmsit

   858 	 * Config Word Register (TXCW) and re-start auto-negotiation.  However, if

   859 	 * auto-negotiation is disabled, then software will have to manually

   860 	 * configure the two flow control enable bits in the CTRL register.

   861 	 *

   862 	 * The possible values of the "fc" parameter are:

   863 	 *      0:  Flow control is completely disabled

   864 	 *      1:  Rx flow control is enabled (we can receive pause frames, but

   865 	 *          not send pause frames).

   866 	 *      2:  Tx flow control is enabled (we can send pause frames but we do

   867 	 *          not support receiving pause frames).

   868 	 *      3:  Both Rx and TX flow control (symmetric) are enabled.

   869 	 */

   870 	switch (hw->fc) {

   871 	case E1000_FC_NONE:

   872 		/* Flow control is completely disabled by a software over-ride. */

   873 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);

   874 		break;

   875 	case E1000_FC_RX_PAUSE:

   876 		/* RX Flow control is enabled and TX Flow control is disabled by a

   877 		 * software over-ride. Since there really isn't a way to advertise

   878 		 * that we are capable of RX Pause ONLY, we will advertise that we

   879 		 * support both symmetric and asymmetric RX PAUSE. Later, we will

   880 		 *  disable the adapter's ability to send PAUSE frames.

   881 		 */

   882 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   883 		break;

   884 	case E1000_FC_TX_PAUSE:

   885 		/* TX Flow control is enabled, and RX Flow control is disabled, by a

   886 		 * software over-ride.

   887 		 */

   888 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);

   889 		break;

   890 	case E1000_FC_FULL:

   891 		/* Flow control (both RX and TX) is enabled by a software over-ride. */

   892 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   893 		break;

   894 	default:

   895 		e_dbg("Flow control param set incorrectly\n");

   896 		return -E1000_ERR_CONFIG;

   897 		break;

   898 	}

   899 

   900 	/* Since auto-negotiation is enabled, take the link out of reset (the link

   901 	 * will be in reset, because we previously reset the chip). This will

   902 	 * restart auto-negotiation.  If auto-negotiation is successful then the

   903 	 * link-up status bit will be set and the flow control enable bits (RFCE

   904 	 * and TFCE) will be set according to their negotiated value.

   905 	 */

   906 	e_dbg("Auto-negotiation enabled\n");

   907 

   908 	ew32(TXCW, txcw);

   909 	ew32(CTRL, ctrl);

   910 	E1000_WRITE_FLUSH();

   911 

   912 	hw->txcw = txcw;

   913 	msleep(1);

   914 

   915 	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"

   916 	 * indication in the Device Status Register.  Time-out if a link isn't

   917 	 * seen in 500 milliseconds seconds (Auto-negotiation should complete in

   918 	 * less than 500 milliseconds even if the other end is doing it in SW).

   919 	 * For internal serdes, we just assume a signal is present, then poll.

   920 	 */

   921 	if (hw->media_type == e1000_media_type_internal_serdes ||

   922 	    (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {

   923 		e_dbg("Looking for Link\n");

   924 		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {

   925 			msleep(10);

   926 			status = er32(STATUS);

   927 			if (status & E1000_STATUS_LU)

   928 				break;

   929 		}

   930 		if (i == (LINK_UP_TIMEOUT / 10)) {

   931 			e_dbg("Never got a valid link from auto-neg!!!\n");

   932 			hw->autoneg_failed = 1;

   933 			/* AutoNeg failed to achieve a link, so we'll call

   934 			 * e1000_check_for_link. This routine will force the link up if

   935 			 * we detect a signal. This will allow us to communicate with

   936 			 * non-autonegotiating link partners.

   937 			 */

   938 			ret_val = e1000_check_for_link(hw);

   939 			if (ret_val) {

   940 				e_dbg("Error while checking for link\n");

   941 				return ret_val;

   942 			}

   943 			hw->autoneg_failed = 0;

   944 		} else {

   945 			hw->autoneg_failed = 0;

   946 			e_dbg("Valid Link Found\n");

   947 		}

   948 	} else {

   949 		e_dbg("No Signal Detected\n");

   950 	}

   951 	return E1000_SUCCESS;

   952 }

   953 

   954 /**

   955  * e1000_copper_link_preconfig - early configuration for copper

   956  * @hw: Struct containing variables accessed by shared code

   957  *

   958  * Make sure we have a valid PHY and change PHY mode before link setup.

   959  */

   960 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)

   961 {

   962 	u32 ctrl;

   963 	s32 ret_val;

   964 	u16 phy_data;

   965 

   966 	e_dbg("e1000_copper_link_preconfig");

   967 

   968 	ctrl = er32(CTRL);

   969 	/* With 82543, we need to force speed and duplex on the MAC equal to what

   970 	 * the PHY speed and duplex configuration is. In addition, we need to

   971 	 * perform a hardware reset on the PHY to take it out of reset.

   972 	 */

   973 	if (hw->mac_type > e1000_82543) {

   974 		ctrl |= E1000_CTRL_SLU;

   975 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

   976 		ew32(CTRL, ctrl);

   977 	} else {

   978 		ctrl |=

   979 		    (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);

   980 		ew32(CTRL, ctrl);

   981 		ret_val = e1000_phy_hw_reset(hw);

   982 		if (ret_val)

   983 			return ret_val;

   984 	}

   985 

   986 	/* Make sure we have a valid PHY */

   987 	ret_val = e1000_detect_gig_phy(hw);

   988 	if (ret_val) {

   989 		e_dbg("Error, did not detect valid phy.\n");

   990 		return ret_val;

   991 	}

   992 	e_dbg("Phy ID = %x\n", hw->phy_id);

   993 

   994 	/* Set PHY to class A mode (if necessary) */

   995 	ret_val = e1000_set_phy_mode(hw);

   996 	if (ret_val)

   997 		return ret_val;

   998 

   999 	if ((hw->mac_type == e1000_82545_rev_3) ||

  1000 	    (hw->mac_type == e1000_82546_rev_3)) {

  1001 		ret_val =

  1002 		    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

  1003 		phy_data |= 0x00000008;

  1004 		ret_val =

  1005 		    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

  1006 	}

  1007 

  1008 	if (hw->mac_type <= e1000_82543 ||

  1009 	    hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||

  1010 	    hw->mac_type == e1000_82541_rev_2

  1011 	    || hw->mac_type == e1000_82547_rev_2)

  1012 		hw->phy_reset_disable = false;

  1013 

  1014 	return E1000_SUCCESS;

  1015 }

  1016 

  1017 /**

  1018  * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.

  1019  * @hw: Struct containing variables accessed by shared code

  1020  */

  1021 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)

  1022 {

  1023 	u32 led_ctrl;

  1024 	s32 ret_val;

  1025 	u16 phy_data;

  1026 

  1027 	e_dbg("e1000_copper_link_igp_setup");

  1028 

  1029 	if (hw->phy_reset_disable)

  1030 		return E1000_SUCCESS;

  1031 

  1032 	ret_val = e1000_phy_reset(hw);

  1033 	if (ret_val) {

  1034 		e_dbg("Error Resetting the PHY\n");

  1035 		return ret_val;

  1036 	}

  1037 

  1038 	/* Wait 15ms for MAC to configure PHY from eeprom settings */

  1039 	msleep(15);

  1040 	/* Configure activity LED after PHY reset */

  1041 	led_ctrl = er32(LEDCTL);

  1042 	led_ctrl &= IGP_ACTIVITY_LED_MASK;

  1043 	led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

  1044 	ew32(LEDCTL, led_ctrl);

  1045 

  1046 	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */

  1047 	if (hw->phy_type == e1000_phy_igp) {

  1048 		/* disable lplu d3 during driver init */

  1049 		ret_val = e1000_set_d3_lplu_state(hw, false);

  1050 		if (ret_val) {

  1051 			e_dbg("Error Disabling LPLU D3\n");

  1052 			return ret_val;

  1053 		}

  1054 	}

  1055 

  1056 	/* Configure mdi-mdix settings */

  1057 	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);

  1058 	if (ret_val)

  1059 		return ret_val;

  1060 

  1061 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

  1062 		hw->dsp_config_state = e1000_dsp_config_disabled;

  1063 		/* Force MDI for earlier revs of the IGP PHY */

  1064 		phy_data &=

  1065 		    ~(IGP01E1000_PSCR_AUTO_MDIX |

  1066 		      IGP01E1000_PSCR_FORCE_MDI_MDIX);

  1067 		hw->mdix = 1;

  1068 

  1069 	} else {

  1070 		hw->dsp_config_state = e1000_dsp_config_enabled;

  1071 		phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;

  1072 

  1073 		switch (hw->mdix) {

  1074 		case 1:

  1075 			phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;

  1076 			break;

  1077 		case 2:

  1078 			phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;

  1079 			break;

  1080 		case 0:

  1081 		default:

  1082 			phy_data |= IGP01E1000_PSCR_AUTO_MDIX;

  1083 			break;

  1084 		}

  1085 	}

  1086 	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);

  1087 	if (ret_val)

  1088 		return ret_val;

  1089 

  1090 	/* set auto-master slave resolution settings */

  1091 	if (hw->autoneg) {

  1092 		e1000_ms_type phy_ms_setting = hw->master_slave;

  1093 

  1094 		if (hw->ffe_config_state == e1000_ffe_config_active)

  1095 			hw->ffe_config_state = e1000_ffe_config_enabled;

  1096 

  1097 		if (hw->dsp_config_state == e1000_dsp_config_activated)

  1098 			hw->dsp_config_state = e1000_dsp_config_enabled;

  1099 

  1100 		/* when autonegotiation advertisement is only 1000Mbps then we

  1101 		 * should disable SmartSpeed and enable Auto MasterSlave

  1102 		 * resolution as hardware default. */

  1103 		if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {

  1104 			/* Disable SmartSpeed */

  1105 			ret_val =

  1106 			    e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

  1107 					       &phy_data);

  1108 			if (ret_val)

  1109 				return ret_val;

  1110 			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;

  1111 			ret_val =

  1112 			    e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

  1113 						phy_data);

  1114 			if (ret_val)

  1115 				return ret_val;

  1116 			/* Set auto Master/Slave resolution process */

  1117 			ret_val =

  1118 			    e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);

  1119 			if (ret_val)

  1120 				return ret_val;

  1121 			phy_data &= ~CR_1000T_MS_ENABLE;

  1122 			ret_val =

  1123 			    e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);

  1124 			if (ret_val)

  1125 				return ret_val;

  1126 		}

  1127 

  1128 		ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);

  1129 		if (ret_val)

  1130 			return ret_val;

  1131 

  1132 		/* load defaults for future use */

  1133 		hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?

  1134 		    ((phy_data & CR_1000T_MS_VALUE) ?

  1135 		     e1000_ms_force_master :