93 const ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */ |
93 const ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */ |
94 const ec_sync_t *sync, /**< Sync manager. */ |
94 const ec_sync_t *sync, /**< Sync manager. */ |
95 uint8_t *data /**> Configuration page memory. */ |
95 uint8_t *data /**> Configuration page memory. */ |
96 ) |
96 ) |
97 { |
97 { |
98 if (fmmu->sc->master->debug_level) { |
98 EC_CONFIG_DBG(fmmu->sc, 1, "FMMU: LogAddr 0x%08X, DomAddr 0x%08X," |
99 EC_DBG("FMMU: LogAddr 0x%08X, DomAddr 0x%08X, Size %3u, Tx %3u, PhysAddr 0x%04X, SM%u, " |
99 " Size %3u, Tx %3u" |
100 "Dir %s\n", fmmu->logical_start_address, fmmu->domain_address, fmmu->data_size, |
100 " PhysAddr 0x%04X, SM%u, Dir %s\n", |
101 fmmu->tx_size, sync->physical_start_address, fmmu->sync_index, |
101 fmmu->logical_start_address, fmmu->domain_address, |
102 fmmu->dir == EC_DIR_INPUT ? "in" : "out"); |
102 fmmu->data_size, fmmu->data_size, |
103 } |
103 sync->physical_start_address, fmmu->sync_index, |
|
104 fmmu->dir == EC_DIR_INPUT ? "in" : "out"); |
104 |
105 |
105 EC_WRITE_U32(data, fmmu->logical_start_address); |
106 EC_WRITE_U32(data, fmmu->logical_start_address); |
106 EC_WRITE_U16(data + 4, fmmu->data_size); // size of fmmu |
107 EC_WRITE_U16(data + 4, fmmu->data_size); // size of fmmu |
107 EC_WRITE_U8 (data + 6, 0x00); // logical start bit |
108 EC_WRITE_U8 (data + 6, 0x00); // logical start bit |
108 EC_WRITE_U8 (data + 7, 0x07); // logical end bit |
109 EC_WRITE_U8 (data + 7, 0x07); // logical end bit |