93 

    93 

    94         slave->ports[i].dl_link = 0;

    94         slave->ports[i].dl_link = 0;

    95         slave->ports[i].dl_loop = 0;

    95         slave->ports[i].dl_loop = 0;

    96         slave->ports[i].dl_signal = 0;

    96         slave->ports[i].dl_signal = 0;

    97         slave->sii.physical_layer[i] = 0xFF;

    97         slave->sii.physical_layer[i] = 0xFF;

    98     }

   100     }

    99 

   101 

   100     slave->base_fmmu_bit_operation = 0;

   102     slave->base_fmmu_bit_operation = 0;

   101     slave->base_dc_supported = 0;

   103     slave->base_dc_supported = 0;

   102     slave->base_dc_range = EC_DC_32;

   104     slave->base_dc_range = EC_DC_32;