95         slave->ports[i].dl_loop = 0;

    95         slave->ports[i].dl_loop = 0;

    96         slave->ports[i].dl_signal = 0;

    96         slave->ports[i].dl_signal = 0;

    97         slave->sii.physical_layer[i] = 0xFF;

    97         slave->sii.physical_layer[i] = 0xFF;

    98 

    98 

    99         slave->dc_receive_times[i] = 0U;

    99         slave->dc_receive_times[i] = 0U;

   100     }

   102     }

   101 

   103 

   102     slave->base_fmmu_bit_operation = 0;

   104     slave->base_fmmu_bit_operation = 0;

   103     slave->base_dc_supported = 0;

   105     slave->base_dc_supported = 0;

   104     slave->base_dc_range = EC_DC_32;

   106     slave->base_dc_range = EC_DC_32;