1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it

    10  *  and/or modify it under the terms of the GNU General Public License

    11  *  as published by the Free Software Foundation; either version 2 of the

    12  *  License, or (at your option) any later version.

    13  *

    14  *  The IgH EtherCAT Master is distributed in the hope that it will be

    15  *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  *  GNU General Public License for more details.

    18  *

    19  *  You should have received a copy of the GNU General Public License

    20  *  along with the IgH EtherCAT Master; if not, write to the Free Software

    21  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    22  *

    23  *  The right to use EtherCAT Technology is granted and comes free of

    24  *  charge under condition of compatibility of product made by

    25  *  Licensee. People intending to distribute/sell products based on the

    26  *  code, have to sign an agreement to guarantee that products using

    27  *  software based on IgH EtherCAT master stay compatible with the actual

    28  *  EtherCAT specification (which are released themselves as an open

    29  *  standard) as the (only) precondition to have the right to use EtherCAT

    30  *  Technology, IP and trade marks.

    31  *

    32  *****************************************************************************/

    33 

    34 /** \file

    35  * EtherCAT FMMU configuration methods.

    36  */

    37 

    38 /*****************************************************************************/

    39 

    40 #include "globals.h"

    41 #include "slave_config.h"

    42 #include "master.h"

    43 

    44 #include "fmmu_config.h"

    45 

    46 /*****************************************************************************/

    47 

    48 /** FMMU configuration constructor.

    49  *

    50  * Inits an FMMU configuration, sets the logical start address and adds the

    51  * process data size for the mapped PDOs of the given direction to the domain

    52  * data size.

    53  */

    54 void ec_fmmu_config_init(

    55         ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */

    56         ec_slave_config_t *sc, /**< EtherCAT slave configuration. */

    57         ec_domain_t *domain, /**< EtherCAT domain. */

    58         ec_direction_t dir /**< PDO direction. */

    59         )

    60 {

    61     fmmu->sc = sc;

    62     fmmu->domain = domain;

    63     fmmu->dir = dir;

    64 

    65     fmmu->logical_start_address = domain->data_size;

    66     fmmu->data_size = ec_pdo_mapping_total_size(&sc->mapping[dir]);

    67     domain->data_size += fmmu->data_size;

    68 }

    69 

    70 /*****************************************************************************/

    71 

    72 /** Initializes an FMMU configuration page.

    73  *

    74  * The referenced memory (\a data) must be at least EC_FMMU_PAGE_SIZE bytes.

    75  */

    76 void ec_fmmu_config_page(

    77         const ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */

    78         const ec_sync_t *sync, /**< Sync manager. */

    79         uint8_t *data /**> Configuration page memory. */

    80         )

    81 {

    82     if (fmmu->sc->master->debug_level) {

    83         EC_DBG("FMMU: LogAddr 0x%08X, Size %3i, PhysAddr 0x%04X, Dir %s\n",

    84                fmmu->logical_start_address, fmmu->data_size,

    85                sync->physical_start_address,

    86                (sync->control_register & 0x04) ? "out" : "in");

    87     }

    88 

    89     EC_WRITE_U32(data,      fmmu->logical_start_address);

    90     EC_WRITE_U16(data + 4,  fmmu->data_size); // size of fmmu

    91     EC_WRITE_U8 (data + 6,  0x00); // logical start bit

    92     EC_WRITE_U8 (data + 7,  0x07); // logical end bit

    93     EC_WRITE_U16(data + 8,  sync->physical_start_address);

    94     EC_WRITE_U8 (data + 10, 0x00); // physical start bit

    95     EC_WRITE_U8 (data + 11, (sync->control_register & 0x04) ? 0x02 : 0x01);

    96     EC_WRITE_U16(data + 12, 0x0001); // enable

    97     EC_WRITE_U16(data + 14, 0x0000); // reserved

    98 }

    99 

   100 /*****************************************************************************/