708 { |
708 { |
709 size_t sync_size; |
709 size_t sync_size; |
710 |
710 |
711 sync_size = ec_slave_calc_sync_size(slave, fmmu->sync); |
711 sync_size = ec_slave_calc_sync_size(slave, fmmu->sync); |
712 |
712 |
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713 if (slave->master->debug_level) { |
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714 EC_DBG("Slave %i, FMMU %i:\n", |
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715 slave->ring_position, fmmu->index); |
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716 |
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717 EC_DBG(" Logical address: 0x%04X\n", fmmu->logical_start_address); |
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718 EC_DBG(" Size: %i\n", sync_size); |
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719 EC_DBG(" Physical address: 0x%04X\n", |
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720 fmmu->sync->physical_start_address); |
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721 EC_DBG(" Direction: %s\n", |
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722 ((fmmu->sync->control_register & 0x04) ? "output" : "input")); |
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723 } |
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724 |
713 EC_WRITE_U32(data, fmmu->logical_start_address); |
725 EC_WRITE_U32(data, fmmu->logical_start_address); |
714 EC_WRITE_U16(data + 4, sync_size); // size of fmmu |
726 EC_WRITE_U16(data + 4, sync_size); // size of fmmu |
715 EC_WRITE_U8 (data + 6, 0x00); // logical start bit |
727 EC_WRITE_U8 (data + 6, 0x00); // logical start bit |
716 EC_WRITE_U8 (data + 7, 0x07); // logical end bit |
728 EC_WRITE_U8 (data + 7, 0x07); // logical end bit |
717 EC_WRITE_U16(data + 8, fmmu->sync->physical_start_address); |
729 EC_WRITE_U16(data + 8, fmmu->sync->physical_start_address); |