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1 /****************************************************************************** |
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2 * |
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3 * Distributed clocks sample for the IgH EtherCAT master. |
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4 * |
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5 * $Id$ |
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6 * |
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7 * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH |
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8 * |
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9 * This file is part of the IgH EtherCAT Master. |
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10 * |
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11 * The IgH EtherCAT Master is free software; you can redistribute it and/or |
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12 * modify it under the terms of the GNU General Public License version 2, as |
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13 * published by the Free Software Foundation. |
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14 * |
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15 * The IgH EtherCAT Master is distributed in the hope that it will be useful, |
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16 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General |
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18 * Public License for more details. |
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19 * |
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20 * You should have received a copy of the GNU General Public License along |
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21 * with the IgH EtherCAT Master; if not, write to the Free Software |
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22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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23 * |
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24 * --- |
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25 * |
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26 * The license mentioned above concerns the source code only. Using the |
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27 * EtherCAT technology and brand is only permitted in compliance with the |
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28 * industrial property and similar rights of Beckhoff Automation GmbH. |
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29 * |
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30 *****************************************************************************/ |
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31 |
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32 // Linux |
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33 #include <linux/module.h> |
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34 #include <linux/err.h> |
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35 |
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36 // RTAI |
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37 #include <rtai_sched.h> |
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38 #include <rtai_sem.h> |
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39 |
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40 // EtherCAT |
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41 #include "../../include/ecrt.h" |
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42 |
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43 /*****************************************************************************/ |
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44 |
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45 // Module parameters |
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46 |
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47 #define FREQUENCY 1000 // task frequency in Hz |
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48 #define INHIBIT_TIME 20 |
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49 |
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50 #define TIMERTICKS (1000000000 / FREQUENCY) |
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51 |
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52 #define NUM_DIG_OUT 1 |
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53 |
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54 #define PFX "ec_dc_sample: " |
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55 |
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56 /*****************************************************************************/ |
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57 |
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58 // EtherCAT |
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59 static ec_master_t *master = NULL; |
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60 static ec_master_state_t master_state = {}; |
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61 spinlock_t master_lock = SPIN_LOCK_UNLOCKED; |
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62 |
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63 static ec_domain_t *domain1 = NULL; |
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64 static ec_domain_state_t domain1_state = {}; |
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65 |
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66 // RTAI |
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67 static RT_TASK task; |
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68 static SEM master_sem; |
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69 static cycles_t t_last_cycle = 0, t_critical; |
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70 |
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71 /*****************************************************************************/ |
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72 |
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73 // process data |
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74 static uint8_t *domain1_pd; // process data memory |
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75 |
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76 #define DigOutSlavePos(X) 0, (1 + (X)) |
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77 #define CounterSlavePos 0, 2 |
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78 |
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79 #define Beckhoff_EK1100 0x00000002, 0x044c2c52 |
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80 #define Beckhoff_EL2008 0x00000002, 0x07d83052 |
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81 #define IDS_Counter 0x000012ad, 0x05de3052 |
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82 |
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83 static int off_dig_out[NUM_DIG_OUT]; |
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84 static int off_counter_in; |
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85 static int off_counter_out; |
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86 |
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87 static unsigned int counter = 0; |
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88 static unsigned int blink_counter = 0; |
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89 static unsigned int blink = 0; |
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90 static u32 counter_value = 0U; |
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91 |
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92 /*****************************************************************************/ |
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93 |
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94 static ec_pdo_entry_info_t el2008_channels[] = { |
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95 {0x7000, 1, 1}, |
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96 {0x7010, 1, 1}, |
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97 {0x7020, 1, 1}, |
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98 {0x7030, 1, 1}, |
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99 {0x7040, 1, 1}, |
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100 {0x7050, 1, 1}, |
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101 {0x7060, 1, 1}, |
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102 {0x7070, 1, 1} |
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103 }; |
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104 |
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105 static ec_pdo_info_t el2008_pdos[] = { |
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106 {0x1600, 1, &el2008_channels[0]}, |
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107 {0x1601, 1, &el2008_channels[1]}, |
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108 {0x1602, 1, &el2008_channels[2]}, |
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109 {0x1603, 1, &el2008_channels[3]}, |
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110 {0x1604, 1, &el2008_channels[4]}, |
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111 {0x1605, 1, &el2008_channels[5]}, |
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112 {0x1606, 1, &el2008_channels[6]}, |
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113 {0x1607, 1, &el2008_channels[7]} |
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114 }; |
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115 |
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116 static ec_sync_info_t el2008_syncs[] = { |
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117 {0, EC_DIR_OUTPUT, 8, el2008_pdos}, |
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118 {1, EC_DIR_INPUT}, |
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119 {0xff} |
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120 }; |
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121 |
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122 /*****************************************************************************/ |
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123 |
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124 void check_domain1_state(void) |
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125 { |
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126 ec_domain_state_t ds; |
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127 |
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128 spin_lock(&master_lock); |
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129 ecrt_domain_state(domain1, &ds); |
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130 spin_unlock(&master_lock); |
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131 |
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132 if (ds.working_counter != domain1_state.working_counter) |
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133 printk(KERN_INFO PFX "Domain1: WC %u.\n", ds.working_counter); |
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134 if (ds.wc_state != domain1_state.wc_state) |
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135 printk(KERN_INFO PFX "Domain1: State %u.\n", ds.wc_state); |
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136 |
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137 domain1_state = ds; |
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138 } |
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139 |
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140 /*****************************************************************************/ |
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141 |
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142 void check_master_state(void) |
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143 { |
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144 ec_master_state_t ms; |
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145 |
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146 spin_lock(&master_lock); |
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147 ecrt_master_state(master, &ms); |
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148 spin_unlock(&master_lock); |
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149 |
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150 if (ms.slaves_responding != master_state.slaves_responding) |
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151 printk(KERN_INFO PFX "%u slave(s).\n", ms.slaves_responding); |
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152 if (ms.al_states != master_state.al_states) |
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153 printk(KERN_INFO PFX "AL states: 0x%02X.\n", ms.al_states); |
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154 if (ms.link_up != master_state.link_up) |
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155 printk(KERN_INFO PFX "Link is %s.\n", ms.link_up ? "up" : "down"); |
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156 |
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157 master_state = ms; |
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158 } |
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159 |
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160 /*****************************************************************************/ |
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161 |
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162 void run(long data) |
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163 { |
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164 int i; |
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165 struct timeval tv; |
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166 unsigned int sync_ref_counter = 0; |
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167 |
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168 count2timeval(nano2count(rt_get_real_time_ns()), &tv); |
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169 |
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170 while (1) { |
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171 t_last_cycle = get_cycles(); |
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172 |
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173 // receive process data |
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174 rt_sem_wait(&master_sem); |
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175 ecrt_master_receive(master); |
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176 ecrt_domain_process(domain1); |
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177 rt_sem_signal(&master_sem); |
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178 |
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179 // check process data state (optional) |
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180 check_domain1_state(); |
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181 |
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182 if (counter) { |
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183 counter--; |
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184 } else { |
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185 u32 c; |
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186 |
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187 counter = FREQUENCY; |
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188 |
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189 // check for master state (optional) |
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190 check_master_state(); |
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191 |
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192 c = EC_READ_U32(domain1_pd + off_counter_in); |
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193 if (counter_value != c) { |
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194 counter_value = c; |
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195 printk(KERN_INFO PFX "counter=%u\n", counter_value); |
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196 } |
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197 |
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198 } |
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199 |
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200 if (blink_counter) { |
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201 blink_counter--; |
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202 } else { |
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203 blink_counter = 9; |
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204 |
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205 // calculate new process data |
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206 blink = !blink; |
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207 } |
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208 |
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209 // write process data |
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210 for (i = 0; i < NUM_DIG_OUT; i++) { |
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211 EC_WRITE_U8(domain1_pd + off_dig_out[i], blink ? 0x66 : 0x99); |
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212 } |
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213 |
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214 EC_WRITE_U8(domain1_pd + off_counter_out, blink ? 0x00 : 0x02); |
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215 |
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216 rt_sem_wait(&master_sem); |
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217 |
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218 tv.tv_usec += 1000; |
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219 if (tv.tv_usec >= 1000000) { |
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220 tv.tv_usec -= 1000000; |
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221 tv.tv_sec++; |
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222 } |
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223 //printk(KERN_INFO PFX "tv=%u.%06u\n", (u32) tv.tv_sec, (u32) tv.tv_usec); |
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224 |
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225 if (sync_ref_counter) { |
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226 sync_ref_counter--; |
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227 } else { |
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228 sync_ref_counter = 9; |
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229 ecrt_master_sync_reference_clock(master, &tv); |
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230 } |
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231 ecrt_master_sync_slave_clocks(master); |
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232 ecrt_domain_queue(domain1); |
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233 ecrt_master_send(master); |
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234 rt_sem_signal(&master_sem); |
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235 |
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236 rt_task_wait_period(); |
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237 } |
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238 } |
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239 |
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240 /*****************************************************************************/ |
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241 |
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242 int request_lock(void *data) |
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243 { |
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244 // too close to the next real time cycle: deny access... |
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245 if (get_cycles() - t_last_cycle > t_critical) return -1; |
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246 |
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247 // allow access |
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248 rt_sem_wait(&master_sem); |
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249 return 0; |
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250 } |
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251 |
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252 /*****************************************************************************/ |
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253 |
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254 void release_lock(void *data) |
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255 { |
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256 rt_sem_signal(&master_sem); |
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257 } |
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258 |
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259 /*****************************************************************************/ |
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260 |
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261 int __init init_mod(void) |
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262 { |
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263 int ret = -1, i; |
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264 RTIME tick_period, requested_ticks, now; |
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265 ec_slave_config_t *sc; |
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266 |
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267 printk(KERN_INFO PFX "Starting...\n"); |
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268 |
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269 rt_sem_init(&master_sem, 1); |
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270 |
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271 t_critical = cpu_khz * 1000 / FREQUENCY - cpu_khz * INHIBIT_TIME / 1000; |
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272 |
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273 master = ecrt_request_master(0); |
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274 if (!master) { |
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275 ret = -EBUSY; |
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276 printk(KERN_ERR PFX "Requesting master 0 failed!\n"); |
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277 goto out_return; |
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278 } |
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279 |
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280 ecrt_master_callbacks(master, request_lock, release_lock, NULL); |
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281 |
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282 printk(KERN_INFO PFX "Registering domain...\n"); |
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283 if (!(domain1 = ecrt_master_create_domain(master))) { |
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284 printk(KERN_ERR PFX "Domain creation failed!\n"); |
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285 goto out_release_master; |
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286 } |
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287 |
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288 printk(KERN_INFO PFX "Configuring PDOs...\n"); |
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289 |
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290 // create configuration for reference clock FIXME |
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291 if (!(sc = ecrt_master_slave_config(master, 0, 0, Beckhoff_EK1100))) { |
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292 printk(KERN_ERR PFX "Failed to get slave configuration.\n"); |
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293 goto out_release_master; |
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294 } |
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295 |
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296 for (i = 0; i < NUM_DIG_OUT; i++) { |
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297 if (!(sc = ecrt_master_slave_config(master, |
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298 DigOutSlavePos(i), Beckhoff_EL2008))) { |
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299 printk(KERN_ERR PFX "Failed to get slave configuration.\n"); |
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300 goto out_release_master; |
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301 } |
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302 |
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303 if (ecrt_slave_config_pdos(sc, EC_END, el2008_syncs)) { |
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304 printk(KERN_ERR PFX "Failed to configure PDOs.\n"); |
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305 goto out_release_master; |
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306 } |
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307 |
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308 off_dig_out[i] = ecrt_slave_config_reg_pdo_entry(sc, |
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309 0x7000, 1, domain1, NULL); |
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310 |
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311 if (off_dig_out[i] < 0) |
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312 goto out_release_master; |
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313 } |
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314 |
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315 if (!(sc = ecrt_master_slave_config(master, |
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316 CounterSlavePos, IDS_Counter))) { |
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317 printk(KERN_ERR PFX "Failed to get slave configuration.\n"); |
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318 goto out_release_master; |
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319 } |
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320 off_counter_in = ecrt_slave_config_reg_pdo_entry(sc, |
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321 0x6020, 0x11, domain1, NULL); |
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322 if (off_counter_in < 0) |
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323 goto out_release_master; |
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324 off_counter_out = ecrt_slave_config_reg_pdo_entry(sc, |
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325 0x7020, 1, domain1, NULL); |
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326 if (off_counter_out < 0) |
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327 goto out_release_master; |
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328 |
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329 #if 1 |
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330 // configure SYNC signals for this slave |
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331 ecrt_slave_config_dc_assign_activate(sc, 0x0700); |
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332 ecrt_slave_config_dc_sync_cycle_times(sc, 1000000, 0); |
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333 ecrt_slave_config_dc_sync_shift_times(sc, 440000, 0); |
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334 #endif |
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335 |
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336 printk(KERN_INFO PFX "Activating master...\n"); |
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337 if (ecrt_master_activate(master)) { |
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338 printk(KERN_ERR PFX "Failed to activate master!\n"); |
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339 goto out_release_master; |
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340 } |
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341 |
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342 // Get internal process data for domain |
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343 domain1_pd = ecrt_domain_data(domain1); |
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344 |
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345 printk(KERN_INFO PFX "Starting cyclic sample thread...\n"); |
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346 requested_ticks = nano2count(TIMERTICKS); |
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347 tick_period = start_rt_timer(requested_ticks); |
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348 printk(KERN_INFO PFX "RT timer started with %i/%i ticks.\n", |
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349 (int) tick_period, (int) requested_ticks); |
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350 |
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351 if (rt_task_init(&task, run, 0, 2000, 0, 1, NULL)) { |
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352 printk(KERN_ERR PFX "Failed to init RTAI task!\n"); |
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353 goto out_stop_timer; |
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354 } |
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355 |
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356 now = rt_get_time(); |
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357 if (rt_task_make_periodic(&task, now + tick_period, tick_period)) { |
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358 printk(KERN_ERR PFX "Failed to run RTAI task!\n"); |
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359 goto out_stop_task; |
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360 } |
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361 |
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362 printk(KERN_INFO PFX "Initialized.\n"); |
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363 return 0; |
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364 |
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365 out_stop_task: |
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366 rt_task_delete(&task); |
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367 out_stop_timer: |
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368 stop_rt_timer(); |
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369 out_release_master: |
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370 printk(KERN_ERR PFX "Releasing master...\n"); |
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371 ecrt_release_master(master); |
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372 out_return: |
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373 rt_sem_delete(&master_sem); |
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374 printk(KERN_ERR PFX "Failed to load. Aborting.\n"); |
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375 return ret; |
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376 } |
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377 |
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378 /*****************************************************************************/ |
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379 |
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380 void __exit cleanup_mod(void) |
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381 { |
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382 printk(KERN_INFO PFX "Stopping...\n"); |
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383 |
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384 rt_task_delete(&task); |
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385 stop_rt_timer(); |
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386 ecrt_release_master(master); |
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387 rt_sem_delete(&master_sem); |
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388 |
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389 printk(KERN_INFO PFX "Unloading.\n"); |
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390 } |
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391 |
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392 /*****************************************************************************/ |
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393 |
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394 MODULE_LICENSE("GPL"); |
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395 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>"); |
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396 MODULE_DESCRIPTION("EtherCAT distributed clocks sample module"); |
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397 |
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398 module_init(init_mod); |
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399 module_exit(cleanup_mod); |
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400 |
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401 /*****************************************************************************/ |