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/******************************************************************************

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 *

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 *  $Id$

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 *

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 *  Copyright (C) 2006-2008  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it and/or

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 *  modify it under the terms of the GNU General Public License version 2, as

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 *  published by the Free Software Foundation.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

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 *  Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License along

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 *  with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

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 *  ---

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 *

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 *  The license mentioned above concerns the source code only. Using the

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 *  EtherCAT technology and brand is only permitted in compliance with the

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 *  industrial property and similar rights of Beckhoff Automation GmbH.

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 *

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 *****************************************************************************/

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/** \file

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 * EtherCAT FMMU configuration methods.

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 */

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/*****************************************************************************/

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#include "globals.h"

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#include "slave_config.h"

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#include "master.h"

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#include "fmmu_config.h"

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/*****************************************************************************/

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/** FMMU configuration constructor.

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 *

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 * Inits an FMMU configuration and the process data size forthe mapped PDOs

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 * of the given direction to the domain data size.

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 */

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void ec_fmmu_config_init(

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        ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */

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        ec_slave_config_t *sc, /**< EtherCAT slave configuration. */

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        uint8_t sync_index, /**< Sync manager index to use. */

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        ec_direction_t dir /**< PDO direction. */

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        )

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{

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    INIT_LIST_HEAD(&fmmu->list);

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    fmmu->sc = sc;

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    fmmu->sync_index = sync_index;

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    fmmu->dir = dir;

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    fmmu->data_size = ec_pdo_list_total_size(

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            &sc->sync_configs[sync_index].pdos);

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}

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/*****************************************************************************/

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/** Sets FMMU domain

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 *

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 * Sets the logical start address and the size of the transmitted data

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 */

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void ec_fmmu_config_domain(

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        ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */

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        ec_domain_t *domain, /**< EtherCAT domain. */

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        uint32_t logical_start_address, /**< FMMU logical start address. */

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        size_t tx_size /**< Size of transmitted data */

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        )

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{

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    fmmu->domain = domain;

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    fmmu->domain_address = domain->data_size;

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    fmmu->logical_start_address = logical_start_address;

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    fmmu->tx_size = tx_size;

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    ec_domain_add_fmmu_config(domain, fmmu);

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}

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/*****************************************************************************/

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/** Initializes an FMMU configuration page.

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 *

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 * The referenced memory (\a data) must be at least EC_FMMU_PAGE_SIZE bytes.

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 */

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void ec_fmmu_config_page(

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        const ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */

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        const ec_sync_t *sync, /**< Sync manager. */

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        uint8_t *data /**> Configuration page memory. */

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        )

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{

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    if (fmmu->sc->master->debug_level) {

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        EC_DBG("FMMU: LogAddr 0x%08X, DomAddr 0x%08X, Size %3u, Tx %3u, PhysAddr 0x%04X, SM%u, "

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                "Dir %s\n", fmmu->logical_start_address, fmmu->domain_address, fmmu->data_size,

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                fmmu->tx_size, sync->physical_start_address, fmmu->sync_index,

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               fmmu->dir == EC_DIR_INPUT ? "in" : "out");

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    }

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    EC_WRITE_U32(data,      fmmu->logical_start_address);

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    EC_WRITE_U16(data + 4,  fmmu->data_size); // size of fmmu

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    EC_WRITE_U8 (data + 6,  0x00); // logical start bit

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    EC_WRITE_U8 (data + 7,  0x07); // logical end bit

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    EC_WRITE_U16(data + 8,  sync->physical_start_address);

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    EC_WRITE_U8 (data + 10, 0x00); // physical start bit

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    EC_WRITE_U8 (data + 11, fmmu->dir == EC_DIR_INPUT ? 0x01 : 0x02);

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    EC_WRITE_U16(data + 12, 0x0001); // enable

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    EC_WRITE_U16(data + 14, 0x0000); // reserved

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}

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/*****************************************************************************/