1

/* Intel(R) Gigabit Ethernet Linux driver

     2

 * Copyright(c) 2007-2014 Intel Corporation.

     3

 *

     4

 * This program is free software; you can redistribute it and/or modify it

     5

 * under the terms and conditions of the GNU General Public License,

     6

 * version 2, as published by the Free Software Foundation.

     7

 *

     8

 * This program is distributed in the hope it will be useful, but WITHOUT

     9

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    11

 * more details.

    12

 *

    13

 * You should have received a copy of the GNU General Public License along with

    14

 * this program; if not, see <http://www.gnu.org/licenses/>.

    15

 *

    16

 * The full GNU General Public License is included in this distribution in

    17

 * the file called "COPYING".

    18

 *

    19

 * Contact Information:

    20

 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    21

 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    22

 */

    23

    24

#include <linux/if_ether.h>

    25

#include <linux/delay.h>

    26

#include <linux/pci.h>

    27

#include <linux/netdevice.h>

    28

#include <linux/etherdevice.h>

    29

    30

#include "e1000_mac-3.18-ethercat.h"

    31

    32

#include "igb-3.18-ethercat.h"

    33

    34

static s32 igb_set_default_fc(struct e1000_hw *hw);

    35

static s32 igb_set_fc_watermarks(struct e1000_hw *hw);

    36

    37

/**

    38

 *  igb_get_bus_info_pcie - Get PCIe bus information

    39

 *  @hw: pointer to the HW structure

    40

 *

    41

 *  Determines and stores the system bus information for a particular

    42

 *  network interface.  The following bus information is determined and stored:

    43

 *  bus speed, bus width, type (PCIe), and PCIe function.

    44

 **/

    45

s32 igb_get_bus_info_pcie(struct e1000_hw *hw)

    46

{

    47

	struct e1000_bus_info *bus = &hw->bus;

    48

	s32 ret_val;

    49

	u32 reg;

    50

	u16 pcie_link_status;

    51

    52

	bus->type = e1000_bus_type_pci_express;

    53

    54

	ret_val = igb_read_pcie_cap_reg(hw,

    55

					PCI_EXP_LNKSTA,

    56

					&pcie_link_status);

    57

	if (ret_val) {

    58

		bus->width = e1000_bus_width_unknown;

    59

		bus->speed = e1000_bus_speed_unknown;

    60

	} else {

    61

		switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {

    62

		case PCI_EXP_LNKSTA_CLS_2_5GB:

    63

			bus->speed = e1000_bus_speed_2500;

    64

			break;

    65

		case PCI_EXP_LNKSTA_CLS_5_0GB:

    66

			bus->speed = e1000_bus_speed_5000;

    67

			break;

    68

		default:

    69

			bus->speed = e1000_bus_speed_unknown;

    70

			break;

    71

		}

    72

    73

		bus->width = (enum e1000_bus_width)((pcie_link_status &

    74

						     PCI_EXP_LNKSTA_NLW) >>

    75

						     PCI_EXP_LNKSTA_NLW_SHIFT);

    76

	}

    77

    78

	reg = rd32(E1000_STATUS);

    79

	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;

    80

    81

	return 0;

    82

}

    83

    84

/**

    85

 *  igb_clear_vfta - Clear VLAN filter table

    86

 *  @hw: pointer to the HW structure

    87

 *

    88

 *  Clears the register array which contains the VLAN filter table by

    89

 *  setting all the values to 0.

    90

 **/

    91

void igb_clear_vfta(struct e1000_hw *hw)

    92

{

    93

	u32 offset;

    94

    95

	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {

    96

		array_wr32(E1000_VFTA, offset, 0);

    97

		wrfl();

    98

	}

    99

}

   100

   101

/**

   102

 *  igb_write_vfta - Write value to VLAN filter table

   103

 *  @hw: pointer to the HW structure

   104

 *  @offset: register offset in VLAN filter table

   105

 *  @value: register value written to VLAN filter table

   106

 *

   107

 *  Writes value at the given offset in the register array which stores

   108

 *  the VLAN filter table.

   109

 **/

   110

static void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)

   111

{

   112

	array_wr32(E1000_VFTA, offset, value);

   113

	wrfl();

   114

}

   115

   116

/* Due to a hw errata, if the host tries to  configure the VFTA register

   117

 * while performing queries from the BMC or DMA, then the VFTA in some

   118

 * cases won't be written.

   119

 */

   120

   121

/**

   122

 *  igb_clear_vfta_i350 - Clear VLAN filter table

   123

 *  @hw: pointer to the HW structure

   124

 *

   125

 *  Clears the register array which contains the VLAN filter table by

   126

 *  setting all the values to 0.

   127

 **/

   128

void igb_clear_vfta_i350(struct e1000_hw *hw)

   129

{

   130

	u32 offset;

   131

	int i;

   132

   133

	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {

   134

		for (i = 0; i < 10; i++)

   135

			array_wr32(E1000_VFTA, offset, 0);

   136

   137

		wrfl();

   138

	}

   139

}

   140

   141

/**

   142

 *  igb_write_vfta_i350 - Write value to VLAN filter table

   143

 *  @hw: pointer to the HW structure

   144

 *  @offset: register offset in VLAN filter table

   145

 *  @value: register value written to VLAN filter table

   146

 *

   147

 *  Writes value at the given offset in the register array which stores

   148

 *  the VLAN filter table.

   149

 **/

   150

static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)

   151

{

   152

	int i;

   153

   154

	for (i = 0; i < 10; i++)

   155

		array_wr32(E1000_VFTA, offset, value);

   156

   157

	wrfl();

   158

}

   159

   160

/**

   161

 *  igb_init_rx_addrs - Initialize receive address's

   162

 *  @hw: pointer to the HW structure

   163

 *  @rar_count: receive address registers

   164

 *

   165

 *  Setups the receive address registers by setting the base receive address

   166

 *  register to the devices MAC address and clearing all the other receive

   167

 *  address registers to 0.

   168

 **/

   169

void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)

   170

{

   171

	u32 i;

   172

	u8 mac_addr[ETH_ALEN] = {0};

   173

   174

	/* Setup the receive address */

   175

	hw_dbg("Programming MAC Address into RAR[0]\n");

   176

   177

	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);

   178

   179

	/* Zero out the other (rar_entry_count - 1) receive addresses */

   180

	hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);

   181

	for (i = 1; i < rar_count; i++)

   182

		hw->mac.ops.rar_set(hw, mac_addr, i);

   183

}

   184

   185

/**

   186

 *  igb_vfta_set - enable or disable vlan in VLAN filter table

   187

 *  @hw: pointer to the HW structure

   188

 *  @vid: VLAN id to add or remove

   189

 *  @add: if true add filter, if false remove

   190

 *

   191

 *  Sets or clears a bit in the VLAN filter table array based on VLAN id

   192

 *  and if we are adding or removing the filter

   193

 **/

   194

s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add)

   195

{

   196

	u32 index = (vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;

   197

	u32 mask = 1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK);

   198

	u32 vfta;

   199

	struct igb_adapter *adapter = hw->back;

   200

	s32 ret_val = 0;

   201

   202

	vfta = adapter->shadow_vfta[index];

   203

   204

	/* bit was set/cleared before we started */

   205

	if ((!!(vfta & mask)) == add) {

   206

		ret_val = -E1000_ERR_CONFIG;

   207

	} else {

   208

		if (add)

   209

			vfta |= mask;

   210

		else

   211

			vfta &= ~mask;

   212

	}

   213

	if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))

   214

		igb_write_vfta_i350(hw, index, vfta);

   215

	else

   216

		igb_write_vfta(hw, index, vfta);

   217

	adapter->shadow_vfta[index] = vfta;

   218

   219

	return ret_val;

   220

}

   221

   222

/**

   223

 *  igb_check_alt_mac_addr - Check for alternate MAC addr

   224

 *  @hw: pointer to the HW structure

   225

 *

   226

 *  Checks the nvm for an alternate MAC address.  An alternate MAC address

   227

 *  can be setup by pre-boot software and must be treated like a permanent

   228

 *  address and must override the actual permanent MAC address.  If an

   229

 *  alternate MAC address is found it is saved in the hw struct and

   230

 *  programmed into RAR0 and the function returns success, otherwise the

   231

 *  function returns an error.

   232

 **/

   233

s32 igb_check_alt_mac_addr(struct e1000_hw *hw)

   234

{

   235

	u32 i;

   236

	s32 ret_val = 0;

   237

	u16 offset, nvm_alt_mac_addr_offset, nvm_data;

   238

	u8 alt_mac_addr[ETH_ALEN];

   239

   240

	/* Alternate MAC address is handled by the option ROM for 82580

   241

	 * and newer. SW support not required.

   242

	 */

   243

	if (hw->mac.type >= e1000_82580)

   244

		goto out;

   245

   246

	ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,

   247

				 &nvm_alt_mac_addr_offset);

   248

	if (ret_val) {

   249

		hw_dbg("NVM Read Error\n");

   250

		goto out;

   251

	}

   252

   253

	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||

   254

	    (nvm_alt_mac_addr_offset == 0x0000))

   255

		/* There is no Alternate MAC Address */

   256

		goto out;

   257

   258

	if (hw->bus.func == E1000_FUNC_1)

   259

		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;

   260

	if (hw->bus.func == E1000_FUNC_2)

   261

		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;

   262

   263

	if (hw->bus.func == E1000_FUNC_3)

   264

		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;

   265

	for (i = 0; i < ETH_ALEN; i += 2) {

   266

		offset = nvm_alt_mac_addr_offset + (i >> 1);

   267

		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);

   268

		if (ret_val) {

   269

			hw_dbg("NVM Read Error\n");

   270

			goto out;

   271

		}

   272

   273

		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);

   274

		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);

   275

	}

   276

   277

	/* if multicast bit is set, the alternate address will not be used */

   278

	if (is_multicast_ether_addr(alt_mac_addr)) {

   279

		hw_dbg("Ignoring Alternate Mac Address with MC bit set\n");

   280

		goto out;

   281

	}

   282

   283

	/* We have a valid alternate MAC address, and we want to treat it the

   284

	 * same as the normal permanent MAC address stored by the HW into the

   285

	 * RAR. Do this by mapping this address into RAR0.

   286

	 */

   287

	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);

   288

   289

out:

   290

	return ret_val;

   291

}

   292

   293

/**

   294

 *  igb_rar_set - Set receive address register

   295

 *  @hw: pointer to the HW structure

   296

 *  @addr: pointer to the receive address

   297

 *  @index: receive address array register

   298

 *

   299

 *  Sets the receive address array register at index to the address passed

   300

 *  in by addr.

   301

 **/

   302

void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)

   303

{

   304

	u32 rar_low, rar_high;

   305

   306

	/* HW expects these in little endian so we reverse the byte order

   307

	 * from network order (big endian) to little endian

   308

	 */

   309

	rar_low = ((u32) addr[0] |

   310

		   ((u32) addr[1] << 8) |

   311

		    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));

   312

   313

	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

   314

   315

	/* If MAC address zero, no need to set the AV bit */

   316

	if (rar_low || rar_high)

   317

		rar_high |= E1000_RAH_AV;

   318

   319

	/* Some bridges will combine consecutive 32-bit writes into

   320

	 * a single burst write, which will malfunction on some parts.

   321

	 * The flushes avoid this.

   322

	 */

   323

	wr32(E1000_RAL(index), rar_low);

   324

	wrfl();

   325

	wr32(E1000_RAH(index), rar_high);

   326

	wrfl();

   327

}

   328

   329

/**

   330

 *  igb_mta_set - Set multicast filter table address

   331

 *  @hw: pointer to the HW structure

   332

 *  @hash_value: determines the MTA register and bit to set

   333

 *

   334

 *  The multicast table address is a register array of 32-bit registers.

   335

 *  The hash_value is used to determine what register the bit is in, the

   336

 *  current value is read, the new bit is OR'd in and the new value is

   337

 *  written back into the register.

   338

 **/

   339

void igb_mta_set(struct e1000_hw *hw, u32 hash_value)

   340

{

   341

	u32 hash_bit, hash_reg, mta;

   342

   343

	/* The MTA is a register array of 32-bit registers. It is

   344

	 * treated like an array of (32*mta_reg_count) bits.  We want to

   345

	 * set bit BitArray[hash_value]. So we figure out what register

   346

	 * the bit is in, read it, OR in the new bit, then write

   347

	 * back the new value.  The (hw->mac.mta_reg_count - 1) serves as a

   348

	 * mask to bits 31:5 of the hash value which gives us the

   349

	 * register we're modifying.  The hash bit within that register

   350

	 * is determined by the lower 5 bits of the hash value.

   351

	 */

   352

	hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);

   353

	hash_bit = hash_value & 0x1F;

   354

   355

	mta = array_rd32(E1000_MTA, hash_reg);

   356

   357

	mta |= (1 << hash_bit);

   358

   359

	array_wr32(E1000_MTA, hash_reg, mta);

   360

	wrfl();

   361

}

   362

   363

/**

   364

 *  igb_hash_mc_addr - Generate a multicast hash value

   365

 *  @hw: pointer to the HW structure

   366

 *  @mc_addr: pointer to a multicast address

   367

 *

   368

 *  Generates a multicast address hash value which is used to determine

   369

 *  the multicast filter table array address and new table value.  See

   370

 *  igb_mta_set()

   371

 **/

   372

static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)

   373

{

   374

	u32 hash_value, hash_mask;

   375

	u8 bit_shift = 0;

   376

   377

	/* Register count multiplied by bits per register */

   378

	hash_mask = (hw->mac.mta_reg_count * 32) - 1;

   379

   380

	/* For a mc_filter_type of 0, bit_shift is the number of left-shifts

   381

	 * where 0xFF would still fall within the hash mask.

   382

	 */

   383

	while (hash_mask >> bit_shift != 0xFF)

   384

		bit_shift++;

   385

   386

	/* The portion of the address that is used for the hash table

   387

	 * is determined by the mc_filter_type setting.

   388

	 * The algorithm is such that there is a total of 8 bits of shifting.

   389

	 * The bit_shift for a mc_filter_type of 0 represents the number of

   390

	 * left-shifts where the MSB of mc_addr[5] would still fall within

   391

	 * the hash_mask.  Case 0 does this exactly.  Since there are a total

   392

	 * of 8 bits of shifting, then mc_addr[4] will shift right the

   393

	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the

   394

	 * cases are a variation of this algorithm...essentially raising the

   395

	 * number of bits to shift mc_addr[5] left, while still keeping the

   396

	 * 8-bit shifting total.

   397

	 *

   398

	 * For example, given the following Destination MAC Address and an

   399

	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),

   400

	 * we can see that the bit_shift for case 0 is 4.  These are the hash

   401

	 * values resulting from each mc_filter_type...

   402

	 * [0] [1] [2] [3] [4] [5]

   403

	 * 01  AA  00  12  34  56

   404

	 * LSB                 MSB

   405

	 *

   406

	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563

   407

	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6

   408

	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163

   409

	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634

   410

	 */

   411

	switch (hw->mac.mc_filter_type) {

   412

	default:

   413

	case 0:

   414

		break;

   415

	case 1:

   416

		bit_shift += 1;

   417

		break;

   418

	case 2:

   419

		bit_shift += 2;

   420

		break;

   421

	case 3:

   422

		bit_shift += 4;

   423

		break;

   424

	}

   425

   426

	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |

   427

				  (((u16) mc_addr[5]) << bit_shift)));

   428

   429

	return hash_value;

   430

}

   431

   432

/**

   433

 *  igb_update_mc_addr_list - Update Multicast addresses

   434

 *  @hw: pointer to the HW structure

   435

 *  @mc_addr_list: array of multicast addresses to program

   436

 *  @mc_addr_count: number of multicast addresses to program

   437

 *

   438

 *  Updates entire Multicast Table Array.

   439

 *  The caller must have a packed mc_addr_list of multicast addresses.

   440

 **/

   441

void igb_update_mc_addr_list(struct e1000_hw *hw,

   442

			     u8 *mc_addr_list, u32 mc_addr_count)

   443

{

   444

	u32 hash_value, hash_bit, hash_reg;

   445

	int i;

   446

   447

	/* clear mta_shadow */

   448

	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));

   449

   450

	/* update mta_shadow from mc_addr_list */

   451

	for (i = 0; (u32) i < mc_addr_count; i++) {

   452

		hash_value = igb_hash_mc_addr(hw, mc_addr_list);

   453

   454

		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);

   455

		hash_bit = hash_value & 0x1F;

   456

   457

		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);

   458

		mc_addr_list += (ETH_ALEN);

   459

	}

   460

   461

	/* replace the entire MTA table */

   462

	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)

   463

		array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);

   464

	wrfl();

   465

}

   466

   467

/**

   468

 *  igb_clear_hw_cntrs_base - Clear base hardware counters

   469

 *  @hw: pointer to the HW structure

   470

 *

   471

 *  Clears the base hardware counters by reading the counter registers.

   472

 **/

   473

void igb_clear_hw_cntrs_base(struct e1000_hw *hw)

   474

{

   475

	rd32(E1000_CRCERRS);

   476

	rd32(E1000_SYMERRS);

   477

	rd32(E1000_MPC);

   478

	rd32(E1000_SCC);

   479

	rd32(E1000_ECOL);

   480

	rd32(E1000_MCC);

   481

	rd32(E1000_LATECOL);

   482

	rd32(E1000_COLC);

   483

	rd32(E1000_DC);

   484

	rd32(E1000_SEC);

   485

	rd32(E1000_RLEC);

   486

	rd32(E1000_XONRXC);

   487

	rd32(E1000_XONTXC);

   488

	rd32(E1000_XOFFRXC);

   489

	rd32(E1000_XOFFTXC);

   490

	rd32(E1000_FCRUC);

   491

	rd32(E1000_GPRC);

   492

	rd32(E1000_BPRC);

   493

	rd32(E1000_MPRC);

   494

	rd32(E1000_GPTC);

   495

	rd32(E1000_GORCL);

   496

	rd32(E1000_GORCH);

   497

	rd32(E1000_GOTCL);

   498

	rd32(E1000_GOTCH);

   499

	rd32(E1000_RNBC);

   500

	rd32(E1000_RUC);

   501

	rd32(E1000_RFC);

   502

	rd32(E1000_ROC);

   503

	rd32(E1000_RJC);

   504

	rd32(E1000_TORL);

   505

	rd32(E1000_TORH);

   506

	rd32(E1000_TOTL);

   507

	rd32(E1000_TOTH);

   508

	rd32(E1000_TPR);

   509

	rd32(E1000_TPT);

   510

	rd32(E1000_MPTC);

   511

	rd32(E1000_BPTC);

   512

}

   513

   514

/**

   515

 *  igb_check_for_copper_link - Check for link (Copper)

   516

 *  @hw: pointer to the HW structure

   517

 *

   518

 *  Checks to see of the link status of the hardware has changed.  If a

   519

 *  change in link status has been detected, then we read the PHY registers

   520

 *  to get the current speed/duplex if link exists.

   521

 **/

   522

s32 igb_check_for_copper_link(struct e1000_hw *hw)

   523

{

   524

	struct e1000_mac_info *mac = &hw->mac;

   525

	s32 ret_val;

   526

	bool link;

   527

   528

	/* We only want to go out to the PHY registers to see if Auto-Neg

   529

	 * has completed and/or if our link status has changed.  The

   530