1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2006 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

 */

    28

    29

/* e1000_hw.c

    30

 * Shared functions for accessing and configuring the MAC

    31

 */

    32

    33

#include "e1000-3.4-ethercat.h"

    34

    35

static s32 e1000_check_downshift(struct e1000_hw *hw);

    36

static s32 e1000_check_polarity(struct e1000_hw *hw,

    37

				e1000_rev_polarity *polarity);

    38

static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39

static void e1000_clear_vfta(struct e1000_hw *hw);

    40

static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41

					      bool link_up);

    42

static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43

static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44

static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45

static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46

				  u16 *max_length);

    47

static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48

static s32 e1000_id_led_init(struct e1000_hw *hw);

    49

static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50

static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51

				  struct e1000_phy_info *phy_info);

    52

static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53

				  struct e1000_phy_info *phy_info);

    54

static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55

static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56

static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57

static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58

static void e1000_phy_init_script(struct e1000_hw *hw);

    59

static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60

static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61

static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62

static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63

static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64

static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65

static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66

static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67

static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68

static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69

static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70

				  u16 words, u16 *data);

    71

static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72

					u16 words, u16 *data);

    73

static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74

static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75

static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76

static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77

static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78

				  u16 phy_data);

    79

static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

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				 u16 *phy_data);

    81

static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82

static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83

static void e1000_release_eeprom(struct e1000_hw *hw);

    84

static void e1000_standby_eeprom(struct e1000_hw *hw);

    85

static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86

static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87

static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88

static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89

				u16 *data);

    90

static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91

				 u16 *data);

    92

    93

/* IGP cable length table */

    94

static const

    95

u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96

	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    97

	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98

	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99

	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100

	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101

	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102

	    100,

   103

	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104

	    110, 110,

   105

	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106

	    120, 120

   107

};

   108

   109

static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110

   111

/**

   112

 * e1000_set_phy_type - Set the phy type member in the hw struct.

   113

 * @hw: Struct containing variables accessed by shared code

   114

 */

   115

static s32 e1000_set_phy_type(struct e1000_hw *hw)

   116

{

   117

	e_dbg("e1000_set_phy_type");

   118

   119

	if (hw->mac_type == e1000_undefined)

   120

		return -E1000_ERR_PHY_TYPE;

   121

   122

	switch (hw->phy_id) {

   123

	case M88E1000_E_PHY_ID:

   124

	case M88E1000_I_PHY_ID:

   125

	case M88E1011_I_PHY_ID:

   126

	case M88E1111_I_PHY_ID:

   127

	case M88E1118_E_PHY_ID:

   128

		hw->phy_type = e1000_phy_m88;

   129

		break;

   130

	case IGP01E1000_I_PHY_ID:

   131

		if (hw->mac_type == e1000_82541 ||

   132

		    hw->mac_type == e1000_82541_rev_2 ||

   133

		    hw->mac_type == e1000_82547 ||

   134

		    hw->mac_type == e1000_82547_rev_2)

   135

			hw->phy_type = e1000_phy_igp;

   136

		break;

   137

	case RTL8211B_PHY_ID:

   138

		hw->phy_type = e1000_phy_8211;

   139

		break;

   140

	case RTL8201N_PHY_ID:

   141

		hw->phy_type = e1000_phy_8201;

   142

		break;

   143

	default:

   144

		/* Should never have loaded on this device */

   145

		hw->phy_type = e1000_phy_undefined;

   146

		return -E1000_ERR_PHY_TYPE;

   147

	}

   148

   149

	return E1000_SUCCESS;

   150

}

   151

   152

/**

   153

 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   154

 * @hw: Struct containing variables accessed by shared code

   155

 */

   156

static void e1000_phy_init_script(struct e1000_hw *hw)

   157

{

   158

	u32 ret_val __attribute__ ((unused));

   159

	u16 phy_saved_data;

   160

   161

	e_dbg("e1000_phy_init_script");

   162

   163

	if (hw->phy_init_script) {

   164

		msleep(20);

   165

   166

		/* Save off the current value of register 0x2F5B to be restored at

   167

		 * the end of this routine. */

   168

		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   169

   170

		/* Disabled the PHY transmitter */

   171

		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   172

		msleep(20);

   173

   174

		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   175

		msleep(5);

   176

   177

		switch (hw->mac_type) {

   178

		case e1000_82541:

   179

		case e1000_82547:

   180

			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   181

			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   182

			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   183

			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   184

			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   185

			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   186

			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   187

			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   188

			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   189

			break;

   190

   191

		case e1000_82541_rev_2:

   192

		case e1000_82547_rev_2:

   193

			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   194

			break;

   195

		default:

   196

			break;

   197

		}

   198

   199

		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   200

		msleep(20);

   201

   202

		/* Now enable the transmitter */

   203

		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   204

   205

		if (hw->mac_type == e1000_82547) {

   206

			u16 fused, fine, coarse;

   207

   208

			/* Move to analog registers page */

   209

			e1000_read_phy_reg(hw,

   210

					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   211

					   &fused);

   212

   213

			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   214

				e1000_read_phy_reg(hw,

   215

						   IGP01E1000_ANALOG_FUSE_STATUS,

   216

						   &fused);

   217

   218

				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   219

				coarse =

   220

				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   221

   222

				if (coarse >

   223

				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   224

					coarse -=

   225

					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   226

					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   227

				} else if (coarse ==

   228

					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   229

					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   230

   231

				fused =

   232

				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   233

				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   234

				    (coarse &

   235

				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   236

   237

				e1000_write_phy_reg(hw,

   238

						    IGP01E1000_ANALOG_FUSE_CONTROL,

   239

						    fused);

   240

				e1000_write_phy_reg(hw,

   241

						    IGP01E1000_ANALOG_FUSE_BYPASS,

   242

						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   243

			}

   244

		}

   245

	}

   246

}

   247

   248

/**

   249

 * e1000_set_mac_type - Set the mac type member in the hw struct.

   250

 * @hw: Struct containing variables accessed by shared code

   251

 */

   252

s32 e1000_set_mac_type(struct e1000_hw *hw)

   253

{

   254

	e_dbg("e1000_set_mac_type");

   255

   256

	switch (hw->device_id) {

   257

	case E1000_DEV_ID_82542:

   258

		switch (hw->revision_id) {

   259

		case E1000_82542_2_0_REV_ID:

   260

			hw->mac_type = e1000_82542_rev2_0;

   261

			break;

   262

		case E1000_82542_2_1_REV_ID:

   263

			hw->mac_type = e1000_82542_rev2_1;

   264

			break;

   265

		default:

   266

			/* Invalid 82542 revision ID */

   267

			return -E1000_ERR_MAC_TYPE;

   268

		}

   269

		break;

   270

	case E1000_DEV_ID_82543GC_FIBER:

   271

	case E1000_DEV_ID_82543GC_COPPER:

   272

		hw->mac_type = e1000_82543;

   273

		break;

   274

	case E1000_DEV_ID_82544EI_COPPER:

   275

	case E1000_DEV_ID_82544EI_FIBER:

   276

	case E1000_DEV_ID_82544GC_COPPER:

   277

	case E1000_DEV_ID_82544GC_LOM:

   278

		hw->mac_type = e1000_82544;

   279

		break;

   280

	case E1000_DEV_ID_82540EM:

   281

	case E1000_DEV_ID_82540EM_LOM:

   282

	case E1000_DEV_ID_82540EP:

   283

	case E1000_DEV_ID_82540EP_LOM:

   284

	case E1000_DEV_ID_82540EP_LP:

   285

		hw->mac_type = e1000_82540;

   286

		break;

   287

	case E1000_DEV_ID_82545EM_COPPER:

   288

	case E1000_DEV_ID_82545EM_FIBER:

   289

		hw->mac_type = e1000_82545;

   290

		break;

   291

	case E1000_DEV_ID_82545GM_COPPER:

   292

	case E1000_DEV_ID_82545GM_FIBER:

   293

	case E1000_DEV_ID_82545GM_SERDES:

   294

		hw->mac_type = e1000_82545_rev_3;

   295

		break;

   296

	case E1000_DEV_ID_82546EB_COPPER:

   297

	case E1000_DEV_ID_82546EB_FIBER:

   298

	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   299

		hw->mac_type = e1000_82546;

   300

		break;

   301

	case E1000_DEV_ID_82546GB_COPPER:

   302

	case E1000_DEV_ID_82546GB_FIBER:

   303

	case E1000_DEV_ID_82546GB_SERDES:

   304

	case E1000_DEV_ID_82546GB_PCIE:

   305

	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   306

	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   307

		hw->mac_type = e1000_82546_rev_3;

   308

		break;

   309

	case E1000_DEV_ID_82541EI:

   310

	case E1000_DEV_ID_82541EI_MOBILE:

   311

	case E1000_DEV_ID_82541ER_LOM:

   312

		hw->mac_type = e1000_82541;

   313

		break;

   314

	case E1000_DEV_ID_82541ER:

   315

	case E1000_DEV_ID_82541GI:

   316

	case E1000_DEV_ID_82541GI_LF:

   317

	case E1000_DEV_ID_82541GI_MOBILE:

   318

		hw->mac_type = e1000_82541_rev_2;

   319

		break;

   320

	case E1000_DEV_ID_82547EI:

   321

	case E1000_DEV_ID_82547EI_MOBILE:

   322

		hw->mac_type = e1000_82547;

   323

		break;

   324

	case E1000_DEV_ID_82547GI:

   325

		hw->mac_type = e1000_82547_rev_2;

   326

		break;

   327

	case E1000_DEV_ID_INTEL_CE4100_GBE:

   328

		hw->mac_type = e1000_ce4100;

   329

		break;

   330

	default:

   331

		/* Should never have loaded on this device */

   332

		return -E1000_ERR_MAC_TYPE;

   333

	}

   334

   335

	switch (hw->mac_type) {

   336

	case e1000_82541:

   337

	case e1000_82547:

   338

	case e1000_82541_rev_2:

   339

	case e1000_82547_rev_2:

   340

		hw->asf_firmware_present = true;

   341

		break;

   342

	default:

   343

		break;

   344

	}

   345

   346

	/* The 82543 chip does not count tx_carrier_errors properly in

   347

	 * FD mode

   348

	 */

   349

	if (hw->mac_type == e1000_82543)

   350

		hw->bad_tx_carr_stats_fd = true;

   351

   352

	if (hw->mac_type > e1000_82544)

   353

		hw->has_smbus = true;

   354

   355

	return E1000_SUCCESS;

   356

}

   357

   358

/**

   359

 * e1000_set_media_type - Set media type and TBI compatibility.

   360

 * @hw: Struct containing variables accessed by shared code

   361

 */

   362

void e1000_set_media_type(struct e1000_hw *hw)

   363

{

   364

	u32 status;

   365

   366

	e_dbg("e1000_set_media_type");

   367

   368

	if (hw->mac_type != e1000_82543) {

   369

		/* tbi_compatibility is only valid on 82543 */

   370

		hw->tbi_compatibility_en = false;

   371

	}

   372

   373

	switch (hw->device_id) {

   374

	case E1000_DEV_ID_82545GM_SERDES:

   375

	case E1000_DEV_ID_82546GB_SERDES:

   376

		hw->media_type = e1000_media_type_internal_serdes;

   377

		break;

   378

	default:

   379

		switch (hw->mac_type) {

   380

		case e1000_82542_rev2_0:

   381

		case e1000_82542_rev2_1:

   382

			hw->media_type = e1000_media_type_fiber;

   383

			break;

   384

		case e1000_ce4100:

   385

			hw->media_type = e1000_media_type_copper;

   386

			break;

   387

		default:

   388

			status = er32(STATUS);

   389

			if (status & E1000_STATUS_TBIMODE) {

   390

				hw->media_type = e1000_media_type_fiber;

   391

				/* tbi_compatibility not valid on fiber */

   392

				hw->tbi_compatibility_en = false;

   393

			} else {

   394

				hw->media_type = e1000_media_type_copper;

   395

			}

   396

			break;

   397

		}

   398

	}

   399

}

   400

   401

/**

   402

 * e1000_reset_hw: reset the hardware completely

   403

 * @hw: Struct containing variables accessed by shared code

   404

 *

   405

 * Reset the transmit and receive units; mask and clear all interrupts.

   406

 */

   407

s32 e1000_reset_hw(struct e1000_hw *hw)

   408

{

   409

	u32 ctrl;

   410

	u32 ctrl_ext;

   411

	u32 icr __attribute__ ((unused));

   412

	u32 manc;

   413

	u32 led_ctrl;

   414

	s32 ret_val;

   415

   416

	e_dbg("e1000_reset_hw");

   417

   418

	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   419

	if (hw->mac_type == e1000_82542_rev2_0) {

   420

		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   421

		e1000_pci_clear_mwi(hw);

   422

	}

   423

   424

	/* Clear interrupt mask to stop board from generating interrupts */

   425

	e_dbg("Masking off all interrupts\n");

   426

	ew32(IMC, 0xffffffff);

   427

   428

	/* Disable the Transmit and Receive units.  Then delay to allow

   429

	 * any pending transactions to complete before we hit the MAC with

   430

	 * the global reset.

   431

	 */

   432

	ew32(RCTL, 0);

   433

	ew32(TCTL, E1000_TCTL_PSP);

   434

	E1000_WRITE_FLUSH();

   435

   436

	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   437

	hw->tbi_compatibility_on = false;

   438

   439

	/* Delay to allow any outstanding PCI transactions to complete before

   440

	 * resetting the device

   441

	 */

   442

	msleep(10);

   443

   444

	ctrl = er32(CTRL);

   445

   446

	/* Must reset the PHY before resetting the MAC */

   447

	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   448

		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   449

		E1000_WRITE_FLUSH();

   450

		msleep(5);

   451

	}

   452

   453

	/* Issue a global reset to the MAC.  This will reset the chip's

   454

	 * transmit, receive, DMA, and link units.  It will not effect

   455

	 * the current PCI configuration.  The global reset bit is self-

   456

	 * clearing, and should clear within a microsecond.

   457

	 */

   458

	e_dbg("Issuing a global reset to MAC\n");

   459

   460

	switch (hw->mac_type) {

   461

	case e1000_82544:

   462

	case e1000_82540:

   463

	case e1000_82545:

   464

	case e1000_82546:

   465

	case e1000_82541:

   466

	case e1000_82541_rev_2:

   467

		/* These controllers can't ack the 64-bit write when issuing the

   468

		 * reset, so use IO-mapping as a workaround to issue the reset */

   469

		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   470

		break;

   471

	case e1000_82545_rev_3:

   472

	case e1000_82546_rev_3:

   473

		/* Reset is performed on a shadow of the control register */

   474

		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   475

		break;

   476

	case e1000_ce4100:

   477

	default:

   478

		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   479

		break;

   480

	}

   481

   482

	/* After MAC reset, force reload of EEPROM to restore power-on settings to

   483

	 * device.  Later controllers reload the EEPROM automatically, so just wait

   484

	 * for reload to complete.

   485

	 */

   486

	switch (hw->mac_type) {

   487

	case e1000_82542_rev2_0:

   488

	case e1000_82542_rev2_1:

   489

	case e1000_82543:

   490

	case e1000_82544:

   491

		/* Wait for reset to complete */

   492

		udelay(10);

   493

		ctrl_ext = er32(CTRL_EXT);

   494

		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   495

		ew32(CTRL_EXT, ctrl_ext);

   496

		E1000_WRITE_FLUSH();

   497

		/* Wait for EEPROM reload */

   498

		msleep(2);

   499

		break;

   500

	case e1000_82541:

   501

	case e1000_82541_rev_2:

   502

	case e1000_82547:

   503

	case e1000_82547_rev_2:

   504

		/* Wait for EEPROM reload */

   505

		msleep(20);

   506

		break;

   507

	default:

   508

		/* Auto read done will delay 5ms or poll based on mac type */

   509

		ret_val = e1000_get_auto_rd_done(hw);

   510

		if (ret_val)

   511

			return ret_val;

   512

		break;

   513

	}

   514

   515

	/* Disable HW ARPs on ASF enabled adapters */

   516

	if (hw->mac_type >= e1000_82540) {

   517

		manc = er32(MANC);

   518

		manc &= ~(E1000_MANC_ARP_EN);

   519

		ew32(MANC, manc);

   520

	}

   521

   522

	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   523

		e1000_phy_init_script(hw);

   524

   525

		/* Configure activity LED after PHY reset */

   526

		led_ctrl = er32(LEDCTL);

   527

		led_ctrl &= IGP_ACTIVITY_LED_MASK;

   528

		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   529

		ew32(LEDCTL, led_ctrl);

   530

	}