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/**

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    Network Driver for Beckhoff CCAT communication controller

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    Copyright (C) 2014  Beckhoff Automation GmbH

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    Author: Patrick Bruenn <p.bruenn@beckhoff.com>

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    This program is free software; you can redistribute it and/or modify

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    it under the terms of the GNU General Public License as published by

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    the Free Software Foundation; either version 2 of the License, or

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    (at your option) any later version.

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    This program is distributed in the hope that it will be useful,

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    but WITHOUT ANY WARRANTY; without even the implied warranty of

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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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    GNU General Public License for more details.

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    You should have received a copy of the GNU General Public License along

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    with this program; if not, write to the Free Software Foundation, Inc.,

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    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

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*/

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#include <linux/kernel.h>

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#include "CCatDefinitions.h"

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#include "module.h"

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#include "print.h"

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#define TESTING_ENABLED 1

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void print_mem(const unsigned char *p, size_t lines)

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{

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#if TESTING_ENABLED

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	pr_info("mem at: %p\n", p);

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	pr_info(" 0  1  2  3  4  5  6  7   8  9  A  B  C  D  E  F\n");

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	while (lines > 0) {

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		pr_info

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		    ("%02x %02x %02x %02x %02x %02x %02x %02x  %02x %02x %02x %02x %02x %02x %02x %02x\n",

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		     p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8], p[9],

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		     p[10], p[11], p[12], p[13], p[14], p[15]);

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		p += 16;

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		--lines;

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	}

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#endif /* #if TESTING_ENABLED */

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}

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static const char *CCatFunctionTypes[CCATINFO_MAX + 1] = {

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	"not used",

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	"Informationblock",

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	"EtherCAT Slave",

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	"EtherCAT Master without DMA",

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	"Ethernet MAC without DMA",

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	"Ethernet Switch",

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	"Sercos III",

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	"Profibus",

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	"CAN Controller",

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	"KBUS Master",

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	"IP-Link Master (planned)",

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	"SPI Master",

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	"I²C",

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	"GPIO",

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	"Drive",

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	"CCAT Update",

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	"Systemtime",

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	"Interrupt Controller",

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	"EEPROM Controller",

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	"DMA Controller",

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	"EtherCAT Master with DMA",

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	"Ethernet MAC with DMA",

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	"SRAM Interface",

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	"Internal Copy block",

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	"unknown"

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};

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static void print_CCatDmaRxActBuf(const struct ccat_eth_priv *const priv)

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{

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	CCatDmaRxActBuf rx_fifo;

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	memcpy_fromio(&rx_fifo, priv->reg.rx_fifo, sizeof(rx_fifo));

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	pr_debug("Rx FIFO base address: %p\n", priv->reg.rx_fifo);

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	pr_debug("     Rx Frame Header start:   0x%08x\n", rx_fifo.startAddr);

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	pr_debug("     reserved:                0x%08x\n", rx_fifo.reserved1);

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	pr_debug("     Rx start address valid:    %8u\n", rx_fifo.nextValid);

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	pr_debug("     reserved:                0x%08x\n", rx_fifo.reserved2);

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	pr_debug("     FIFO level:              0x%08x\n", rx_fifo.FifoLevel);

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	pr_debug("     Buffer level:            0x%08x\n", rx_fifo.bufferLevel);

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	pr_debug("     next address:            0x%08x\n", rx_fifo.nextAddr);

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}

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static void print_CCatDmaTxFifo(const struct ccat_eth_priv *const priv)

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{

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	CCatDmaTxFifo tx_fifo;

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	memcpy_fromio(&tx_fifo, priv->reg.tx_fifo, sizeof(tx_fifo));

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	pr_debug("Tx FIFO base address: %p\n", priv->reg.tx_fifo);

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	pr_debug("     Tx Frame Header start:   0x%08x\n", tx_fifo.startAddr);

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	pr_debug("     # 64 bit words:          %10d\n", tx_fifo.numQuadWords);

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	pr_debug("     reserved:                0x%08x\n", tx_fifo.reserved1);

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	pr_debug("     FIFO reset:              0x%08x\n", tx_fifo.fifoReset);

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}

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static void print_CCatInfoBlock(const CCatInfoBlock * info,

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				const void __iomem * const base_addr)

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{

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	const size_t index = min((int)info->eCCatInfoType, CCATINFO_MAX);

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	pr_debug("%s\n", CCatFunctionTypes[index]);

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	pr_debug("     revision:     0x%x\n", info->nRevision);

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	pr_debug("     RX channel:   %d\n", info->rxDmaChn);

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	pr_debug("     TX channel:   %d\n", info->txDmaChn);

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	pr_debug("     baseaddr:     0x%x\n", info->nAddr);

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	pr_debug("     size:         0x%x\n", info->nSize);

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	pr_debug("     subfunction:  %p\n", base_addr);

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}

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static void print_CCatMacRegs(const struct ccat_eth_priv *const priv)

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{

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	CCatMacRegs mac;

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	memcpy_fromio(&mac, priv->reg.mac, sizeof(mac));

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	pr_debug("MAC base address: %p\n", priv->reg.mac);

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	pr_debug("     frame length error count:   %10d\n", mac.frameLenErrCnt);

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	pr_debug("     RX error count:             %10d\n", mac.rxErrCnt);

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	pr_debug("     CRC error count:            %10d\n", mac.crcErrCnt);

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	pr_debug("     Link lost error count:      %10d\n", mac.linkLostErrCnt);

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	pr_debug("     reserved:                   0x%08x\n", mac.reserved1);

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	pr_debug("     RX overflow count:          %10d\n",

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		 mac.dropFrameErrCnt);

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	pr_debug("     DMA overflow count:         %10d\n", mac.reserved2[0]);

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	//pr_debug("     reserverd:         %10d\n", DRV_NAME, mac.reserved2[1]);

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	pr_debug("     TX frame counter:           %10d\n", mac.txFrameCnt);

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	pr_debug("     RX frame counter:           %10d\n", mac.rxFrameCnt);

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	pr_debug("     TX-FIFO level:              0x%08x\n", mac.txFifoLevel);

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	pr_debug("     MII connection:             0x%08x\n", mac.miiConnected);

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}

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static void print_CCatMii(const struct ccat_eth_priv *const priv)

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{

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	CCatMii mii;

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	memcpy_fromio(&mii, priv->reg.mii, sizeof(mii));

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	pr_debug("MII base address: %p\n", priv->reg.mii);

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	pr_debug("     MII cycle:    %s\n",

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		 mii.startMiCycle ? "running" : "no cycle");

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	pr_debug("     reserved:     0x%x\n", mii.reserved1);

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	pr_debug("     cmd valid:    %s\n", mii.cmdErr ? "no" : "yes");

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	pr_debug("     cmd:          0x%x\n", mii.cmd);

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	pr_debug("     reserved:     0x%x\n", mii.reserved2);

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	pr_debug("     PHY addr:     0x%x\n", mii.phyAddr);

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	pr_debug("     reserved:     0x%x\n", mii.reserved3);

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	pr_debug("     PHY reg:      0x%x\n", mii.phyReg);

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	pr_debug("     reserved:     0x%x\n", mii.reserved4);

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	pr_debug("     PHY write:    0x%x\n", mii.phyWriteData);

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	pr_debug("     PHY read:     0x%x\n", mii.phyReadData);

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	pr_debug("     MAC addr:     %02x:%02x:%02x:%02x:%02x:%02x\n",

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		 mii.macAddr.b[0], mii.macAddr.b[1], mii.macAddr.b[2],

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		 mii.macAddr.b[3], mii.macAddr.b[4], mii.macAddr.b[5]);

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	pr_debug("     MAC filter enable:   %s\n",

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		 mii.macFilterEnabled ? "enabled" : "disabled");

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	pr_debug("     reserved:     0x%x\n", mii.reserved6);

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	pr_debug("     Link State:   %s\n",

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		 mii.linkStatus ? "link" : "no link");

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	pr_debug("     reserved:     0x%x\n", mii.reserved7);

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	//pr_debug("     reserved:     0x%x\n", DRV_NAME, mii.reserved8);

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	//TODO add leds, systemtime insertion and interrupts

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}

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void ccat_print_function_info(struct ccat_eth_priv *priv)

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{

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	print_CCatInfoBlock(&priv->info, priv->ccatdev->bar[0].ioaddr);

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	print_CCatMii(priv);

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	print_CCatDmaTxFifo(priv);

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	print_CCatDmaRxActBuf(priv);

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	print_CCatMacRegs(priv);

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	pr_debug("  RX window:    %p\n", priv->reg.rx_mem);

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	pr_debug("  TX memory:    %p\n", priv->reg.tx_mem);

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	pr_debug("  misc:         %p\n", priv->reg.misc);

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}

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void print_update_info(const CCatInfoBlock * const info,

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		       void __iomem * const ioaddr)

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{

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	const size_t index = min((int)info->eCCatInfoType, CCATINFO_MAX);

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	pr_debug("%s\n", CCatFunctionTypes[index]);

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	pr_debug("     revision:     0x%x\n", info->nRevision);

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	pr_debug("     baseaddr:     0x%x\n", info->nAddr);

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	pr_debug("     size:         0x%x\n", info->nSize);

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	pr_debug("     PROM ID is:   0x%x\n", ccat_get_prom_id(ioaddr));

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}