1

/******************************************************************************

     2

 *

     3

 *  drv_8139too.c

     4

 *

     5

 *  EtherCAT-Treiber für RTL8139-kompatible Netzwerkkarten.

     6

 *

     7

 *  Autoren: Wilhelm Hagemeister, Florian Pose

     8

 *

     9

 *  $Date$

    10

 *  $Author$

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 *

    12

 *  (C) Copyright IgH 2005

    13

 *  Ingenieurgemeinschaft IgH

    14

 *  Heinz-Bäcker Str. 34

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 *  D-45356 Essen

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 *  Tel.: +49 201/61 99 31

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 *  Fax.: +49 201/61 98 36

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 *  E-mail: sp@igh-essen.com

    19

 *

    20

 ******************************************************************************/

    21

    22

/*

    23

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    24

    25

	Maintained by Jeff Garzik <jgarzik@pobox.com>

    26

	Copyright 2000-2002 Jeff Garzik

    27

    28

	Much code comes from Donald Becker's rtl8139.c driver,

    29

	versions 1.13 and older.  This driver was originally based

    30

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    31

    32

	-----<snip>-----

    33

    34

        	Written 1997-2001 by Donald Becker.

    35

		This software may be used and distributed according to the

    36

		terms of the GNU General Public License (GPL), incorporated

    37

		herein by reference.  Drivers based on or derived from this

    38

		code fall under the GPL and must retain the authorship,

    39

		copyright and license notice.  This file is not a complete

    40

		program and may only be used when the entire operating

    41

		system is licensed under the GPL.

    42

    43

		This driver is for boards based on the RTL8129 and RTL8139

    44

		PCI ethernet chips.

    45

    46

		The author may be reached as becker@scyld.com, or C/O Scyld

    47

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

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		MD 21403

    49

    50

		Support and updates available at

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		http://www.scyld.com/network/rtl8139.html

    52

    53

		Twister-tuning table provided by Kinston

    54

		<shangh@realtek.com.tw>.

    55

    56

	-----<snip>-----

    57

    58

	This software may be used and distributed according to the terms

    59

	of the GNU General Public License, incorporated herein by reference.

    60

    61

	Contributors:

    62

    63

		Donald Becker - he wrote the original driver, kudos to him!

    64

		(but please don't e-mail him for support, this isn't his driver)

    65

    66

		Tigran Aivazian - bug fixes, skbuff free cleanup

    67

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		Martin Mares - suggestions for PCI cleanup

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		David S. Miller - PCI DMA and softnet updates

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    72

		Ernst Gill - fixes ported from BSD driver

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		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

    76

    77

		Gerard Sharp - bug fix, testing and feedback

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    79

		David Ford - Rx ring wrap fix

    80

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		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    82

		to find and fix a crucial bug on older chipsets.

    83

    84

		Donald Becker/Chris Butterworth/Marcus Westergren -

    85

		Noticed various Rx packet size-related buglets.

    86

    87

		Santiago Garcia Mantinan - testing and feedback

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		Jens David - 2.2.x kernel backports

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		Martin Dennett - incredibly helpful insight on undocumented

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		features of the 8139 chips

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		Jean-Jacques Michel - bug fix

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		Tobias Ringström - Rx interrupt status checking suggestion

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		Andrew Morton - Clear blocked signals, avoid

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		buffer overrun setting current->comm.

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		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

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		"rtl8139-diag -mmmaaavvveefN" output

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		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

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   110

*/

   111

   112

#define DRV_NAME	"8139too_ec"

   113

#define DRV_VERSION	"0.9.27"

   114

   115

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#include <linux/config.h>

   117

#include <linux/module.h>

   118

#include <linux/kernel.h>

   119

#include <linux/compiler.h>

   120

#include <linux/pci.h>

   121

#include <linux/init.h>

   122

#include <linux/ioport.h>

   123

#include <linux/netdevice.h>

   124

#include <linux/etherdevice.h>

   125

#include <linux/rtnetlink.h>

   126

#include <linux/delay.h>

   127

#include <linux/ethtool.h>

   128

#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <asm/io.h>

   132

#include <asm/uaccess.h>

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#include <asm/irq.h>

   134

   135

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   136

   137

#include "../include/EtherCAT_dev.h"

   138

   139

#define LIT(X) #X

   140

#define STR(X) LIT(X)

   141

   142

#define COMPILE_INFO "Revision " STR(EC_REV) \

   143

                     ", compiled by " STR(EC_USER) \

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                     " at " STR(EC_DATE)

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   146

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   147

   148

#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   149

#define PFX DRV_NAME ": "

   150

   151

/* Default Message level */

   152

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   153

                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

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   156

   157

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   158

#ifdef CONFIG_8139TOO_PIO

   159

#define USE_IO_OPS 1

   160

#endif

   161

   162

/* define to 1, 2 or 3 to enable copious debugging info */

   163

#define RTL8139_DEBUG 0

   164

   165

/* define to 1 to disable lightweight runtime debugging checks */

   166

#undef RTL8139_NDEBUG

   167

   168

   169

#if RTL8139_DEBUG

   170

/* note: prints function name for you */

   171

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   172

#else

   173

#  define DPRINTK(fmt, args...)

   174

#endif

   175

   176

#ifdef RTL8139_NDEBUG

   177

#  define assert(expr) do {} while (0)

   178

#else

   179

#  define assert(expr) \

   180

        if(unlikely(!(expr))) {				        \

   181

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

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        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   183

        }

   184

#endif

   185

   186

   187

/* A few user-configurable values. */

   188

/* media options */

   189

#define MAX_UNITS 8

   190

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   191

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   192

   193

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   194

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   195

static int multicast_filter_limit = 32;

   196

   197

/* bitmapped message enable number */

   198

static int debug = -1;

   199

   200

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   201

   202

// Uncomment for debugging

   203

//#define EC_DEBUG

   204

   205

// Device index for EtherCAT device selection

   206

static int ec_device_index = -1;

   207

static int ec_device_master_index = 0;

   208

   209

static ec_device_t *rtl_ec_dev;

   210

int rtl_ec_dev_registered = 0;

   211

   212

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   213

   214

/*

   215

 * Receive ring size 

   216

 * Warning: 64K ring has hardware issues and may lock up.

   217

 */

   218

#if defined(CONFIG_SH_DREAMCAST)

   219

#define RX_BUF_IDX	1	/* 16K ring */

   220

#else

   221

#define RX_BUF_IDX	2	/* 32K ring */

   222

#endif

   223

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   224

#define RX_BUF_PAD	16

   225

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   226

   227

#if RX_BUF_LEN == 65536

   228

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   229

#else

   230

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   231

#endif

   232

   233

/* Number of Tx descriptor registers. */

   234

#define NUM_TX_DESC	4

   235

   236

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   237

#define MAX_ETH_FRAME_SIZE	1536

   238

   239

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   240

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   241

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   242

   243

/* PCI Tuning Parameters

   244

   Threshold is bytes transferred to chip before transmission starts. */

   245

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   246

   247

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   248

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   249

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   250

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   251

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   252

   253

/* Operational parameters that usually are not changed. */

   254

/* Time in jiffies before concluding the transmitter is hung. */

   255

#define TX_TIMEOUT  (6*HZ)

   256

   257

   258

enum {

   259

	HAS_MII_XCVR = 0x010000,

   260

	HAS_CHIP_XCVR = 0x020000,

   261

	HAS_LNK_CHNG = 0x040000,

   262

};

   263

   264

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   265

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   266

#define RTL_MIN_IO_SIZE 0x80

   267

#define RTL8139B_IO_SIZE 256

   268

   269

#define RTL8129_CAPS	HAS_MII_XCVR

   270

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   271

   272

typedef enum {

   273

	RTL8139 = 0,

   274

	RTL8129,

   275

} board_t;

   276

   277

   278

/* indexed by board_t, above */

   279

static struct {

   280

	const char *name;

   281

	u32 hw_flags;

   282

} board_info[] __devinitdata = {

   283

	{ "RealTek RTL8139", RTL8139_CAPS },

   284

	{ "RealTek RTL8129", RTL8129_CAPS },

   285

};

   286

   287

   288

static struct pci_device_id rtl8139_pci_tbl[] = {

   289

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 

   308

   309

#ifdef CONFIG_SH_SECUREEDGE5410

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	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

   313

#ifdef CONFIG_8139TOO_8129

   314

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   315

#endif

   316

   317

	/* some crazy cards report invalid vendor ids like

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	 * 0x0001 here.  The other ids are valid and constant,

   319

	 * so we simply don't match on the main vendor id.

   320

	 */

   321

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   324

   325

	{0,}

   326

};

   327

MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   328

   329

static struct {

   330

	const char str[ETH_GSTRING_LEN];

   331

} ethtool_stats_keys[] = {

   332

	{ "early_rx" },

   333

	{ "tx_buf_mapped" },

   334

	{ "tx_timeouts" },

   335

	{ "rx_lost_in_ring" },

   336

};

   337

   338

/* The rest of these values should never change. */

   339

   340

/* Symbolic offsets to registers. */

   341

enum RTL8139_registers {

   342

	MAC0 = 0,		/* Ethernet hardware address. */

   343

	MAR0 = 8,		/* Multicast filter. */

   344

	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   345

	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   346

	RxBuf = 0x30,

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	ChipCmd = 0x37,

   348

	RxBufPtr = 0x38,

   349

	RxBufAddr = 0x3A,

   350

	IntrMask = 0x3C,

   351

	IntrStatus = 0x3E,

   352

	TxConfig = 0x40,

   353

	RxConfig = 0x44,

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	Timer = 0x48,		/* A general-purpose counter. */

   355

	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   356

	Cfg9346 = 0x50,

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	Config0 = 0x51,

   358

	Config1 = 0x52,

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	FlashReg = 0x54,

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	MediaStatus = 0x58,

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	Config3 = 0x59,

   362

	Config4 = 0x5A,		/* absent on RTL-8139A */

   363

	HltClk = 0x5B,

   364

	MultiIntr = 0x5C,

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	TxSummary = 0x60,

   366

	BasicModeCtrl = 0x62,

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	BasicModeStatus = 0x64,

   368

	NWayAdvert = 0x66,

   369

	NWayLPAR = 0x68,

   370

	NWayExpansion = 0x6A,

   371

	/* Undocumented registers, but required for proper operation. */

   372

	FIFOTMS = 0x70,		/* FIFO Control and test. */

   373

	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   374

	PARA78 = 0x78,

   375

	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   376

	Config5 = 0xD8,		/* absent on RTL-8139A */

   377

};

   378

   379

enum ClearBitMasks {

   380

	MultiIntrClear = 0xF000,

   381

	ChipCmdClear = 0xE2,

   382

	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   383

};

   384

   385

enum ChipCmdBits {

   386

	CmdReset = 0x10,

   387

	CmdRxEnb = 0x08,

   388

	CmdTxEnb = 0x04,

   389

	RxBufEmpty = 0x01,

   390

};

   391

   392

/* Interrupt register bits, using my own meaningful names. */

   393

enum IntrStatusBits {

   394

	PCIErr = 0x8000,

   395

	PCSTimeout = 0x4000,

   396

	RxFIFOOver = 0x40,

   397

	RxUnderrun = 0x20,

   398

	RxOverflow = 0x10,

   399

	TxErr = 0x08,

   400

	TxOK = 0x04,

   401

	RxErr = 0x02,

   402

	RxOK = 0x01,

   403

   404

	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   405

};

   406

   407

enum TxStatusBits {

   408

	TxHostOwns = 0x2000,

   409

	TxUnderrun = 0x4000,

   410

	TxStatOK = 0x8000,

   411

	TxOutOfWindow = 0x20000000,

   412

	TxAborted = 0x40000000,

   413

	TxCarrierLost = 0x80000000,

   414

};

   415

enum RxStatusBits {

   416

	RxMulticast = 0x8000,

   417

	RxPhysical = 0x4000,

   418

	RxBroadcast = 0x2000,

   419

	RxBadSymbol = 0x0020,

   420

	RxRunt = 0x0010,

   421

	RxTooLong = 0x0008,

   422

	RxCRCErr = 0x0004,

   423

	RxBadAlign = 0x0002,

   424

	RxStatusOK = 0x0001,

   425

};

   426

   427

/* Bits in RxConfig. */

   428

enum rx_mode_bits {

   429

	AcceptErr = 0x20,

   430

	AcceptRunt = 0x10,

   431

	AcceptBroadcast = 0x08,

   432

	AcceptMulticast = 0x04,

   433

	AcceptMyPhys = 0x02,

   434

	AcceptAllPhys = 0x01,

   435

};

   436

   437

/* Bits in TxConfig. */

   438

enum tx_config_bits {

   439

   440

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   441

        TxIFGShift = 24,

   442

        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   443

        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   444

        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   445

        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   446

   447

	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   448

	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   449

	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   450

	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   451

	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   452

   453

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   454

};

   455

   456

/* Bits in Config1 */

   457

enum Config1Bits {

   458

	Cfg1_PM_Enable = 0x01,

   459

	Cfg1_VPD_Enable = 0x02,

   460

	Cfg1_PIO = 0x04,

   461

	Cfg1_MMIO = 0x08,

   462

	LWAKE = 0x10,		/* not on 8139, 8139A */

   463

	Cfg1_Driver_Load = 0x20,

   464

	Cfg1_LED0 = 0x40,

   465

	Cfg1_LED1 = 0x80,

   466

	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   467

	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   468

};

   469

   470

/* Bits in Config3 */

   471

enum Config3Bits {

   472

	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   473

	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   474

	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   475

	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   476

	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   477

	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   478

	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   479

	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   480

};

   481

   482

/* Bits in Config4 */

   483

enum Config4Bits {

   484

	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   485

};

   486

   487

/* Bits in Config5 */

   488

enum Config5Bits {

   489

	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   490

	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   491

	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   492

	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   493

	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   494

	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   495

	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   496

};

   497

   498

enum RxConfigBits {

   499

	/* rx fifo threshold */

   500

	RxCfgFIFOShift = 13,

   501

	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   502

   503

	/* Max DMA burst */

   504

	RxCfgDMAShift = 8,

   505

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   506

   507

	/* rx ring buffer length */

   508

	RxCfgRcv8K = 0,

   509

	RxCfgRcv16K = (1 << 11),

   510

	RxCfgRcv32K = (1 << 12),

   511

	RxCfgRcv64K = (1 << 11) | (1 << 12),

   512

   513

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   514

	RxNoWrap = (1 << 7),

   515

};

   516

   517

/* Twister tuning parameters from RealTek.

   518

   Completely undocumented, but required to tune bad links on some boards. */

   519

enum CSCRBits {

   520

	CSCR_LinkOKBit = 0x0400,

   521

	CSCR_LinkChangeBit = 0x0800,

   522

	CSCR_LinkStatusBits = 0x0f000,

   523

	CSCR_LinkDownOffCmd = 0x003c0,

   524

	CSCR_LinkDownCmd = 0x0f3c0,

   525

};

   526

   527

enum Cfg9346Bits {