1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2006 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

 */

    28

    29

/* e1000_hw.c

    30

 * Shared functions for accessing and configuring the MAC

    31

 */

    32

    33

#include "e1000-3.8-ethercat.h"

    34

    35

static s32 e1000_check_downshift(struct e1000_hw *hw);

    36

static s32 e1000_check_polarity(struct e1000_hw *hw,

    37

				e1000_rev_polarity *polarity);

    38

static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39

static void e1000_clear_vfta(struct e1000_hw *hw);

    40

static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41

					      bool link_up);

    42

static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43

static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44

static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45

static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46

				  u16 *max_length);

    47

static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48

static s32 e1000_id_led_init(struct e1000_hw *hw);

    49

static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50

static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51

				  struct e1000_phy_info *phy_info);

    52

static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53

				  struct e1000_phy_info *phy_info);

    54

static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55

static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56

static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57

static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58

static void e1000_phy_init_script(struct e1000_hw *hw);

    59

static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60

static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61

static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62

static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63

static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64

static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65

static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66

static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67

static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68

static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69

static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70

				  u16 words, u16 *data);

    71

static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72

					u16 words, u16 *data);

    73

static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74

static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75

static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76

static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77

static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78

				  u16 phy_data);

    79

static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    80

				 u16 *phy_data);

    81

static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82

static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83

static void e1000_release_eeprom(struct e1000_hw *hw);

    84

static void e1000_standby_eeprom(struct e1000_hw *hw);

    85

static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86

static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87

static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88

static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89

				u16 *data);

    90

static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91

				 u16 *data);

    92

    93

/* IGP cable length table */

    94

static const

    95

u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96

	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    97

	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98

	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99

	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100

	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101

	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102

	    100,

   103

	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104

	    110, 110,

   105

	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106

	    120, 120

   107

};

   108

   109

static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110

static DEFINE_SPINLOCK(e1000_phy_lock);

   111

   112

/**

   113

 * e1000_set_phy_type - Set the phy type member in the hw struct.

   114

 * @hw: Struct containing variables accessed by shared code

   115

 */

   116

static s32 e1000_set_phy_type(struct e1000_hw *hw)

   117

{

   118

	e_dbg("e1000_set_phy_type");

   119

   120

	if (hw->mac_type == e1000_undefined)

   121

		return -E1000_ERR_PHY_TYPE;

   122

   123

	switch (hw->phy_id) {

   124

	case M88E1000_E_PHY_ID:

   125

	case M88E1000_I_PHY_ID:

   126

	case M88E1011_I_PHY_ID:

   127

	case M88E1111_I_PHY_ID:

   128

	case M88E1118_E_PHY_ID:

   129

		hw->phy_type = e1000_phy_m88;

   130

		break;

   131

	case IGP01E1000_I_PHY_ID:

   132

		if (hw->mac_type == e1000_82541 ||

   133

		    hw->mac_type == e1000_82541_rev_2 ||

   134

		    hw->mac_type == e1000_82547 ||

   135

		    hw->mac_type == e1000_82547_rev_2)

   136

			hw->phy_type = e1000_phy_igp;

   137

		break;

   138

	case RTL8211B_PHY_ID:

   139

		hw->phy_type = e1000_phy_8211;

   140

		break;

   141

	case RTL8201N_PHY_ID:

   142

		hw->phy_type = e1000_phy_8201;

   143

		break;

   144

	default:

   145

		/* Should never have loaded on this device */

   146

		hw->phy_type = e1000_phy_undefined;

   147

		return -E1000_ERR_PHY_TYPE;

   148

	}

   149

   150

	return E1000_SUCCESS;

   151

}

   152

   153

/**

   154

 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   155

 * @hw: Struct containing variables accessed by shared code

   156

 */

   157

static void e1000_phy_init_script(struct e1000_hw *hw)

   158

{

   159

	u32 ret_val __attribute__ ((unused));

   160

	u16 phy_saved_data;

   161

   162

	e_dbg("e1000_phy_init_script");

   163

   164

	if (hw->phy_init_script) {

   165

		msleep(20);

   166

   167

		/* Save off the current value of register 0x2F5B to be restored at

   168

		 * the end of this routine. */

   169

		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   170

   171

		/* Disabled the PHY transmitter */

   172

		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   173

		msleep(20);

   174

   175

		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   176

		msleep(5);

   177

   178

		switch (hw->mac_type) {

   179

		case e1000_82541:

   180

		case e1000_82547:

   181

			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   182

			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   183

			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   184

			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   185

			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   186

			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   187

			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   188

			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   189

			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   190

			break;

   191

   192

		case e1000_82541_rev_2:

   193

		case e1000_82547_rev_2:

   194

			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   195

			break;

   196

		default:

   197

			break;

   198

		}

   199

   200

		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   201

		msleep(20);

   202

   203

		/* Now enable the transmitter */

   204

		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   205

   206

		if (hw->mac_type == e1000_82547) {

   207

			u16 fused, fine, coarse;

   208

   209

			/* Move to analog registers page */

   210

			e1000_read_phy_reg(hw,

   211

					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   212

					   &fused);

   213

   214

			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   215

				e1000_read_phy_reg(hw,

   216

						   IGP01E1000_ANALOG_FUSE_STATUS,

   217

						   &fused);

   218

   219

				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   220

				coarse =

   221

				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   222

   223

				if (coarse >

   224

				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   225

					coarse -=

   226

					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   227

					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   228

				} else if (coarse ==

   229

					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   230

					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   231

   232

				fused =

   233

				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   234

				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   235

				    (coarse &

   236

				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   237

   238

				e1000_write_phy_reg(hw,

   239

						    IGP01E1000_ANALOG_FUSE_CONTROL,

   240

						    fused);

   241

				e1000_write_phy_reg(hw,

   242

						    IGP01E1000_ANALOG_FUSE_BYPASS,

   243

						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   244

			}

   245

		}

   246

	}

   247

}

   248

   249

/**

   250

 * e1000_set_mac_type - Set the mac type member in the hw struct.

   251

 * @hw: Struct containing variables accessed by shared code

   252

 */

   253

s32 e1000_set_mac_type(struct e1000_hw *hw)

   254

{

   255

	e_dbg("e1000_set_mac_type");

   256

   257

	switch (hw->device_id) {

   258

	case E1000_DEV_ID_82542:

   259

		switch (hw->revision_id) {

   260

		case E1000_82542_2_0_REV_ID:

   261

			hw->mac_type = e1000_82542_rev2_0;

   262

			break;

   263

		case E1000_82542_2_1_REV_ID:

   264

			hw->mac_type = e1000_82542_rev2_1;

   265

			break;

   266

		default:

   267

			/* Invalid 82542 revision ID */

   268

			return -E1000_ERR_MAC_TYPE;

   269

		}

   270

		break;

   271

	case E1000_DEV_ID_82543GC_FIBER:

   272

	case E1000_DEV_ID_82543GC_COPPER:

   273

		hw->mac_type = e1000_82543;

   274

		break;

   275

	case E1000_DEV_ID_82544EI_COPPER:

   276

	case E1000_DEV_ID_82544EI_FIBER:

   277

	case E1000_DEV_ID_82544GC_COPPER:

   278

	case E1000_DEV_ID_82544GC_LOM:

   279

		hw->mac_type = e1000_82544;

   280

		break;

   281

	case E1000_DEV_ID_82540EM:

   282

	case E1000_DEV_ID_82540EM_LOM:

   283

	case E1000_DEV_ID_82540EP:

   284

	case E1000_DEV_ID_82540EP_LOM:

   285

	case E1000_DEV_ID_82540EP_LP:

   286

		hw->mac_type = e1000_82540;

   287

		break;

   288

	case E1000_DEV_ID_82545EM_COPPER:

   289

	case E1000_DEV_ID_82545EM_FIBER:

   290

		hw->mac_type = e1000_82545;

   291

		break;

   292

	case E1000_DEV_ID_82545GM_COPPER:

   293

	case E1000_DEV_ID_82545GM_FIBER:

   294

	case E1000_DEV_ID_82545GM_SERDES:

   295

		hw->mac_type = e1000_82545_rev_3;

   296

		break;

   297

	case E1000_DEV_ID_82546EB_COPPER:

   298

	case E1000_DEV_ID_82546EB_FIBER:

   299

	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   300

		hw->mac_type = e1000_82546;

   301

		break;

   302

	case E1000_DEV_ID_82546GB_COPPER:

   303

	case E1000_DEV_ID_82546GB_FIBER:

   304

	case E1000_DEV_ID_82546GB_SERDES:

   305

	case E1000_DEV_ID_82546GB_PCIE:

   306

	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   307

	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   308

		hw->mac_type = e1000_82546_rev_3;

   309

		break;

   310

	case E1000_DEV_ID_82541EI:

   311

	case E1000_DEV_ID_82541EI_MOBILE:

   312

	case E1000_DEV_ID_82541ER_LOM:

   313

		hw->mac_type = e1000_82541;

   314

		break;

   315

	case E1000_DEV_ID_82541ER:

   316

	case E1000_DEV_ID_82541GI:

   317

	case E1000_DEV_ID_82541GI_LF:

   318

	case E1000_DEV_ID_82541GI_MOBILE:

   319

		hw->mac_type = e1000_82541_rev_2;

   320

		break;

   321

	case E1000_DEV_ID_82547EI:

   322

	case E1000_DEV_ID_82547EI_MOBILE:

   323

		hw->mac_type = e1000_82547;

   324

		break;

   325

	case E1000_DEV_ID_82547GI:

   326

		hw->mac_type = e1000_82547_rev_2;

   327

		break;

   328

	case E1000_DEV_ID_INTEL_CE4100_GBE:

   329

		hw->mac_type = e1000_ce4100;

   330

		break;

   331

	default:

   332

		/* Should never have loaded on this device */

   333

		return -E1000_ERR_MAC_TYPE;

   334

	}

   335

   336

	switch (hw->mac_type) {

   337

	case e1000_82541:

   338

	case e1000_82547:

   339

	case e1000_82541_rev_2:

   340

	case e1000_82547_rev_2:

   341

		hw->asf_firmware_present = true;

   342

		break;

   343

	default:

   344

		break;

   345

	}

   346

   347

	/* The 82543 chip does not count tx_carrier_errors properly in

   348

	 * FD mode

   349

	 */

   350

	if (hw->mac_type == e1000_82543)

   351

		hw->bad_tx_carr_stats_fd = true;

   352

   353

	if (hw->mac_type > e1000_82544)

   354

		hw->has_smbus = true;

   355

   356

	return E1000_SUCCESS;

   357

}

   358

   359

/**

   360

 * e1000_set_media_type - Set media type and TBI compatibility.

   361

 * @hw: Struct containing variables accessed by shared code

   362

 */

   363

void e1000_set_media_type(struct e1000_hw *hw)

   364

{

   365

	u32 status;

   366

   367

	e_dbg("e1000_set_media_type");

   368

   369

	if (hw->mac_type != e1000_82543) {

   370

		/* tbi_compatibility is only valid on 82543 */

   371

		hw->tbi_compatibility_en = false;

   372

	}

   373

   374

	switch (hw->device_id) {

   375

	case E1000_DEV_ID_82545GM_SERDES:

   376

	case E1000_DEV_ID_82546GB_SERDES:

   377

		hw->media_type = e1000_media_type_internal_serdes;

   378

		break;

   379

	default:

   380

		switch (hw->mac_type) {

   381

		case e1000_82542_rev2_0:

   382

		case e1000_82542_rev2_1:

   383

			hw->media_type = e1000_media_type_fiber;

   384

			break;

   385

		case e1000_ce4100:

   386

			hw->media_type = e1000_media_type_copper;

   387

			break;

   388

		default:

   389

			status = er32(STATUS);

   390

			if (status & E1000_STATUS_TBIMODE) {

   391

				hw->media_type = e1000_media_type_fiber;

   392

				/* tbi_compatibility not valid on fiber */

   393

				hw->tbi_compatibility_en = false;

   394

			} else {

   395

				hw->media_type = e1000_media_type_copper;

   396

			}

   397

			break;

   398

		}

   399

	}

   400

}

   401

   402

/**

   403

 * e1000_reset_hw - reset the hardware completely

   404

 * @hw: Struct containing variables accessed by shared code

   405

 *

   406

 * Reset the transmit and receive units; mask and clear all interrupts.

   407

 */

   408

s32 e1000_reset_hw(struct e1000_hw *hw)

   409

{

   410

	u32 ctrl;

   411

	u32 ctrl_ext;

   412

	u32 icr __attribute__ ((unused));

   413

	u32 manc;

   414

	u32 led_ctrl;

   415

	s32 ret_val;

   416

   417

	e_dbg("e1000_reset_hw");

   418

   419

	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   420

	if (hw->mac_type == e1000_82542_rev2_0) {

   421

		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   422

		e1000_pci_clear_mwi(hw);

   423

	}

   424

   425

	/* Clear interrupt mask to stop board from generating interrupts */

   426

	e_dbg("Masking off all interrupts\n");

   427

	ew32(IMC, 0xffffffff);

   428

   429

	/* Disable the Transmit and Receive units.  Then delay to allow

   430

	 * any pending transactions to complete before we hit the MAC with

   431

	 * the global reset.

   432

	 */

   433

	ew32(RCTL, 0);

   434

	ew32(TCTL, E1000_TCTL_PSP);

   435

	E1000_WRITE_FLUSH();

   436

   437

	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   438

	hw->tbi_compatibility_on = false;

   439

   440

	/* Delay to allow any outstanding PCI transactions to complete before

   441

	 * resetting the device

   442

	 */

   443

	msleep(10);

   444

   445

	ctrl = er32(CTRL);

   446

   447

	/* Must reset the PHY before resetting the MAC */

   448

	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   449

		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   450

		E1000_WRITE_FLUSH();

   451

		msleep(5);

   452

	}

   453

   454

	/* Issue a global reset to the MAC.  This will reset the chip's

   455

	 * transmit, receive, DMA, and link units.  It will not effect

   456

	 * the current PCI configuration.  The global reset bit is self-

   457

	 * clearing, and should clear within a microsecond.

   458

	 */

   459

	e_dbg("Issuing a global reset to MAC\n");

   460

   461

	switch (hw->mac_type) {

   462

	case e1000_82544:

   463

	case e1000_82540:

   464

	case e1000_82545:

   465

	case e1000_82546:

   466

	case e1000_82541:

   467

	case e1000_82541_rev_2:

   468

		/* These controllers can't ack the 64-bit write when issuing the

   469

		 * reset, so use IO-mapping as a workaround to issue the reset */

   470

		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   471

		break;

   472

	case e1000_82545_rev_3:

   473

	case e1000_82546_rev_3:

   474

		/* Reset is performed on a shadow of the control register */

   475

		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   476

		break;

   477

	case e1000_ce4100:

   478

	default:

   479

		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   480

		break;

   481

	}

   482

   483

	/* After MAC reset, force reload of EEPROM to restore power-on settings to

   484

	 * device.  Later controllers reload the EEPROM automatically, so just wait

   485

	 * for reload to complete.

   486

	 */

   487

	switch (hw->mac_type) {

   488

	case e1000_82542_rev2_0:

   489

	case e1000_82542_rev2_1:

   490

	case e1000_82543:

   491

	case e1000_82544:

   492

		/* Wait for reset to complete */

   493

		udelay(10);

   494

		ctrl_ext = er32(CTRL_EXT);

   495

		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   496

		ew32(CTRL_EXT, ctrl_ext);

   497

		E1000_WRITE_FLUSH();

   498

		/* Wait for EEPROM reload */

   499

		msleep(2);

   500

		break;

   501

	case e1000_82541:

   502

	case e1000_82541_rev_2:

   503

	case e1000_82547:

   504

	case e1000_82547_rev_2:

   505

		/* Wait for EEPROM reload */

   506

		msleep(20);

   507

		break;

   508

	default:

   509

		/* Auto read done will delay 5ms or poll based on mac type */

   510

		ret_val = e1000_get_auto_rd_done(hw);

   511

		if (ret_val)

   512

			return ret_val;

   513

		break;

   514

	}

   515

   516

	/* Disable HW ARPs on ASF enabled adapters */

   517

	if (hw->mac_type >= e1000_82540) {

   518

		manc = er32(MANC);

   519

		manc &= ~(E1000_MANC_ARP_EN);

   520

		ew32(MANC, manc);

   521

	}

   522

   523

	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   524

		e1000_phy_init_script(hw);

   525

   526

		/* Configure activity LED after PHY reset */

   527

		led_ctrl = er32(LEDCTL);

   528

		led_ctrl &= IGP_ACTIVITY_LED_MASK;

   529

		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   530