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/*******************************************************************************

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  Intel PRO/1000 Linux driver

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  Copyright(c) 1999 - 2011 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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    19

  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

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  Linux NICS <linux.nics@intel.com>

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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

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    29

/*

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 * 82562G 10/100 Network Connection

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 * 82562G-2 10/100 Network Connection

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 * 82562GT 10/100 Network Connection

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 * 82562GT-2 10/100 Network Connection

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 * 82562V 10/100 Network Connection

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 * 82562V-2 10/100 Network Connection

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 * 82566DC-2 Gigabit Network Connection

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 * 82566DC Gigabit Network Connection

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 * 82566DM-2 Gigabit Network Connection

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 * 82566DM Gigabit Network Connection

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 * 82566MC Gigabit Network Connection

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 * 82566MM Gigabit Network Connection

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 * 82567LM Gigabit Network Connection

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 * 82567LF Gigabit Network Connection

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 * 82567V Gigabit Network Connection

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 * 82567LM-2 Gigabit Network Connection

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 * 82567LF-2 Gigabit Network Connection

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 * 82567V-2 Gigabit Network Connection

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 * 82567LF-3 Gigabit Network Connection

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 * 82567LM-3 Gigabit Network Connection

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 * 82567LM-4 Gigabit Network Connection

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 * 82577LM Gigabit Network Connection

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 * 82577LC Gigabit Network Connection

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 * 82578DM Gigabit Network Connection

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 * 82578DC Gigabit Network Connection

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 * 82579LM Gigabit Network Connection

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 * 82579V Gigabit Network Connection

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 */

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#include "e1000-3.2-ethercat.h"

    60

    61

#define ICH_FLASH_GFPREG		0x0000

    62

#define ICH_FLASH_HSFSTS		0x0004

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#define ICH_FLASH_HSFCTL		0x0006

    64

#define ICH_FLASH_FADDR			0x0008

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#define ICH_FLASH_FDATA0		0x0010

    66

#define ICH_FLASH_PR0			0x0074

    67

    68

#define ICH_FLASH_READ_COMMAND_TIMEOUT	500

    69

#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	500

    70

#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	3000000

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#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF

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#define ICH_FLASH_CYCLE_REPEAT_COUNT	10

    73

    74

#define ICH_CYCLE_READ			0

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#define ICH_CYCLE_WRITE			2

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#define ICH_CYCLE_ERASE			3

    77

    78

#define FLASH_GFPREG_BASE_MASK		0x1FFF

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#define FLASH_SECTOR_ADDR_SHIFT		12

    80

    81

#define ICH_FLASH_SEG_SIZE_256		256

    82

#define ICH_FLASH_SEG_SIZE_4K		4096

    83

#define ICH_FLASH_SEG_SIZE_8K		8192

    84

#define ICH_FLASH_SEG_SIZE_64K		65536

    85

    86

    87

#define E1000_ICH_FWSM_RSPCIPHY	0x00000040 /* Reset PHY on PCI Reset */

    88

/* FW established a valid mode */

    89

#define E1000_ICH_FWSM_FW_VALID		0x00008000

    90

    91

#define E1000_ICH_MNG_IAMT_MODE		0x2

    92

    93

#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \

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				 (ID_LED_DEF1_OFF2 <<  8) | \

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				 (ID_LED_DEF1_ON2  <<  4) | \

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				 (ID_LED_DEF1_DEF2))

    97

    98

#define E1000_ICH_NVM_SIG_WORD		0x13

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#define E1000_ICH_NVM_SIG_MASK		0xC000

   100

#define E1000_ICH_NVM_VALID_SIG_MASK    0xC0

   101

#define E1000_ICH_NVM_SIG_VALUE         0x80

   102

   103

#define E1000_ICH8_LAN_INIT_TIMEOUT	1500

   104

   105

#define E1000_FEXTNVM_SW_CONFIG		1

   106

#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */

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   108

#define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7

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#define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7

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#define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3

   111

   112

#define PCIE_ICH8_SNOOP_ALL		PCIE_NO_SNOOP_ALL

   113

   114

#define E1000_ICH_RAR_ENTRIES		7

   115

   116

#define PHY_PAGE_SHIFT 5

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#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

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			   ((reg) & MAX_PHY_REG_ADDRESS))

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#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */

   120

#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */

   121

   122

#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS	0x0002

   123

#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300

   124

#define IGP3_VR_CTRL_MODE_SHUTDOWN	0x0200

   125

   126

#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */

   127

   128

#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */

   129

   130

/* SMBus Address Phy Register */

   131

#define HV_SMB_ADDR            PHY_REG(768, 26)

   132

#define HV_SMB_ADDR_MASK       0x007F

   133

#define HV_SMB_ADDR_PEC_EN     0x0200

   134

#define HV_SMB_ADDR_VALID      0x0080

   135

   136

/* PHY Power Management Control */

   137

#define HV_PM_CTRL		PHY_REG(770, 17)

   138

   139

/* PHY Low Power Idle Control */

   140

#define I82579_LPI_CTRL				PHY_REG(772, 20)

   141

#define I82579_LPI_CTRL_ENABLE_MASK		0x6000

   142

#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT	0x80

   143

   144

/* EMI Registers */

   145

#define I82579_EMI_ADDR         0x10

   146

#define I82579_EMI_DATA         0x11

   147

#define I82579_LPI_UPDATE_TIMER 0x4805	/* in 40ns units + 40 ns base value */

   148

   149

/* Strapping Option Register - RO */

   150

#define E1000_STRAP                     0x0000C

   151

#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000

   152

#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17

   153

   154

/* OEM Bits Phy Register */

   155

#define HV_OEM_BITS            PHY_REG(768, 25)

   156

#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */

   157

#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */

   158

#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */

   159

   160

#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */

   161

#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */

   162

   163

/* KMRN Mode Control */

   164

#define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)

   165

#define HV_KMRN_MDIO_SLOW      0x0400

   166

   167

/* KMRN FIFO Control and Status */

   168

#define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)

   169

#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000

   170

#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12

   171

   172

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

   173

/* Offset 04h HSFSTS */

   174

union ich8_hws_flash_status {

   175

	struct ich8_hsfsts {

   176

		u16 flcdone    :1; /* bit 0 Flash Cycle Done */

   177

		u16 flcerr     :1; /* bit 1 Flash Cycle Error */

   178

		u16 dael       :1; /* bit 2 Direct Access error Log */

   179

		u16 berasesz   :2; /* bit 4:3 Sector Erase Size */

   180

		u16 flcinprog  :1; /* bit 5 flash cycle in Progress */

   181

		u16 reserved1  :2; /* bit 13:6 Reserved */

   182

		u16 reserved2  :6; /* bit 13:6 Reserved */

   183

		u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */

   184

		u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */

   185

	} hsf_status;

   186

	u16 regval;

   187

};

   188

   189

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

   190

/* Offset 06h FLCTL */

   191

union ich8_hws_flash_ctrl {

   192

	struct ich8_hsflctl {

   193

		u16 flcgo      :1;   /* 0 Flash Cycle Go */

   194

		u16 flcycle    :2;   /* 2:1 Flash Cycle */

   195

		u16 reserved   :5;   /* 7:3 Reserved  */

   196

		u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */

   197

		u16 flockdn    :6;   /* 15:10 Reserved */

   198

	} hsf_ctrl;

   199

	u16 regval;

   200

};

   201

   202

/* ICH Flash Region Access Permissions */

   203

union ich8_hws_flash_regacc {

   204

	struct ich8_flracc {

   205

		u32 grra      :8; /* 0:7 GbE region Read Access */

   206

		u32 grwa      :8; /* 8:15 GbE region Write Access */

   207

		u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */

   208

		u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */

   209

	} hsf_flregacc;

   210

	u16 regval;

   211

};

   212

   213

/* ICH Flash Protected Region */

   214

union ich8_flash_protected_range {

   215

	struct ich8_pr {

   216

		u32 base:13;     /* 0:12 Protected Range Base */

   217

		u32 reserved1:2; /* 13:14 Reserved */

   218

		u32 rpe:1;       /* 15 Read Protection Enable */

   219

		u32 limit:13;    /* 16:28 Protected Range Limit */

   220

		u32 reserved2:2; /* 29:30 Reserved */

   221

		u32 wpe:1;       /* 31 Write Protection Enable */

   222

	} range;

   223

	u32 regval;

   224

};

   225

   226

static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);

   227

static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

   228

static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

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static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

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static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

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						u32 offset, u8 byte);

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static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

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					 u8 *data);

   234

static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

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					 u16 *data);

   236

static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

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					 u8 size, u16 *data);

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static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);

   239

static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

   240

static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);

   241

static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

   242

static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

   243

static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

   244

static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

   245

static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

   246

static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

   247

static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

   248

static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

   249

static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

   250

static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);

   251

static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

   252

static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

   253

static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

   254

static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);

   255

static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);

   256

static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);

   257

static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);

   258

   259

static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

   260

{

   261

	return readw(hw->flash_address + reg);

   262

}

   263

   264

static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

   265

{

   266

	return readl(hw->flash_address + reg);

   267

}

   268

   269

static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

   270

{

   271

	writew(val, hw->flash_address + reg);

   272

}

   273

   274

static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

   275

{

   276

	writel(val, hw->flash_address + reg);

   277

}

   278

   279

#define er16flash(reg)		__er16flash(hw, (reg))

   280

#define er32flash(reg)		__er32flash(hw, (reg))

   281

#define ew16flash(reg,val)	__ew16flash(hw, (reg), (val))

   282

#define ew32flash(reg,val)	__ew32flash(hw, (reg), (val))

   283

   284

static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)

   285

{

   286

	u32 ctrl;

   287

   288

	ctrl = er32(CTRL);

   289

	ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;

   290

	ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;

   291

	ew32(CTRL, ctrl);

   292

	e1e_flush();

   293

	udelay(10);

   294

	ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;

   295

	ew32(CTRL, ctrl);

   296

}

   297

   298

/**

   299

 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

   300

 *  @hw: pointer to the HW structure

   301

 *

   302

 *  Initialize family-specific PHY parameters and function pointers.

   303

 **/

   304

static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   305

{

   306

	struct e1000_phy_info *phy = &hw->phy;

   307

	u32 fwsm;

   308

	s32 ret_val = 0;

   309

   310

	phy->addr                     = 1;

   311

	phy->reset_delay_us           = 100;

   312

   313

	phy->ops.set_page             = e1000_set_page_igp;

   314

	phy->ops.read_reg             = e1000_read_phy_reg_hv;

   315

	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;

   316

	phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;

   317

	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;

   318

	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;

   319

	phy->ops.write_reg            = e1000_write_phy_reg_hv;

   320

	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;

   321

	phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;

   322

	phy->ops.power_up             = e1000_power_up_phy_copper;

   323

	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;

   324

	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   325

   326

	/*

   327

	 * The MAC-PHY interconnect may still be in SMBus mode

   328

	 * after Sx->S0.  If the manageability engine (ME) is

   329

	 * disabled, then toggle the LANPHYPC Value bit to force

   330

	 * the interconnect to PCIe mode.

   331

	 */

   332

	fwsm = er32(FWSM);

   333

	if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {

   334

		e1000_toggle_lanphypc_value_ich8lan(hw);

   335

		msleep(50);

   336

   337

		/*

   338

		 * Gate automatic PHY configuration by hardware on

   339

		 * non-managed 82579

   340

		 */

   341

		if (hw->mac.type == e1000_pch2lan)

   342

			e1000_gate_hw_phy_config_ich8lan(hw, true);

   343

	}

   344

   345

	/*

   346

	 * Reset the PHY before any access to it.  Doing so, ensures that

   347

	 * the PHY is in a known good state before we read/write PHY registers.

   348

	 * The generic reset is sufficient here, because we haven't determined

   349

	 * the PHY type yet.

   350

	 */

   351

	ret_val = e1000e_phy_hw_reset_generic(hw);

   352

	if (ret_val)

   353

		goto out;

   354

   355

	/* Ungate automatic PHY configuration on non-managed 82579 */

   356

	if ((hw->mac.type == e1000_pch2lan) &&

   357

	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {

   358

		usleep_range(10000, 20000);

   359

		e1000_gate_hw_phy_config_ich8lan(hw, false);

   360

	}

   361

   362

	phy->id = e1000_phy_unknown;

   363

	switch (hw->mac.type) {

   364

	default:

   365

		ret_val = e1000e_get_phy_id(hw);

   366

		if (ret_val)

   367

			goto out;

   368

		if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))

   369

			break;

   370

		/* fall-through */

   371

	case e1000_pch2lan:

   372

		/*

   373

		 * In case the PHY needs to be in mdio slow mode,

   374

		 * set slow mode and try to get the PHY id again.

   375

		 */

   376

		ret_val = e1000_set_mdio_slow_mode_hv(hw);

   377

		if (ret_val)

   378

			goto out;

   379

		ret_val = e1000e_get_phy_id(hw);

   380

		if (ret_val)

   381

			goto out;

   382

		break;

   383

	}

   384

	phy->type = e1000e_get_phy_type_from_id(phy->id);

   385

   386

	switch (phy->type) {

   387

	case e1000_phy_82577:

   388

	case e1000_phy_82579:

   389

		phy->ops.check_polarity = e1000_check_polarity_82577;

   390

		phy->ops.force_speed_duplex =

   391

		    e1000_phy_force_speed_duplex_82577;

   392

		phy->ops.get_cable_length = e1000_get_cable_length_82577;

   393

		phy->ops.get_info = e1000_get_phy_info_82577;

   394

		phy->ops.commit = e1000e_phy_sw_reset;

   395

		break;

   396

	case e1000_phy_82578:

   397

		phy->ops.check_polarity = e1000_check_polarity_m88;

   398

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   399

		phy->ops.get_cable_length = e1000e_get_cable_length_m88;

   400

		phy->ops.get_info = e1000e_get_phy_info_m88;

   401

		break;

   402

	default:

   403

		ret_val = -E1000_ERR_PHY;

   404

		break;

   405

	}

   406

   407

out:

   408

	return ret_val;

   409

}

   410

   411

/**

   412

 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers

   413

 *  @hw: pointer to the HW structure

   414

 *

   415

 *  Initialize family-specific PHY parameters and function pointers.

   416

 **/

   417

static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)

   418

{

   419

	struct e1000_phy_info *phy = &hw->phy;

   420

	s32 ret_val;

   421

	u16 i = 0;

   422

   423

	phy->addr			= 1;

   424

	phy->reset_delay_us		= 100;

   425

   426

	phy->ops.power_up               = e1000_power_up_phy_copper;

   427

	phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;

   428

   429

	/*

   430

	 * We may need to do this twice - once for IGP and if that fails,

   431

	 * we'll set BM func pointers and try again

   432

	 */

   433

	ret_val = e1000e_determine_phy_address(hw);

   434

	if (ret_val) {

   435

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   436

		phy->ops.read_reg  = e1000e_read_phy_reg_bm;

   437

		ret_val = e1000e_determine_phy_address(hw);

   438

		if (ret_val) {

   439

			e_dbg("Cannot determine PHY addr. Erroring out\n");

   440

			return ret_val;

   441

		}

   442

	}

   443

   444

	phy->id = 0;

   445

	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&

   446

	       (i++ < 100)) {

   447

		usleep_range(1000, 2000);

   448

		ret_val = e1000e_get_phy_id(hw);

   449

		if (ret_val)

   450

			return ret_val;

   451

	}

   452

   453

	/* Verify phy id */

   454

	switch (phy->id) {

   455

	case IGP03E1000_E_PHY_ID:

   456

		phy->type = e1000_phy_igp_3;

   457

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   458

		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;

   459

		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;

   460

		phy->ops.get_info = e1000e_get_phy_info_igp;

   461

		phy->ops.check_polarity = e1000_check_polarity_igp;

   462

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;

   463

		break;

   464

	case IFE_E_PHY_ID:

   465

	case IFE_PLUS_E_PHY_ID:

   466

	case IFE_C_E_PHY_ID:

   467

		phy->type = e1000_phy_ife;

   468

		phy->autoneg_mask = E1000_ALL_NOT_GIG;

   469

		phy->ops.get_info = e1000_get_phy_info_ife;

   470

		phy->ops.check_polarity = e1000_check_polarity_ife;

   471

		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;

   472

		break;

   473

	case BME1000_E_PHY_ID:

   474

		phy->type = e1000_phy_bm;

   475

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   476

		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   477

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   478

		phy->ops.commit = e1000e_phy_sw_reset;

   479

		phy->ops.get_info = e1000e_get_phy_info_m88;

   480

		phy->ops.check_polarity = e1000_check_polarity_m88;

   481

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   482

		break;

   483

	default:

   484

		return -E1000_ERR_PHY;

   485

		break;

   486

	}

   487

   488

	return 0;

   489

}

   490

   491

/**

   492

 *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers

   493

 *  @hw: pointer to the HW structure

   494

 *

   495

 *  Initialize family-specific NVM parameters and function

   496

 *  pointers.

   497

 **/

   498

static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)

   499

{

   500

	struct e1000_nvm_info *nvm = &hw->nvm;

   501

	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;

   502

	u32 gfpreg, sector_base_addr, sector_end_addr;

   503

	u16 i;

   504

   505

	/* Can't read flash registers if the register set isn't mapped. */

   506

	if (!hw->flash_address) {

   507

		e_dbg("ERROR: Flash registers not mapped\n");

   508

		return -E1000_ERR_CONFIG;

   509

	}

   510

   511

	nvm->type = e1000_nvm_flash_sw;

   512

   513

	gfpreg = er32flash(ICH_FLASH_GFPREG);

   514

   515

	/*

   516

	 * sector_X_addr is a "sector"-aligned address (4096 bytes)

   517

	 * Add 1 to sector_end_addr since this sector is included in

   518

	 * the overall size.

   519

	 */

   520

	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;

   521

	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;

   522

   523

	/* flash_base_addr is byte-aligned */

   524

	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;

   525

   526

	/*

   527

	 * find total size of the NVM, then cut in half since the total

   528

	 * size represents two separate NVM banks.

   529

	 */

   530

	nvm->flash_bank_size = (sector_end_addr - sector_base_addr)