1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2008 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

#include <linux/netdevice.h>

    30

#include <linux/ethtool.h>

    31

#include <linux/delay.h>

    32

#include <linux/pci.h>

    33

    34

#include "e1000-2.6.32-ethercat.h"

    35

    36

enum e1000_mng_mode {

    37

	e1000_mng_mode_none = 0,

    38

	e1000_mng_mode_asf,

    39

	e1000_mng_mode_pt,

    40

	e1000_mng_mode_ipmi,

    41

	e1000_mng_mode_host_if_only

    42

};

    43

    44

#define E1000_FACTPS_MNGCG		0x20000000

    45

    46

/* Intel(R) Active Management Technology signature */

    47

#define E1000_IAMT_SIGNATURE		0x544D4149

    48

    49

/**

    50

 *  e1000e_get_bus_info_pcie - Get PCIe bus information

    51

 *  @hw: pointer to the HW structure

    52

 *

    53

 *  Determines and stores the system bus information for a particular

    54

 *  network interface.  The following bus information is determined and stored:

    55

 *  bus speed, bus width, type (PCIe), and PCIe function.

    56

 **/

    57

s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)

    58

{

    59

	struct e1000_bus_info *bus = &hw->bus;

    60

	struct e1000_adapter *adapter = hw->adapter;

    61

	u32 status;

    62

	u16 pcie_link_status, pci_header_type, cap_offset;

    63

    64

	cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);

    65

	if (!cap_offset) {

    66

		bus->width = e1000_bus_width_unknown;

    67

	} else {

    68

		pci_read_config_word(adapter->pdev,

    69

				     cap_offset + PCIE_LINK_STATUS,

    70

				     &pcie_link_status);

    71

		bus->width = (enum e1000_bus_width)((pcie_link_status &

    72

						     PCIE_LINK_WIDTH_MASK) >>

    73

						    PCIE_LINK_WIDTH_SHIFT);

    74

	}

    75

    76

	pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER,

    77

			     &pci_header_type);

    78

	if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {

    79

		status = er32(STATUS);

    80

		bus->func = (status & E1000_STATUS_FUNC_MASK)

    81

			    >> E1000_STATUS_FUNC_SHIFT;

    82

	} else {

    83

		bus->func = 0;

    84

	}

    85

    86

	return 0;

    87

}

    88

    89

/**

    90

 *  e1000e_write_vfta - Write value to VLAN filter table

    91

 *  @hw: pointer to the HW structure

    92

 *  @offset: register offset in VLAN filter table

    93

 *  @value: register value written to VLAN filter table

    94

 *

    95

 *  Writes value at the given offset in the register array which stores

    96

 *  the VLAN filter table.

    97

 **/

    98

void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)

    99

{

   100

	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);

   101

	e1e_flush();

   102

}

   103

   104

/**

   105

 *  e1000e_init_rx_addrs - Initialize receive address's

   106

 *  @hw: pointer to the HW structure

   107

 *  @rar_count: receive address registers

   108

 *

   109

 *  Setups the receive address registers by setting the base receive address

   110

 *  register to the devices MAC address and clearing all the other receive

   111

 *  address registers to 0.

   112

 **/

   113

void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)

   114

{

   115

	u32 i;

   116

   117

	/* Setup the receive address */

   118

	hw_dbg(hw, "Programming MAC Address into RAR[0]\n");

   119

   120

	e1000e_rar_set(hw, hw->mac.addr, 0);

   121

   122

	/* Zero out the other (rar_entry_count - 1) receive addresses */

   123

	hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1);

   124

	for (i = 1; i < rar_count; i++) {

   125

		E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);

   126

		e1e_flush();

   127

		E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);

   128

		e1e_flush();

   129

	}

   130

}

   131

   132

/**

   133

 *  e1000e_rar_set - Set receive address register

   134

 *  @hw: pointer to the HW structure

   135

 *  @addr: pointer to the receive address

   136

 *  @index: receive address array register

   137

 *

   138

 *  Sets the receive address array register at index to the address passed

   139

 *  in by addr.

   140

 **/

   141

void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)

   142

{

   143

	u32 rar_low, rar_high;

   144

   145

	/*

   146

	 * HW expects these in little endian so we reverse the byte order

   147

	 * from network order (big endian) to little endian

   148

	 */

   149

	rar_low = ((u32) addr[0] |

   150

		   ((u32) addr[1] << 8) |

   151

		    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));

   152

   153

	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

   154

   155

	rar_high |= E1000_RAH_AV;

   156

   157

	E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);

   158

	E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);

   159

}

   160

   161

/**

   162

 *  e1000_hash_mc_addr - Generate a multicast hash value

   163

 *  @hw: pointer to the HW structure

   164

 *  @mc_addr: pointer to a multicast address

   165

 *

   166

 *  Generates a multicast address hash value which is used to determine

   167

 *  the multicast filter table array address and new table value.  See

   168

 *  e1000_mta_set_generic()

   169

 **/

   170

static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)

   171

{

   172

	u32 hash_value, hash_mask;

   173

	u8 bit_shift = 0;

   174

   175

	/* Register count multiplied by bits per register */

   176

	hash_mask = (hw->mac.mta_reg_count * 32) - 1;

   177

   178

	/*

   179

	 * For a mc_filter_type of 0, bit_shift is the number of left-shifts

   180

	 * where 0xFF would still fall within the hash mask.

   181

	 */

   182

	while (hash_mask >> bit_shift != 0xFF)

   183

		bit_shift++;

   184

   185

	/*

   186

	 * The portion of the address that is used for the hash table

   187

	 * is determined by the mc_filter_type setting.

   188

	 * The algorithm is such that there is a total of 8 bits of shifting.

   189

	 * The bit_shift for a mc_filter_type of 0 represents the number of

   190

	 * left-shifts where the MSB of mc_addr[5] would still fall within

   191

	 * the hash_mask.  Case 0 does this exactly.  Since there are a total

   192

	 * of 8 bits of shifting, then mc_addr[4] will shift right the

   193

	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the

   194

	 * cases are a variation of this algorithm...essentially raising the

   195

	 * number of bits to shift mc_addr[5] left, while still keeping the

   196

	 * 8-bit shifting total.

   197

	 *

   198

	 * For example, given the following Destination MAC Address and an

   199

	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),

   200

	 * we can see that the bit_shift for case 0 is 4.  These are the hash

   201

	 * values resulting from each mc_filter_type...

   202

	 * [0] [1] [2] [3] [4] [5]

   203

	 * 01  AA  00  12  34  56

   204

	 * LSB		 MSB

   205

	 *

   206

	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563

   207

	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6

   208

	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163

   209

	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634

   210

	 */

   211

	switch (hw->mac.mc_filter_type) {

   212

	default:

   213

	case 0:

   214

		break;

   215

	case 1:

   216

		bit_shift += 1;

   217

		break;

   218

	case 2:

   219

		bit_shift += 2;

   220

		break;

   221

	case 3:

   222

		bit_shift += 4;

   223

		break;

   224

	}

   225

   226

	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |

   227

				  (((u16) mc_addr[5]) << bit_shift)));

   228

   229

	return hash_value;

   230

}

   231

   232

/**

   233

 *  e1000e_update_mc_addr_list_generic - Update Multicast addresses

   234

 *  @hw: pointer to the HW structure

   235

 *  @mc_addr_list: array of multicast addresses to program

   236

 *  @mc_addr_count: number of multicast addresses to program

   237

 *  @rar_used_count: the first RAR register free to program

   238

 *  @rar_count: total number of supported Receive Address Registers

   239

 *

   240

 *  Updates the Receive Address Registers and Multicast Table Array.

   241

 *  The caller must have a packed mc_addr_list of multicast addresses.

   242

 *  The parameter rar_count will usually be hw->mac.rar_entry_count

   243

 *  unless there are workarounds that change this.

   244

 **/

   245

void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,

   246

					u8 *mc_addr_list, u32 mc_addr_count,

   247

					u32 rar_used_count, u32 rar_count)

   248

{

   249

	u32 i;

   250

	u32 *mcarray = kzalloc(hw->mac.mta_reg_count * sizeof(u32), GFP_ATOMIC);

   251

   252

	if (!mcarray) {

   253

		printk(KERN_ERR "multicast array memory allocation failed\n");

   254

		return;

   255

	}

   256

   257

	/*

   258

	 * Load the first set of multicast addresses into the exact

   259

	 * filters (RAR).  If there are not enough to fill the RAR

   260

	 * array, clear the filters.

   261

	 */

   262

	for (i = rar_used_count; i < rar_count; i++) {

   263

		if (mc_addr_count) {

   264

			e1000e_rar_set(hw, mc_addr_list, i);

   265

			mc_addr_count--;

   266

			mc_addr_list += ETH_ALEN;

   267

		} else {

   268

			E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);

   269

			e1e_flush();

   270

			E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);

   271

			e1e_flush();

   272

		}

   273

	}

   274

   275

	/* Load any remaining multicast addresses into the hash table. */

   276

	for (; mc_addr_count > 0; mc_addr_count--) {

   277

		u32 hash_value, hash_reg, hash_bit, mta;

   278

		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);

   279

		hw_dbg(hw, "Hash value = 0x%03X\n", hash_value);

   280

		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);

   281

		hash_bit = hash_value & 0x1F;

   282

		mta = (1 << hash_bit);

   283

		mcarray[hash_reg] |= mta;

   284

		mc_addr_list += ETH_ALEN;

   285

	}

   286

   287

	/* write the hash table completely */

   288

	for (i = 0; i < hw->mac.mta_reg_count; i++)

   289

		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, mcarray[i]);

   290

   291

	e1e_flush();

   292

	kfree(mcarray);

   293

}

   294

   295

/**

   296

 *  e1000e_clear_hw_cntrs_base - Clear base hardware counters

   297

 *  @hw: pointer to the HW structure

   298

 *

   299

 *  Clears the base hardware counters by reading the counter registers.

   300

 **/

   301

void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)

   302

{

   303

	u32 temp;

   304

   305

	temp = er32(CRCERRS);

   306

	temp = er32(SYMERRS);

   307

	temp = er32(MPC);

   308

	temp = er32(SCC);

   309

	temp = er32(ECOL);

   310

	temp = er32(MCC);

   311

	temp = er32(LATECOL);

   312

	temp = er32(COLC);

   313

	temp = er32(DC);

   314

	temp = er32(SEC);

   315

	temp = er32(RLEC);

   316

	temp = er32(XONRXC);

   317

	temp = er32(XONTXC);

   318

	temp = er32(XOFFRXC);

   319

	temp = er32(XOFFTXC);

   320

	temp = er32(FCRUC);

   321

	temp = er32(GPRC);

   322

	temp = er32(BPRC);

   323

	temp = er32(MPRC);

   324

	temp = er32(GPTC);

   325

	temp = er32(GORCL);

   326

	temp = er32(GORCH);

   327

	temp = er32(GOTCL);

   328

	temp = er32(GOTCH);

   329

	temp = er32(RNBC);

   330

	temp = er32(RUC);

   331

	temp = er32(RFC);

   332

	temp = er32(ROC);

   333

	temp = er32(RJC);

   334

	temp = er32(TORL);

   335

	temp = er32(TORH);

   336

	temp = er32(TOTL);

   337

	temp = er32(TOTH);

   338

	temp = er32(TPR);

   339

	temp = er32(TPT);

   340

	temp = er32(MPTC);

   341

	temp = er32(BPTC);

   342

}

   343

   344

/**

   345

 *  e1000e_check_for_copper_link - Check for link (Copper)

   346

 *  @hw: pointer to the HW structure

   347

 *

   348

 *  Checks to see of the link status of the hardware has changed.  If a

   349

 *  change in link status has been detected, then we read the PHY registers

   350

 *  to get the current speed/duplex if link exists.

   351

 **/

   352

s32 e1000e_check_for_copper_link(struct e1000_hw *hw)

   353

{

   354

	struct e1000_mac_info *mac = &hw->mac;

   355

	s32 ret_val;

   356

	bool link;

   357

   358

	/*

   359

	 * We only want to go out to the PHY registers to see if Auto-Neg

   360

	 * has completed and/or if our link status has changed.  The

   361

	 * get_link_status flag is set upon receiving a Link Status

   362

	 * Change or Rx Sequence Error interrupt.

   363

	 */

   364

	if (!mac->get_link_status)

   365

		return 0;

   366

   367

	/*

   368

	 * First we want to see if the MII Status Register reports

   369

	 * link.  If so, then we want to get the current speed/duplex

   370

	 * of the PHY.

   371

	 */

   372

	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);

   373

	if (ret_val)

   374

		return ret_val;

   375

   376

	if (!link)

   377

		return ret_val; /* No link detected */

   378

   379

	mac->get_link_status = 0;

   380

   381

	/*

   382

	 * Check if there was DownShift, must be checked

   383

	 * immediately after link-up

   384

	 */

   385

	e1000e_check_downshift(hw);

   386

   387

	/*

   388

	 * If we are forcing speed/duplex, then we simply return since

   389

	 * we have already determined whether we have link or not.

   390

	 */

   391

	if (!mac->autoneg) {

   392

		ret_val = -E1000_ERR_CONFIG;

   393

		return ret_val;

   394

	}

   395

   396

	/*

   397

	 * Auto-Neg is enabled.  Auto Speed Detection takes care

   398

	 * of MAC speed/duplex configuration.  So we only need to

   399

	 * configure Collision Distance in the MAC.

   400

	 */

   401

	e1000e_config_collision_dist(hw);

   402

   403

	/*

   404

	 * Configure Flow Control now that Auto-Neg has completed.

   405

	 * First, we need to restore the desired flow control

   406

	 * settings because we may have had to re-autoneg with a

   407

	 * different link partner.

   408

	 */

   409

	ret_val = e1000e_config_fc_after_link_up(hw);

   410

	if (ret_val) {

   411

		hw_dbg(hw, "Error configuring flow control\n");

   412

	}

   413

   414

	return ret_val;

   415

}

   416

   417

/**

   418

 *  e1000e_check_for_fiber_link - Check for link (Fiber)

   419

 *  @hw: pointer to the HW structure

   420

 *

   421

 *  Checks for link up on the hardware.  If link is not up and we have

   422

 *  a signal, then we need to force link up.

   423

 **/

   424

s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)

   425

{

   426

	struct e1000_mac_info *mac = &hw->mac;

   427

	u32 rxcw;

   428

	u32 ctrl;

   429

	u32 status;

   430

	s32 ret_val;

   431

   432

	ctrl = er32(CTRL);

   433

	status = er32(STATUS);

   434

	rxcw = er32(RXCW);

   435

   436

	/*

   437

	 * If we don't have link (auto-negotiation failed or link partner

   438

	 * cannot auto-negotiate), the cable is plugged in (we have signal),

   439

	 * and our link partner is not trying to auto-negotiate with us (we

   440

	 * are receiving idles or data), we need to force link up. We also

   441

	 * need to give auto-negotiation time to complete, in case the cable

   442

	 * was just plugged in. The autoneg_failed flag does this.

   443

	 */

   444

	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */

   445

	if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&

   446

	    (!(rxcw & E1000_RXCW_C))) {

   447

		if (mac->autoneg_failed == 0) {

   448

			mac->autoneg_failed = 1;

   449

			return 0;

   450

		}

   451

		hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n");

   452

   453

		/* Disable auto-negotiation in the TXCW register */

   454

		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));

   455

   456

		/* Force link-up and also force full-duplex. */

   457

		ctrl = er32(CTRL);

   458

		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

   459

		ew32(CTRL, ctrl);

   460

   461

		/* Configure Flow Control after forcing link up. */

   462

		ret_val = e1000e_config_fc_after_link_up(hw);

   463

		if (ret_val) {

   464

			hw_dbg(hw, "Error configuring flow control\n");

   465

			return ret_val;

   466

		}

   467

	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {

   468

		/*

   469

		 * If we are forcing link and we are receiving /C/ ordered

   470

		 * sets, re-enable auto-negotiation in the TXCW register

   471

		 * and disable forced link in the Device Control register

   472

		 * in an attempt to auto-negotiate with our link partner.

   473

		 */

   474

		hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n");

   475

		ew32(TXCW, mac->txcw);

   476

		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));

   477

   478

		mac->serdes_has_link = true;

   479

	}

   480

   481

	return 0;

   482

}

   483

   484

/**

   485

 *  e1000e_check_for_serdes_link - Check for link (Serdes)

   486

 *  @hw: pointer to the HW structure

   487

 *

   488

 *  Checks for link up on the hardware.  If link is not up and we have

   489

 *  a signal, then we need to force link up.

   490

 **/

   491

s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)

   492

{

   493

	struct e1000_mac_info *mac = &hw->mac;

   494

	u32 rxcw;

   495

	u32 ctrl;

   496

	u32 status;

   497

	s32 ret_val;

   498

   499

	ctrl = er32(CTRL);

   500

	status = er32(STATUS);

   501

	rxcw = er32(RXCW);

   502

   503

	/*

   504

	 * If we don't have link (auto-negotiation failed or link partner

   505

	 * cannot auto-negotiate), and our link partner is not trying to

   506

	 * auto-negotiate with us (we are receiving idles or data),

   507

	 * we need to force link up. We also need to give auto-negotiation

   508

	 * time to complete.

   509

	 */

   510

	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */

   511

	if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {

   512

		if (mac->autoneg_failed == 0) {

   513

			mac->autoneg_failed = 1;

   514

			return 0;

   515

		}

   516

		hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n");

   517

   518

		/* Disable auto-negotiation in the TXCW register */

   519

		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));

   520

   521

		/* Force link-up and also force full-duplex. */

   522

		ctrl = er32(CTRL);

   523

		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

   524

		ew32(CTRL, ctrl);

   525

   526

		/* Configure Flow Control after forcing link up. */

   527

		ret_val = e1000e_config_fc_after_link_up(hw);

   528

		if (ret_val) {

   529

			hw_dbg(hw, "Error configuring flow control\n");

   530

			return ret_val;