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/******************************************************************************

     2

 *

     3

 *  $Id$

     4

 *

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 *  Copyright (C) 2006-2008  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it and/or

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 *  modify it under the terms of the GNU General Public License version 2, as

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 *  published by the Free Software Foundation.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

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 *  Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License along

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 *  with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

    22

 *  ---

    23

 *

    24

 *  The license mentioned above concerns the source code only. Using the

    25

 *  EtherCAT technology and brand is only permitted in compliance with the

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 *  industrial property and similar rights of Beckhoff Automation GmbH.

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 *

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 *****************************************************************************/

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/**

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   \file

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   EtherCAT driver for RTL8139-compatible NICs.

    33

*/

    34

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/*****************************************************************************/

    36

    37

/*

    38

  Former documentation:

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    40

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41

    42

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

    44

    45

	Much code comes from Donald Becker's rtl8139.c driver,

    46

	versions 1.13 and older.  This driver was originally based

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	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48

    49

	-----<snip>-----

    50

    51

        	Written 1997-2001 by Donald Becker.

    52

		This software may be used and distributed according to the

    53

		terms of the GNU General Public License (GPL), incorporated

    54

		herein by reference.  Drivers based on or derived from this

    55

		code fall under the GPL and must retain the authorship,

    56

		copyright and license notice.  This file is not a complete

    57

		program and may only be used when the entire operating

    58

		system is licensed under the GPL.

    59

    60

		This driver is for boards based on the RTL8129 and RTL8139

    61

		PCI ethernet chips.

    62

    63

		The author may be reached as becker@scyld.com, or C/O Scyld

    64

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65

		MD 21403

    66

    67

		Support and updates available at

    68

		http://www.scyld.com/network/rtl8139.html

    69

    70

		Twister-tuning table provided by Kinston

    71

		<shangh@realtek.com.tw>.

    72

    73

	-----<snip>-----

    74

    75

	This software may be used and distributed according to the terms

    76

	of the GNU General Public License, incorporated herein by reference.

    77

    78

	Contributors:

    79

    80

		Donald Becker - he wrote the original driver, kudos to him!

    81

		(but please don't e-mail him for support, this isn't his driver)

    82

    83

		Tigran Aivazian - bug fixes, skbuff free cleanup

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		Martin Mares - suggestions for PCI cleanup

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		David S. Miller - PCI DMA and softnet updates

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		Ernst Gill - fixes ported from BSD driver

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    91

		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

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		Gerard Sharp - bug fix, testing and feedback

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    96

		David Ford - Rx ring wrap fix

    97

    98

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

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		to find and fix a crucial bug on older chipsets.

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   101

		Donald Becker/Chris Butterworth/Marcus Westergren -

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		Noticed various Rx packet size-related buglets.

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   104

		Santiago Garcia Mantinan - testing and feedback

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		Jens David - 2.2.x kernel backports

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   108

		Martin Dennett - incredibly helpful insight on undocumented

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		features of the 8139 chips

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   111

		Jean-Jacques Michel - bug fix

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		Tobias Ringström - Rx interrupt status checking suggestion

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		Andrew Morton - Clear blocked signals, avoid

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		buffer overrun setting current->comm.

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		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

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   124

		"rtl8139-diag -mmmaaavvveefN" output

   125

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

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   127

*/

   128

   129

#define DRV_NAME	"ec_8139too"

   130

#define DRV_VERSION	"0.9.27"

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#include <linux/module.h>

   134

#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

   137

#include <linux/init.h>

   138

#include <linux/ioport.h>

   139

#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/rtnetlink.h>

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#include <linux/delay.h>

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#include <linux/ethtool.h>

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#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <asm/io.h>

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#include <asm/uaccess.h>

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#include <asm/irq.h>

   150

   151

#include "../globals.h"

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#include "ecdev.h"

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   154

#define RTL8139_DRIVER_NAME DRV_NAME \

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                            " EtherCAT-capable Fast Ethernet driver " \

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                            DRV_VERSION ", master " EC_MASTER_VERSION

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   158

#define PFX DRV_NAME ": "

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   160

/* Default Message level */

   161

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   162

                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   164

   165

   166

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   167

#ifdef CONFIG_8139TOO_PIO

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#define USE_IO_OPS 1

   169

#endif

   170

   171

/* define to 1, 2 or 3 to enable copious debugging info */

   172

#define RTL8139_DEBUG 0

   173

   174

/* define to 1 to disable lightweight runtime debugging checks */

   175

#undef RTL8139_NDEBUG

   176

   177

   178

#if RTL8139_DEBUG

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/* note: prints function name for you */

   180

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

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#else

   182

#  define DPRINTK(fmt, args...)

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#endif

   184

   185

#ifdef RTL8139_NDEBUG

   186

#  define assert(expr) do {} while (0)

   187

#else

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#  define assert(expr) \

   189

        if(unlikely(!(expr))) {				        \

   190

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

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        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   192

        }

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#endif

   194

   195

   196

/* A few user-configurable values. */

   197

/* media options */

   198

#define MAX_UNITS 8

   199

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   200

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   201

   202

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   203

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   204

static int multicast_filter_limit = 32;

   205

   206

/* bitmapped message enable number */

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static int debug = -1;

   208

   209

/*

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 * Receive ring size

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 * Warning: 64K ring has hardware issues and may lock up.

   212

 */

   213

#if defined(CONFIG_SH_DREAMCAST)

   214

#define RX_BUF_IDX	1	/* 16K ring */

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#else

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#define RX_BUF_IDX	2	/* 32K ring */

   217

#endif

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#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   219

#define RX_BUF_PAD	16

   220

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   221

   222

#if RX_BUF_LEN == 65536

   223

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   224

#else

   225

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   226

#endif

   227

   228

/* Number of Tx descriptor registers. */

   229

#define NUM_TX_DESC	4

   230

   231

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   232

#define MAX_ETH_FRAME_SIZE	1536

   233

   234

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   235

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   236

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   237

   238

/* PCI Tuning Parameters

   239

   Threshold is bytes transferred to chip before transmission starts. */

   240

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   241

   242

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   243

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   244

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   245

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   246

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   247

   248

/* Operational parameters that usually are not changed. */

   249

/* Time in jiffies before concluding the transmitter is hung. */

   250

#define TX_TIMEOUT  (6*HZ)

   251

   252

   253

enum {

   254

	HAS_MII_XCVR = 0x010000,

   255

	HAS_CHIP_XCVR = 0x020000,

   256

	HAS_LNK_CHNG = 0x040000,

   257

};

   258

   259

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   260

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   261

#define RTL_MIN_IO_SIZE 0x80

   262

#define RTL8139B_IO_SIZE 256

   263

   264

#define RTL8129_CAPS	HAS_MII_XCVR

   265

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   266

   267

typedef enum {

   268

	RTL8139 = 0,

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	RTL8129,

   270

} board_t;

   271

   272

   273

/* indexed by board_t, above */

   274

static const struct {

   275

	const char *name;

   276

	u32 hw_flags;

   277

} board_info[] __devinitdata = {

   278

	{ "RealTek RTL8139", RTL8139_CAPS },

   279

	{ "RealTek RTL8129", RTL8129_CAPS },

   280

};

   281

   282

   283

static struct pci_device_id rtl8139_pci_tbl[] = {

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	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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   304

#ifdef CONFIG_SH_SECUREEDGE5410

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	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

   308

#ifdef CONFIG_8139TOO_8129

   309

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

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#endif

   311

   312

	/* some crazy cards report invalid vendor ids like

   313

	 * 0x0001 here.  The other ids are valid and constant,

   314

	 * so we simply don't match on the main vendor id.

   315

	 */

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	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   318

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   319

   320

	{0,}

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};

   322

   323

/* prevent driver from being loaded automatically */

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//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   325

   326

static struct {

   327

	const char str[ETH_GSTRING_LEN];

   328

} ethtool_stats_keys[] = {

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	{ "early_rx" },

   330

	{ "tx_buf_mapped" },

   331

	{ "tx_timeouts" },

   332

	{ "rx_lost_in_ring" },

   333

};

   334

   335

/* The rest of these values should never change. */

   336

   337

/* Symbolic offsets to registers. */

   338

enum RTL8139_registers {

   339

	MAC0 = 0,		/* Ethernet hardware address. */

   340

	MAR0 = 8,		/* Multicast filter. */

   341

	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   342

	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   343

	RxBuf = 0x30,

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	ChipCmd = 0x37,

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	RxBufPtr = 0x38,

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	RxBufAddr = 0x3A,

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	IntrMask = 0x3C,

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	IntrStatus = 0x3E,

   349

	TxConfig = 0x40,

   350

	RxConfig = 0x44,

   351

	Timer = 0x48,		/* A general-purpose counter. */

   352

	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   353

	Cfg9346 = 0x50,

   354

	Config0 = 0x51,

   355

	Config1 = 0x52,

   356

	FlashReg = 0x54,

   357

	MediaStatus = 0x58,

   358

	Config3 = 0x59,

   359

	Config4 = 0x5A,		/* absent on RTL-8139A */

   360

	HltClk = 0x5B,

   361

	MultiIntr = 0x5C,

   362

	TxSummary = 0x60,

   363

	BasicModeCtrl = 0x62,

   364

	BasicModeStatus = 0x64,

   365

	NWayAdvert = 0x66,

   366

	NWayLPAR = 0x68,

   367

	NWayExpansion = 0x6A,

   368

	/* Undocumented registers, but required for proper operation. */

   369

	FIFOTMS = 0x70,		/* FIFO Control and test. */

   370

	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   371

	PARA78 = 0x78,

   372

	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   373

	Config5 = 0xD8,		/* absent on RTL-8139A */

   374

};

   375

   376

enum ClearBitMasks {

   377

	MultiIntrClear = 0xF000,

   378

	ChipCmdClear = 0xE2,

   379

	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   380

};

   381

   382

enum ChipCmdBits {

   383

	CmdReset = 0x10,

   384

	CmdRxEnb = 0x08,

   385

	CmdTxEnb = 0x04,

   386

	RxBufEmpty = 0x01,

   387

};

   388

   389

/* Interrupt register bits, using my own meaningful names. */

   390

enum IntrStatusBits {

   391

	PCIErr = 0x8000,

   392

	PCSTimeout = 0x4000,

   393

	RxFIFOOver = 0x40,

   394

	RxUnderrun = 0x20,

   395

	RxOverflow = 0x10,

   396

	TxErr = 0x08,

   397

	TxOK = 0x04,

   398

	RxErr = 0x02,

   399

	RxOK = 0x01,

   400

   401

	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   402

};

   403

   404

enum TxStatusBits {

   405

	TxHostOwns = 0x2000,

   406

	TxUnderrun = 0x4000,

   407

	TxStatOK = 0x8000,

   408

	TxOutOfWindow = 0x20000000,

   409

	TxAborted = 0x40000000,

   410

	TxCarrierLost = 0x80000000,

   411

};

   412

enum RxStatusBits {

   413

	RxMulticast = 0x8000,

   414

	RxPhysical = 0x4000,

   415

	RxBroadcast = 0x2000,

   416

	RxBadSymbol = 0x0020,

   417

	RxRunt = 0x0010,

   418

	RxTooLong = 0x0008,

   419

	RxCRCErr = 0x0004,

   420

	RxBadAlign = 0x0002,

   421

	RxStatusOK = 0x0001,

   422

};

   423

   424

/* Bits in RxConfig. */

   425

enum rx_mode_bits {

   426

	AcceptErr = 0x20,

   427

	AcceptRunt = 0x10,

   428

	AcceptBroadcast = 0x08,

   429

	AcceptMulticast = 0x04,

   430

	AcceptMyPhys = 0x02,

   431

	AcceptAllPhys = 0x01,

   432

};

   433

   434

/* Bits in TxConfig. */

   435

enum tx_config_bits {

   436

   437

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   438

        TxIFGShift = 24,

   439

        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   440

        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   441

        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   442

        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   443

   444

	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   445

	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   446

	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   447

	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   448

	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   449

   450

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   451

};

   452

   453

/* Bits in Config1 */

   454

enum Config1Bits {

   455

	Cfg1_PM_Enable = 0x01,

   456

	Cfg1_VPD_Enable = 0x02,

   457

	Cfg1_PIO = 0x04,

   458

	Cfg1_MMIO = 0x08,

   459

	LWAKE = 0x10,		/* not on 8139, 8139A */

   460

	Cfg1_Driver_Load = 0x20,

   461

	Cfg1_LED0 = 0x40,

   462

	Cfg1_LED1 = 0x80,

   463

	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   464

	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   465

};

   466

   467

/* Bits in Config3 */

   468

enum Config3Bits {

   469

	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   470

	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   471

	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   472

	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   473

	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   474

	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   475

	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   476

	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   477

};

   478

   479

/* Bits in Config4 */

   480

enum Config4Bits {

   481

	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   482

};

   483

   484

/* Bits in Config5 */

   485

enum Config5Bits {

   486

	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   487

	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   488

	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   489

	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   490

	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   491

	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   492

	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   493

};

   494

   495

enum RxConfigBits {

   496

	/* rx fifo threshold */

   497

	RxCfgFIFOShift = 13,

   498

	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   499

   500

	/* Max DMA burst */

   501

	RxCfgDMAShift = 8,

   502

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   503

   504

	/* rx ring buffer length */

   505

	RxCfgRcv8K = 0,

   506

	RxCfgRcv16K = (1 << 11),

   507

	RxCfgRcv32K = (1 << 12),

   508

	RxCfgRcv64K = (1 << 11) | (1 << 12),

   509

   510

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   511

	RxNoWrap = (1 << 7),

   512

};

   513

   514

/* Twister tuning parameters from RealTek.

   515

   Completely undocumented, but required to tune bad links on some boards. */

   516

enum CSCRBits {

   517

	CSCR_LinkOKBit = 0x0400,

   518

	CSCR_LinkChangeBit = 0x0800,

   519

	CSCR_LinkStatusBits = 0x0f000,

   520

	CSCR_LinkDownOffCmd = 0x003c0,

   521

	CSCR_LinkDownCmd = 0x0f3c0,

   522

};

   523

   524

enum Cfg9346Bits {

   525

	Cfg9346_Lock = 0x00,

   526

	Cfg9346_Unlock = 0xC0,

   527

};