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Standard library

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================

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..

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    Documentation originally part of Smarteh's user Manual, and donated to Beremiz project.

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.. list-table::

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    * - .. figure:: library_panel.png

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            Library browser

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      - Library contains various groups of standard

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        and user defined functions. They support the

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        usage in different programmable controller

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        programming languages inside POUs.

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    * - .. figure:: block_properties.png

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            Block Properties

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      - Block Properties pop-up window can be

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        opened by double-click on function block.

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        Some of the blocks can have more inputs than

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        default. This is selectable in the Inputs field

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        (e.g. ADD block). Also an Execution Order of

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        the blocks can be programmer-defined. All

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        blocks have an additional Execution Control

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        check-box. If it is checked than two new pins

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        are added (EN – input and ENO – output) to

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        control dynamically their execution.

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Standard function blocks

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------------------------

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.. highlight:: text

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.. list-table::

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    * - .. figure:: std_block-012.png

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            SR bistable

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      - The SR bistable is a latch where the Set dominates.::

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            ( BOOL:S1, BOOL:R ) => ( BOOL:Q1 )

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        This function represents a standard set-dominant set/reset flip

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        flop. The Q1 output become TRUE when the input S1 is TRUE and

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        the R input is FALSE. In the same way, the Q1 output become

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        FALSE when the input S1 is FALSE and the R input is TRUE. After

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        one of these transitions, when both the S1 and R signals return to

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        FALSE, the Q1 output keeps the previous state until a new

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        condition occurs. If you apply a TRUE condition for both the

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        signals, the Q1 output is forced to TRUE (set-dominant).

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    * - .. figure:: std_block-010.png

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            RS bistable

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      - The RS bistable is a latch where the Reset dominates.::

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            ( BOOL:S, BOOL:R1 ) => ( BOOL:Q1 )

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        This function represents a standard reset-dominant set/reset flip

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        flop. The Q1 output become TRUE when the input S is TRUE and

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        the R1 input is FALSE. In the same way, the Q1 output become

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        FALSE when the input S is FALSE and the R1 input is TRUE. After

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        one of these transitions, when both the S and R1 signals return to

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        FALSE, the Q1 output keeps the previous state until a new

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        condition occurs. If you apply a TRUE condition for both the

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        signals, the Q1 output is forced to FALSE (reset-dominant).

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    * - .. figure:: std_block-019.png

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            SEMA Semaphore

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      - The semaphore provides a mechanism to allow software elements

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        mutually exclusive access to certain resources.::

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            ( BOOL:CLAIM, BOOL:RELEASE ) => ( BOOL:BUSY )

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        This function block implements a semaphore function. Normally

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        this function is used to synchronize events. The BUSY output is

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        activated by a TRUE condition on the CLAIM input and it is de-

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        activated by a TRUE condition on the RELEASE input.

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    * - .. figure:: std_block-021.png

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            R_TRIG Rising edge detector

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      - The output produces a single pulse when a rising edge is detected.::

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            ( BOOL:CLK ) => ( BOOL:Q )

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        This function is a rising-edge detector. The Q output becomes

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        TRUE when a 0 to 1 (or FALSE to TRUE or OFF to ON) condition is

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        detected on the CLK input and it sustains this state for a complete

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        scan cycle.

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    * - .. figure:: std_block-023.png

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            F TRIG

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      - Falling edge detector

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        The output Q produces a single pulse when a falling edge is

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        detected.::

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            ( BOOL:CLK ) => ( BOOL:Q )

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        This function is a falling-edge detector. The Q output becomes

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        TRUE when a 1 to 0 (or TRUE to FALSE or ON to OFF) condition is

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        detected on the CLK input and it sustains this state for a complete

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        scan cycle.

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    * - .. figure:: std_block-030.png

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            CTU

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            CTU_DINT,

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            CTU_LINT,

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            CTU_UDINT, CTU_ULINT

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            Up-counter

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      - The up-counter can be used to signal when a count has reached a

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        maximum value.::

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            CTU:       ( BOOL:CU, BOOL:R, INT:PV ) => ( BOOL:Q, INT:CV )

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            CTU_DINT:  ( BOOL:CU, BOOL:R, DINT:PV ) => ( BOOL:Q, DINT:CV )

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            CTU_LINT:

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            ( BOOL:CU, BOOL:R, LINT:PV ) => ( BOOL:Q, LINT:CV )

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            CTU_UDINT: ( BOOL:CU, BOOL:R, UDINT:PV ) => ( BOOL:Q, UDINT:CV )

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            CTU_ULINT: ( BOOL:CU, BOOL:R, ULINT:PV ) => ( BOOL:Q, ULINT:CV )

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        The CTU function represents an up-counter. A rising-edge on CU

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        input will increment the counter by one. When the programmed

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        value, applied to the input PV, is reached, the Q output becomes

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        TRUE. Applying a TRUE signal on R input will reset the counter to

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        zero (Asynchronous reset). The CV output reports the current

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        counting value.

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    * - .. figure:: std_block-028.png

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            CTD

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            CTD_DINT, CTD_LINT,

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            CTD_UDINT, CTD_ULINT

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            Down-counter

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      - The down-counter can be used to signal when a count has reached

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        zero, on counting down from a pre-set value.::

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            CTD:       ( BOOL:CD, BOOL:LD, INT:PV ) => ( BOOL:Q, INT:CV )

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            CTD_DINT:  ( BOOL:CD, BOOL:LD, DINT:PV ) => ( BOOL:Q, DINT:CV )

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            CTD_LINT:  ( BOOL:CD, BOOL:LD, LINT:PV ) => ( BOOL:Q, LINT:CV )

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            CTD_UDINT: ( BOOL:CD, BOOL:LD, UDINT:PV ) => ( BOOL:Q, UDINT:CV )

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            CTD_ULINT: ( BOOL:CD, BOOL:LD, ULINT:PV ) => ( BOOL:Q, ULINT:CV )

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        The CTD function represents a down-counter. A rising-edge on CD

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        input will decrement the counter by one. The Q output becomes

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        TRUE when the current counting value is equal or less than zero.

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        Applying a TRUE signal on LD (LOAD) input will load the counter

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        with the value present at input PV (Asynchronous load). The CV

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        output reports the current counting value.

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    * - .. figure:: std_block-035.png

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            CTUD

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            CTUD_DINT,

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            CTUD_LINT,

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            CTUD_UDINT,

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            CTUD_ULINT

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            Up-down counter

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      - The up-down counter has two inputs CU and CD. It can be used to

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        both count up on one input and down on the other.::

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            CTUD:       ( BOOL:CU, BOOL:CD, BOOL:R, BOOL:LD, INT:PV ) => ( BOOL:QU, BOOL:QD, INT:CV )

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            CTUD_DINT:  ( BOOL:CU, BOOL:CD, BOOL:R, BOOL:LD, DINT:PV ) => ( BOOL:QU, BOOL:QD, DINT:CV )

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            CTUD_LINT:  ( BOOL:CU, BOOL:CD, BOOL:R, BOOL:LD, LINT:PV ) => ( BOOL:QU, BOOL:QD, LINT:CV )

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            CTUD_UDINT: ( BOOL:CU, BOOL:CD, BOOL:R, BOOL:LD, UDINT:PV ) => ( BOOL:QU, BOOL:QD, UDINT:CV )

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            CTUD_ULINT: ( BOOL:CU, BOOL:CD, BOOL:R, BOOL:LD, ULINT:PV ) => ( BOOL:QU, BOOL:QD, ULINT:CV )

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        This function represents an up-down programmable counter. A

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        rising-edge on the CU (COUNT-UP) input increments the counter

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        by one while a rising-edge on the CD (COUNT-DOWN) decreases

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        the current value. Applying a TRUE signal on R input will reset the

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        counter to zero. A TRUE condition on the LD signal will load the

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        counter with the value applied to the input PV (PROGRAMMED

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        VALUE). QU output becomes active when the current counting

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        value is greater or equal to the programmed value. The QD output

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        becomes active when the current value is less or equal to zero.

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        The CV output reports the current counter value.

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    * - .. figure:: std_block-037.png

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            TP

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            Pulse timer

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      - The pulse timer can be used to generate output pulses of a given

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        time duration.::

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            ( BOOL:IN, TIME:PT ) => ( BOOL:Q, TIME:ET )

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        This kind of timer has the same behaviour of a single-shot timer or

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        a monostable timer.

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        When a rising-edge transition is detected on the IN input, the Q

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        output becomes TRUE immediately. This condition continues until

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        the programmed time PT, applied to the relative pin, is elapsed.

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        After that the PT is elapsed, the Q output keeps the ON state if

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        the input IN is still asserted else the Q output returns to the OFF

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        state. This timer is not re-triggerable. This means that after that

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        the timer has started it can't be stopped until the complete

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        session ends. The ET output reports the current elapsed time.

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    * - .. figure:: std_block-042.png

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            TON

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            On-delay timer

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      - The on-delay timer can be used to delay setting an output true,

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        for fixed period after an input becomes true.::

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            ( BOOL:IN, TIME:PT ) => ( BOOL:Q, TIME:ET )

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        Asserting the input signal IN of this function starts the timer.

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        When the programmed time, applied to the input PT, is elapsed

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        and the input IN is still asserted, the Q output becomes TRUE. This

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        condition will continue until the input IN is released. If the IN

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        input is released before time elapsing, the timer will be cleared.

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        The ET output reports the current elapsed time.

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    * - .. figure:: std_block-044.png

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            TOF

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            Off-delay timer

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      - The off-delay timer can be used to delay setting an output false,

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        for fixed period after input goes false.::

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        ( BOOL:IN, TIME:PT ) => ( BOOL:Q, TIME:ET )

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        Asserting the input signal IN of this function immediately activates

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        the Q output. At this point, releasing the input IN will start the

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        time elapsing. When the programmed time, applied to the input

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        PT, is elapsed and the input IN is still released, the Q output

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        becomes FALSE. This condition will be kept until the input IN is

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        released. If the IN input is asserted again before time elapses, the

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        timer will be cleared and the Q output remains TRUE. The ET

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        output reports the current elapsed time.

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Additional function blocks

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--------------------------

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.. list-table::

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    * - .. figure:: std_block-055.png

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            RTC

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            Real Time Clock

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      - The RTC function block sets the output CDT to the input value PDT at the next

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        evaluation of the function block following a transition from 0 to 1 of the IN input. The CDT output

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        of the RTC function block is undefined when the value of IN is 0.

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        .. line-block:: 

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            PDT = Preset date and time, loaded on rising edge of IN

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            CDT = Current date and time, valid when IN=1

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            Q = copy of EN

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        .. code-block:: 

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            (BOOL:IN, PDT:DT) => (BOOL:Q, CDT:DT)

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    * - .. figure:: std_block-049.png

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            INTEGRAL

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            Integral

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      - The integral function block integrates the value of input XIN over

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        time.::

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            ( BOOL:RUN, BOOL:R1, REAL:XIN, REAL:X0, TIME:CYCLE ) => ( BOOL:Q, REAL:XOUT )

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        When input RUN is True and override R1 is False, XOUT will

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        change for XIN value depends on CYCLE time value sampling

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        period. When RUN is False and override R1 is True, XOUT will hold

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        the last output value. If R1 is True, XOUT will be set to the X0

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        value.::

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            XOUT = XOUT + (XIN * CYCLE)

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    * - .. figure:: std_block-051.png

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            DERIVATIVE

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            Derivative

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      - The derivative function block produces an output XOUT

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        proportional to the rate of change of the input XIN.::

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            ( BOOL:RUN, REAL:XIN, TIME:CYCLE ) => ( REAL:XOUT )

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        When RUN is True, XOUT will change proportional to the rate of

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        changing of the value XIN depends on CYCLE time value sampling

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        period.::

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            XOUT = ((3 * (XIN - XIN(to-3))) + XIN(to-1) – XIN(to-2) ) / (10 * CYCLE)

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    * - .. figure:: std_block-060.png

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            PID

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            Proportional, Integral, Derivative

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      - The PID (Proportional, Integral, Derivative) function block

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        provides the classical three term controller for closed loop

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        control. It does not contain any output limitation parameters

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        (dead-band, minimum, maximum, …) or other parameters

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        normally used for real process control (see also PID_A).::

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            ( BOOL:AUTO, REAL:PV, REAL:SP, REAL:X0, REAL:KP, REAL:TR, REAL:TD, TIME:CYCLE ) => ( REAL:XOUT )

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        When AUTO is False, PID function block XOUT will follow X0 value.

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        When AUTO is True, XOUT will be calculated from error value (PV

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        process variable – SP set point), KP proportional constant, TR

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        reset time, TD derivative constant and CYCLE time value sampling

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        period.::

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            XOUT = KP * ((PV-SP) + (I_OUT/TR) + (D_OUT * TD))

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    * - .. figure:: std_block-062.png

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            RAMP

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            Ramp

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      - The RAMP function block is modelled on example given in the

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        standard but with the addition of a 'Holdback' feature.::

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            ( BOOL:RUN, REAL:X0, REAL:X1, TIME:TR, TIME:CYCLE, BOOL:HOLDBACK, REAL:ERROR, REAL:PV ) => ( BOOL:RAMP, REAL:XOUT )

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        When RUN and HOLDBACK are False, XOUT will follow X0 value.

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        When RUN is True and HOLDBACK value is False, XOUT will change

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        for ``OUT(to-1) + (X1 – XOUT(to-1))`` every CYCLE time value sampling

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        period.

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    * - .. figure:: std_block-064.png

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            HYSTERESIS

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            Hysteresis

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      - The hysteresis function block provides a hysteresis boolean output

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        driven by the difference of two floating point (REAL) inputs XIN1

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        and XIN2.::

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            ( REAL:XIN1, REAL:XIN2, REAL:EPS ) => ( BOOL:Q )

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        When XIN1 value will be grater than XIN2 + EPS value, Q becomes

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        True. When XIN1 value will be less than XIN2 - EPS value, Q

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        becomes False.