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Adjusted DC clock discipline parameters. stable-1.5
authorFlorian Pose <fp@igh-essen.com>
Tue, 20 Nov 2012 14:53:36 +0100
branchstable-1.5
changeset 2448 41dc9a4a0f76
parent 2447 e93efb4af231
child 2449 5db725cc40f9
Adjusted DC clock discipline parameters.
master/fsm_master.c file | annotate | diff | comparison | revisions
master/fsm_slave_config.c file | annotate | diff | comparison | revisions 
--- a/master/fsm_master.c	Tue Nov 20 14:35:53 2012 +0100
+++ b/master/fsm_master.c	Tue Nov 20 14:53:36 2012 +0100
@@ -48,7 +48,7 @@
 
 /** Time difference [ns] to tolerate without setting a new system time offset.
  */
-#define EC_SYSTEM_TIME_TOLERANCE_NS 100000000
+#define EC_SYSTEM_TIME_TOLERANCE_NS 1000000
 
 /*****************************************************************************/
 
--- a/master/fsm_slave_config.c	Tue Nov 20 14:35:53 2012 +0100
+++ b/master/fsm_slave_config.c	Tue Nov 20 14:53:36 2012 +0100
@@ -49,7 +49,7 @@
  * Wait for DC time difference to drop under this absolute value before
  * requesting SAFEOP.
  */
-#define EC_DC_MAX_SYNC_DIFF_NS 5000
+#define EC_DC_MAX_SYNC_DIFF_NS 10000
 
 /** Maximum time (in ms) to wait for clock discipline.
  */
etherlabmaster