# HG changeset patch
# User Florian Pose <fp@igh-essen.com>
# Date 1353419616 -3600
# Node ID 41dc9a4a0f76698cb6a2c1ed2640d7b4e790d15b
# Parent  e93efb4af231c2dbb3235a62c8a9b344843b0eb6
Adjusted DC clock discipline parameters.

diff -r e93efb4af231 -r 41dc9a4a0f76 master/fsm_master.c
--- a/master/fsm_master.c	Tue Nov 20 14:35:53 2012 +0100
+++ b/master/fsm_master.c	Tue Nov 20 14:53:36 2012 +0100
@@ -48,7 +48,7 @@
 
 /** Time difference [ns] to tolerate without setting a new system time offset.
  */
-#define EC_SYSTEM_TIME_TOLERANCE_NS 100000000
+#define EC_SYSTEM_TIME_TOLERANCE_NS 1000000
 
 /*****************************************************************************/
 
diff -r e93efb4af231 -r 41dc9a4a0f76 master/fsm_slave_config.c
--- a/master/fsm_slave_config.c	Tue Nov 20 14:35:53 2012 +0100
+++ b/master/fsm_slave_config.c	Tue Nov 20 14:53:36 2012 +0100
@@ -49,7 +49,7 @@
  * Wait for DC time difference to drop under this absolute value before
  * requesting SAFEOP.
  */
-#define EC_DC_MAX_SYNC_DIFF_NS 5000
+#define EC_DC_MAX_SYNC_DIFF_NS 10000
 
 /** Maximum time (in ms) to wait for clock discipline.
  */