examples/dc_user/Makefile.am
author Martin Troxler <ch1010277@ch10pc446>
Tue, 16 Nov 2010 15:32:27 +0100
changeset 1998 0330fdcbdd1f
parent 1414 0037a63d3cc5
child 1970 00e18cef9fc8
permissions -rw-r--r--
Use ESC port order (0-3-1-2) for bus topology and DC delay calculation
#------------------------------------------------------------------------------
#
#  $Id$
#
#  Copyright (C) 2006-2008  Florian Pose, Ingenieurgemeinschaft IgH
#
#  This file is part of the IgH EtherCAT Master.
#
#  The IgH EtherCAT Master is free software; you can redistribute it and/or
#  modify it under the terms of the GNU General Public License version 2, as
#  published by the Free Software Foundation.
#
#  The IgH EtherCAT Master is distributed in the hope that it will be useful,
#  but WITHOUT ANY WARRANTY; without even the implied warranty of
#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General
#  Public License for more details.
#
#  You should have received a copy of the GNU General Public License along with
#  the IgH EtherCAT Master; if not, write to the Free Software Foundation,
#  Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
#
#  ---
#  
#  The license mentioned above concerns the source code only. Using the
#  EtherCAT technology and brand is only permitted in compliance with the
#  industrial property and similar rights of Beckhoff Automation GmbH.
#
#------------------------------------------------------------------------------

AM_CFLAGS = -Wall

noinst_PROGRAMS = ec_dc_user_example

ec_dc_user_example_SOURCES = main.c
ec_dc_user_example_CFLAGS = -I$(top_srcdir)/include
ec_dc_user_example_LDFLAGS = -L$(top_builddir)/lib/.libs -lethercat

#------------------------------------------------------------------------------