devices/e1000e/ich8lan-2.6.37-orig.c
branchredundancy
changeset 2135 f99b2249704c
equal deleted inserted replaced
2134:2aee73b9f63f 2135:f99b2249704c
       
     1 /*******************************************************************************
       
     2 
       
     3   Intel PRO/1000 Linux driver
       
     4   Copyright(c) 1999 - 2010 Intel Corporation.
       
     5 
       
     6   This program is free software; you can redistribute it and/or modify it
       
     7   under the terms and conditions of the GNU General Public License,
       
     8   version 2, as published by the Free Software Foundation.
       
     9 
       
    10   This program is distributed in the hope it will be useful, but WITHOUT
       
    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
       
    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
       
    13   more details.
       
    14 
       
    15   You should have received a copy of the GNU General Public License along with
       
    16   this program; if not, write to the Free Software Foundation, Inc.,
       
    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
       
    18 
       
    19   The full GNU General Public License is included in this distribution in
       
    20   the file called "COPYING".
       
    21 
       
    22   Contact Information:
       
    23   Linux NICS <linux.nics@intel.com>
       
    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
       
    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
       
    26 
       
    27 *******************************************************************************/
       
    28 
       
    29 /*
       
    30  * 82562G 10/100 Network Connection
       
    31  * 82562G-2 10/100 Network Connection
       
    32  * 82562GT 10/100 Network Connection
       
    33  * 82562GT-2 10/100 Network Connection
       
    34  * 82562V 10/100 Network Connection
       
    35  * 82562V-2 10/100 Network Connection
       
    36  * 82566DC-2 Gigabit Network Connection
       
    37  * 82566DC Gigabit Network Connection
       
    38  * 82566DM-2 Gigabit Network Connection
       
    39  * 82566DM Gigabit Network Connection
       
    40  * 82566MC Gigabit Network Connection
       
    41  * 82566MM Gigabit Network Connection
       
    42  * 82567LM Gigabit Network Connection
       
    43  * 82567LF Gigabit Network Connection
       
    44  * 82567V Gigabit Network Connection
       
    45  * 82567LM-2 Gigabit Network Connection
       
    46  * 82567LF-2 Gigabit Network Connection
       
    47  * 82567V-2 Gigabit Network Connection
       
    48  * 82567LF-3 Gigabit Network Connection
       
    49  * 82567LM-3 Gigabit Network Connection
       
    50  * 82567LM-4 Gigabit Network Connection
       
    51  * 82577LM Gigabit Network Connection
       
    52  * 82577LC Gigabit Network Connection
       
    53  * 82578DM Gigabit Network Connection
       
    54  * 82578DC Gigabit Network Connection
       
    55  * 82579LM Gigabit Network Connection
       
    56  * 82579V Gigabit Network Connection
       
    57  */
       
    58 
       
    59 #include "e1000.h"
       
    60 
       
    61 #define ICH_FLASH_GFPREG		0x0000
       
    62 #define ICH_FLASH_HSFSTS		0x0004
       
    63 #define ICH_FLASH_HSFCTL		0x0006
       
    64 #define ICH_FLASH_FADDR			0x0008
       
    65 #define ICH_FLASH_FDATA0		0x0010
       
    66 #define ICH_FLASH_PR0			0x0074
       
    67 
       
    68 #define ICH_FLASH_READ_COMMAND_TIMEOUT	500
       
    69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT	500
       
    70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT	3000000
       
    71 #define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF
       
    72 #define ICH_FLASH_CYCLE_REPEAT_COUNT	10
       
    73 
       
    74 #define ICH_CYCLE_READ			0
       
    75 #define ICH_CYCLE_WRITE			2
       
    76 #define ICH_CYCLE_ERASE			3
       
    77 
       
    78 #define FLASH_GFPREG_BASE_MASK		0x1FFF
       
    79 #define FLASH_SECTOR_ADDR_SHIFT		12
       
    80 
       
    81 #define ICH_FLASH_SEG_SIZE_256		256
       
    82 #define ICH_FLASH_SEG_SIZE_4K		4096
       
    83 #define ICH_FLASH_SEG_SIZE_8K		8192
       
    84 #define ICH_FLASH_SEG_SIZE_64K		65536
       
    85 
       
    86 
       
    87 #define E1000_ICH_FWSM_RSPCIPHY	0x00000040 /* Reset PHY on PCI Reset */
       
    88 /* FW established a valid mode */
       
    89 #define E1000_ICH_FWSM_FW_VALID		0x00008000
       
    90 
       
    91 #define E1000_ICH_MNG_IAMT_MODE		0x2
       
    92 
       
    93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
       
    94 				 (ID_LED_DEF1_OFF2 <<  8) | \
       
    95 				 (ID_LED_DEF1_ON2  <<  4) | \
       
    96 				 (ID_LED_DEF1_DEF2))
       
    97 
       
    98 #define E1000_ICH_NVM_SIG_WORD		0x13
       
    99 #define E1000_ICH_NVM_SIG_MASK		0xC000
       
   100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
       
   101 #define E1000_ICH_NVM_SIG_VALUE         0x80
       
   102 
       
   103 #define E1000_ICH8_LAN_INIT_TIMEOUT	1500
       
   104 
       
   105 #define E1000_FEXTNVM_SW_CONFIG		1
       
   106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
       
   107 
       
   108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
       
   109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
       
   110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
       
   111 
       
   112 #define PCIE_ICH8_SNOOP_ALL		PCIE_NO_SNOOP_ALL
       
   113 
       
   114 #define E1000_ICH_RAR_ENTRIES		7
       
   115 
       
   116 #define PHY_PAGE_SHIFT 5
       
   117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
       
   118 			   ((reg) & MAX_PHY_REG_ADDRESS))
       
   119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
       
   120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
       
   121 
       
   122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS	0x0002
       
   123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
       
   124 #define IGP3_VR_CTRL_MODE_SHUTDOWN	0x0200
       
   125 
       
   126 #define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */
       
   127 
       
   128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
       
   129 
       
   130 /* SMBus Address Phy Register */
       
   131 #define HV_SMB_ADDR            PHY_REG(768, 26)
       
   132 #define HV_SMB_ADDR_MASK       0x007F
       
   133 #define HV_SMB_ADDR_PEC_EN     0x0200
       
   134 #define HV_SMB_ADDR_VALID      0x0080
       
   135 
       
   136 /* PHY Power Management Control */
       
   137 #define HV_PM_CTRL		PHY_REG(770, 17)
       
   138 
       
   139 /* PHY Low Power Idle Control */
       
   140 #define I82579_LPI_CTRL			PHY_REG(772, 20)
       
   141 #define I82579_LPI_CTRL_ENABLE_MASK	0x6000
       
   142 
       
   143 /* Strapping Option Register - RO */
       
   144 #define E1000_STRAP                     0x0000C
       
   145 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
       
   146 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
       
   147 
       
   148 /* OEM Bits Phy Register */
       
   149 #define HV_OEM_BITS            PHY_REG(768, 25)
       
   150 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
       
   151 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
       
   152 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
       
   153 
       
   154 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
       
   155 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
       
   156 
       
   157 /* KMRN Mode Control */
       
   158 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
       
   159 #define HV_KMRN_MDIO_SLOW      0x0400
       
   160 
       
   161 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
       
   162 /* Offset 04h HSFSTS */
       
   163 union ich8_hws_flash_status {
       
   164 	struct ich8_hsfsts {
       
   165 		u16 flcdone    :1; /* bit 0 Flash Cycle Done */
       
   166 		u16 flcerr     :1; /* bit 1 Flash Cycle Error */
       
   167 		u16 dael       :1; /* bit 2 Direct Access error Log */
       
   168 		u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
       
   169 		u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
       
   170 		u16 reserved1  :2; /* bit 13:6 Reserved */
       
   171 		u16 reserved2  :6; /* bit 13:6 Reserved */
       
   172 		u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
       
   173 		u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
       
   174 	} hsf_status;
       
   175 	u16 regval;
       
   176 };
       
   177 
       
   178 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
       
   179 /* Offset 06h FLCTL */
       
   180 union ich8_hws_flash_ctrl {
       
   181 	struct ich8_hsflctl {
       
   182 		u16 flcgo      :1;   /* 0 Flash Cycle Go */
       
   183 		u16 flcycle    :2;   /* 2:1 Flash Cycle */
       
   184 		u16 reserved   :5;   /* 7:3 Reserved  */
       
   185 		u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
       
   186 		u16 flockdn    :6;   /* 15:10 Reserved */
       
   187 	} hsf_ctrl;
       
   188 	u16 regval;
       
   189 };
       
   190 
       
   191 /* ICH Flash Region Access Permissions */
       
   192 union ich8_hws_flash_regacc {
       
   193 	struct ich8_flracc {
       
   194 		u32 grra      :8; /* 0:7 GbE region Read Access */
       
   195 		u32 grwa      :8; /* 8:15 GbE region Write Access */
       
   196 		u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
       
   197 		u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
       
   198 	} hsf_flregacc;
       
   199 	u16 regval;
       
   200 };
       
   201 
       
   202 /* ICH Flash Protected Region */
       
   203 union ich8_flash_protected_range {
       
   204 	struct ich8_pr {
       
   205 		u32 base:13;     /* 0:12 Protected Range Base */
       
   206 		u32 reserved1:2; /* 13:14 Reserved */
       
   207 		u32 rpe:1;       /* 15 Read Protection Enable */
       
   208 		u32 limit:13;    /* 16:28 Protected Range Limit */
       
   209 		u32 reserved2:2; /* 29:30 Reserved */
       
   210 		u32 wpe:1;       /* 31 Write Protection Enable */
       
   211 	} range;
       
   212 	u32 regval;
       
   213 };
       
   214 
       
   215 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
       
   216 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
       
   217 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
       
   218 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
       
   219 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
       
   220 						u32 offset, u8 byte);
       
   221 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
       
   222 					 u8 *data);
       
   223 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
       
   224 					 u16 *data);
       
   225 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
       
   226 					 u8 size, u16 *data);
       
   227 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
       
   228 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
       
   229 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
       
   230 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
       
   231 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
       
   232 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
       
   233 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
       
   234 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
       
   235 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
       
   236 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
       
   237 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
       
   238 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
       
   239 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
       
   240 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
       
   241 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
       
   242 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
       
   243 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
       
   244 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
       
   245 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
       
   246 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
       
   247 
       
   248 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
       
   249 {
       
   250 	return readw(hw->flash_address + reg);
       
   251 }
       
   252 
       
   253 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
       
   254 {
       
   255 	return readl(hw->flash_address + reg);
       
   256 }
       
   257 
       
   258 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
       
   259 {
       
   260 	writew(val, hw->flash_address + reg);
       
   261 }
       
   262 
       
   263 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
       
   264 {
       
   265 	writel(val, hw->flash_address + reg);
       
   266 }
       
   267 
       
   268 #define er16flash(reg)		__er16flash(hw, (reg))
       
   269 #define er32flash(reg)		__er32flash(hw, (reg))
       
   270 #define ew16flash(reg,val)	__ew16flash(hw, (reg), (val))
       
   271 #define ew32flash(reg,val)	__ew32flash(hw, (reg), (val))
       
   272 
       
   273 /**
       
   274  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
       
   275  *  @hw: pointer to the HW structure
       
   276  *
       
   277  *  Initialize family-specific PHY parameters and function pointers.
       
   278  **/
       
   279 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
       
   280 {
       
   281 	struct e1000_phy_info *phy = &hw->phy;
       
   282 	u32 ctrl, fwsm;
       
   283 	s32 ret_val = 0;
       
   284 
       
   285 	phy->addr                     = 1;
       
   286 	phy->reset_delay_us           = 100;
       
   287 
       
   288 	phy->ops.read_reg             = e1000_read_phy_reg_hv;
       
   289 	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
       
   290 	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
       
   291 	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
       
   292 	phy->ops.write_reg            = e1000_write_phy_reg_hv;
       
   293 	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
       
   294 	phy->ops.power_up             = e1000_power_up_phy_copper;
       
   295 	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
       
   296 	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
       
   297 
       
   298 	/*
       
   299 	 * The MAC-PHY interconnect may still be in SMBus mode
       
   300 	 * after Sx->S0.  If the manageability engine (ME) is
       
   301 	 * disabled, then toggle the LANPHYPC Value bit to force
       
   302 	 * the interconnect to PCIe mode.
       
   303 	 */
       
   304 	fwsm = er32(FWSM);
       
   305 	if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
       
   306 		ctrl = er32(CTRL);
       
   307 		ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
       
   308 		ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
       
   309 		ew32(CTRL, ctrl);
       
   310 		udelay(10);
       
   311 		ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
       
   312 		ew32(CTRL, ctrl);
       
   313 		msleep(50);
       
   314 
       
   315 		/*
       
   316 		 * Gate automatic PHY configuration by hardware on
       
   317 		 * non-managed 82579
       
   318 		 */
       
   319 		if (hw->mac.type == e1000_pch2lan)
       
   320 			e1000_gate_hw_phy_config_ich8lan(hw, true);
       
   321 	}
       
   322 
       
   323 	/*
       
   324 	 * Reset the PHY before any acccess to it.  Doing so, ensures that
       
   325 	 * the PHY is in a known good state before we read/write PHY registers.
       
   326 	 * The generic reset is sufficient here, because we haven't determined
       
   327 	 * the PHY type yet.
       
   328 	 */
       
   329 	ret_val = e1000e_phy_hw_reset_generic(hw);
       
   330 	if (ret_val)
       
   331 		goto out;
       
   332 
       
   333 	/* Ungate automatic PHY configuration on non-managed 82579 */
       
   334 	if ((hw->mac.type == e1000_pch2lan)  &&
       
   335 	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
       
   336 		msleep(10);
       
   337 		e1000_gate_hw_phy_config_ich8lan(hw, false);
       
   338 	}
       
   339 
       
   340 	phy->id = e1000_phy_unknown;
       
   341 	switch (hw->mac.type) {
       
   342 	default:
       
   343 		ret_val = e1000e_get_phy_id(hw);
       
   344 		if (ret_val)
       
   345 			goto out;
       
   346 		if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
       
   347 			break;
       
   348 		/* fall-through */
       
   349 	case e1000_pch2lan:
       
   350 		/*
       
   351 		 * In case the PHY needs to be in mdio slow mode,
       
   352 		 * set slow mode and try to get the PHY id again.
       
   353 		 */
       
   354 		ret_val = e1000_set_mdio_slow_mode_hv(hw);
       
   355 		if (ret_val)
       
   356 			goto out;
       
   357 		ret_val = e1000e_get_phy_id(hw);
       
   358 		if (ret_val)
       
   359 			goto out;
       
   360 		break;
       
   361 	}
       
   362 	phy->type = e1000e_get_phy_type_from_id(phy->id);
       
   363 
       
   364 	switch (phy->type) {
       
   365 	case e1000_phy_82577:
       
   366 	case e1000_phy_82579:
       
   367 		phy->ops.check_polarity = e1000_check_polarity_82577;
       
   368 		phy->ops.force_speed_duplex =
       
   369 			e1000_phy_force_speed_duplex_82577;
       
   370 		phy->ops.get_cable_length = e1000_get_cable_length_82577;
       
   371 		phy->ops.get_info = e1000_get_phy_info_82577;
       
   372 		phy->ops.commit = e1000e_phy_sw_reset;
       
   373 		break;
       
   374 	case e1000_phy_82578:
       
   375 		phy->ops.check_polarity = e1000_check_polarity_m88;
       
   376 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
       
   377 		phy->ops.get_cable_length = e1000e_get_cable_length_m88;
       
   378 		phy->ops.get_info = e1000e_get_phy_info_m88;
       
   379 		break;
       
   380 	default:
       
   381 		ret_val = -E1000_ERR_PHY;
       
   382 		break;
       
   383 	}
       
   384 
       
   385 out:
       
   386 	return ret_val;
       
   387 }
       
   388 
       
   389 /**
       
   390  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
       
   391  *  @hw: pointer to the HW structure
       
   392  *
       
   393  *  Initialize family-specific PHY parameters and function pointers.
       
   394  **/
       
   395 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
       
   396 {
       
   397 	struct e1000_phy_info *phy = &hw->phy;
       
   398 	s32 ret_val;
       
   399 	u16 i = 0;
       
   400 
       
   401 	phy->addr			= 1;
       
   402 	phy->reset_delay_us		= 100;
       
   403 
       
   404 	phy->ops.power_up               = e1000_power_up_phy_copper;
       
   405 	phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
       
   406 
       
   407 	/*
       
   408 	 * We may need to do this twice - once for IGP and if that fails,
       
   409 	 * we'll set BM func pointers and try again
       
   410 	 */
       
   411 	ret_val = e1000e_determine_phy_address(hw);
       
   412 	if (ret_val) {
       
   413 		phy->ops.write_reg = e1000e_write_phy_reg_bm;
       
   414 		phy->ops.read_reg  = e1000e_read_phy_reg_bm;
       
   415 		ret_val = e1000e_determine_phy_address(hw);
       
   416 		if (ret_val) {
       
   417 			e_dbg("Cannot determine PHY addr. Erroring out\n");
       
   418 			return ret_val;
       
   419 		}
       
   420 	}
       
   421 
       
   422 	phy->id = 0;
       
   423 	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
       
   424 	       (i++ < 100)) {
       
   425 		msleep(1);
       
   426 		ret_val = e1000e_get_phy_id(hw);
       
   427 		if (ret_val)
       
   428 			return ret_val;
       
   429 	}
       
   430 
       
   431 	/* Verify phy id */
       
   432 	switch (phy->id) {
       
   433 	case IGP03E1000_E_PHY_ID:
       
   434 		phy->type = e1000_phy_igp_3;
       
   435 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
       
   436 		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
       
   437 		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
       
   438 		phy->ops.get_info = e1000e_get_phy_info_igp;
       
   439 		phy->ops.check_polarity = e1000_check_polarity_igp;
       
   440 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
       
   441 		break;
       
   442 	case IFE_E_PHY_ID:
       
   443 	case IFE_PLUS_E_PHY_ID:
       
   444 	case IFE_C_E_PHY_ID:
       
   445 		phy->type = e1000_phy_ife;
       
   446 		phy->autoneg_mask = E1000_ALL_NOT_GIG;
       
   447 		phy->ops.get_info = e1000_get_phy_info_ife;
       
   448 		phy->ops.check_polarity = e1000_check_polarity_ife;
       
   449 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
       
   450 		break;
       
   451 	case BME1000_E_PHY_ID:
       
   452 		phy->type = e1000_phy_bm;
       
   453 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
       
   454 		phy->ops.read_reg = e1000e_read_phy_reg_bm;
       
   455 		phy->ops.write_reg = e1000e_write_phy_reg_bm;
       
   456 		phy->ops.commit = e1000e_phy_sw_reset;
       
   457 		phy->ops.get_info = e1000e_get_phy_info_m88;
       
   458 		phy->ops.check_polarity = e1000_check_polarity_m88;
       
   459 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
       
   460 		break;
       
   461 	default:
       
   462 		return -E1000_ERR_PHY;
       
   463 		break;
       
   464 	}
       
   465 
       
   466 	return 0;
       
   467 }
       
   468 
       
   469 /**
       
   470  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
       
   471  *  @hw: pointer to the HW structure
       
   472  *
       
   473  *  Initialize family-specific NVM parameters and function
       
   474  *  pointers.
       
   475  **/
       
   476 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
       
   477 {
       
   478 	struct e1000_nvm_info *nvm = &hw->nvm;
       
   479 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
       
   480 	u32 gfpreg, sector_base_addr, sector_end_addr;
       
   481 	u16 i;
       
   482 
       
   483 	/* Can't read flash registers if the register set isn't mapped. */
       
   484 	if (!hw->flash_address) {
       
   485 		e_dbg("ERROR: Flash registers not mapped\n");
       
   486 		return -E1000_ERR_CONFIG;
       
   487 	}
       
   488 
       
   489 	nvm->type = e1000_nvm_flash_sw;
       
   490 
       
   491 	gfpreg = er32flash(ICH_FLASH_GFPREG);
       
   492 
       
   493 	/*
       
   494 	 * sector_X_addr is a "sector"-aligned address (4096 bytes)
       
   495 	 * Add 1 to sector_end_addr since this sector is included in
       
   496 	 * the overall size.
       
   497 	 */
       
   498 	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
       
   499 	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
       
   500 
       
   501 	/* flash_base_addr is byte-aligned */
       
   502 	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
       
   503 
       
   504 	/*
       
   505 	 * find total size of the NVM, then cut in half since the total
       
   506 	 * size represents two separate NVM banks.
       
   507 	 */
       
   508 	nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
       
   509 				<< FLASH_SECTOR_ADDR_SHIFT;
       
   510 	nvm->flash_bank_size /= 2;
       
   511 	/* Adjust to word count */
       
   512 	nvm->flash_bank_size /= sizeof(u16);
       
   513 
       
   514 	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
       
   515 
       
   516 	/* Clear shadow ram */
       
   517 	for (i = 0; i < nvm->word_size; i++) {
       
   518 		dev_spec->shadow_ram[i].modified = false;
       
   519 		dev_spec->shadow_ram[i].value    = 0xFFFF;
       
   520 	}
       
   521 
       
   522 	return 0;
       
   523 }
       
   524 
       
   525 /**
       
   526  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
       
   527  *  @hw: pointer to the HW structure
       
   528  *
       
   529  *  Initialize family-specific MAC parameters and function
       
   530  *  pointers.
       
   531  **/
       
   532 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
       
   533 {
       
   534 	struct e1000_hw *hw = &adapter->hw;
       
   535 	struct e1000_mac_info *mac = &hw->mac;
       
   536 
       
   537 	/* Set media type function pointer */
       
   538 	hw->phy.media_type = e1000_media_type_copper;
       
   539 
       
   540 	/* Set mta register count */
       
   541 	mac->mta_reg_count = 32;
       
   542 	/* Set rar entry count */
       
   543 	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
       
   544 	if (mac->type == e1000_ich8lan)
       
   545 		mac->rar_entry_count--;
       
   546 	/* FWSM register */
       
   547 	mac->has_fwsm = true;
       
   548 	/* ARC subsystem not supported */
       
   549 	mac->arc_subsystem_valid = false;
       
   550 	/* Adaptive IFS supported */
       
   551 	mac->adaptive_ifs = true;
       
   552 
       
   553 	/* LED operations */
       
   554 	switch (mac->type) {
       
   555 	case e1000_ich8lan:
       
   556 	case e1000_ich9lan:
       
   557 	case e1000_ich10lan:
       
   558 		/* check management mode */
       
   559 		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
       
   560 		/* ID LED init */
       
   561 		mac->ops.id_led_init = e1000e_id_led_init;
       
   562 		/* setup LED */
       
   563 		mac->ops.setup_led = e1000e_setup_led_generic;
       
   564 		/* cleanup LED */
       
   565 		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
       
   566 		/* turn on/off LED */
       
   567 		mac->ops.led_on = e1000_led_on_ich8lan;
       
   568 		mac->ops.led_off = e1000_led_off_ich8lan;
       
   569 		break;
       
   570 	case e1000_pchlan:
       
   571 	case e1000_pch2lan:
       
   572 		/* check management mode */
       
   573 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
       
   574 		/* ID LED init */
       
   575 		mac->ops.id_led_init = e1000_id_led_init_pchlan;
       
   576 		/* setup LED */
       
   577 		mac->ops.setup_led = e1000_setup_led_pchlan;
       
   578 		/* cleanup LED */
       
   579 		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
       
   580 		/* turn on/off LED */
       
   581 		mac->ops.led_on = e1000_led_on_pchlan;
       
   582 		mac->ops.led_off = e1000_led_off_pchlan;
       
   583 		break;
       
   584 	default:
       
   585 		break;
       
   586 	}
       
   587 
       
   588 	/* Enable PCS Lock-loss workaround for ICH8 */
       
   589 	if (mac->type == e1000_ich8lan)
       
   590 		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
       
   591 
       
   592 	/* Gate automatic PHY configuration by hardware on managed 82579 */
       
   593 	if ((mac->type == e1000_pch2lan) &&
       
   594 	    (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
       
   595 		e1000_gate_hw_phy_config_ich8lan(hw, true);
       
   596 
       
   597 	return 0;
       
   598 }
       
   599 
       
   600 /**
       
   601  *  e1000_set_eee_pchlan - Enable/disable EEE support
       
   602  *  @hw: pointer to the HW structure
       
   603  *
       
   604  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
       
   605  *  the LPI Control register will remain set only if/when link is up.
       
   606  **/
       
   607 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
       
   608 {
       
   609 	s32 ret_val = 0;
       
   610 	u16 phy_reg;
       
   611 
       
   612 	if (hw->phy.type != e1000_phy_82579)
       
   613 		goto out;
       
   614 
       
   615 	ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
       
   616 	if (ret_val)
       
   617 		goto out;
       
   618 
       
   619 	if (hw->dev_spec.ich8lan.eee_disable)
       
   620 		phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
       
   621 	else
       
   622 		phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
       
   623 
       
   624 	ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
       
   625 out:
       
   626 	return ret_val;
       
   627 }
       
   628 
       
   629 /**
       
   630  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
       
   631  *  @hw: pointer to the HW structure
       
   632  *
       
   633  *  Checks to see of the link status of the hardware has changed.  If a
       
   634  *  change in link status has been detected, then we read the PHY registers
       
   635  *  to get the current speed/duplex if link exists.
       
   636  **/
       
   637 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
       
   638 {
       
   639 	struct e1000_mac_info *mac = &hw->mac;
       
   640 	s32 ret_val;
       
   641 	bool link;
       
   642 
       
   643 	/*
       
   644 	 * We only want to go out to the PHY registers to see if Auto-Neg
       
   645 	 * has completed and/or if our link status has changed.  The
       
   646 	 * get_link_status flag is set upon receiving a Link Status
       
   647 	 * Change or Rx Sequence Error interrupt.
       
   648 	 */
       
   649 	if (!mac->get_link_status) {
       
   650 		ret_val = 0;
       
   651 		goto out;
       
   652 	}
       
   653 
       
   654 	/*
       
   655 	 * First we want to see if the MII Status Register reports
       
   656 	 * link.  If so, then we want to get the current speed/duplex
       
   657 	 * of the PHY.
       
   658 	 */
       
   659 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
       
   660 	if (ret_val)
       
   661 		goto out;
       
   662 
       
   663 	if (hw->mac.type == e1000_pchlan) {
       
   664 		ret_val = e1000_k1_gig_workaround_hv(hw, link);
       
   665 		if (ret_val)
       
   666 			goto out;
       
   667 	}
       
   668 
       
   669 	if (!link)
       
   670 		goto out; /* No link detected */
       
   671 
       
   672 	mac->get_link_status = false;
       
   673 
       
   674 	if (hw->phy.type == e1000_phy_82578) {
       
   675 		ret_val = e1000_link_stall_workaround_hv(hw);
       
   676 		if (ret_val)
       
   677 			goto out;
       
   678 	}
       
   679 
       
   680 	if (hw->mac.type == e1000_pch2lan) {
       
   681 		ret_val = e1000_k1_workaround_lv(hw);
       
   682 		if (ret_val)
       
   683 			goto out;
       
   684 	}
       
   685 
       
   686 	/*
       
   687 	 * Check if there was DownShift, must be checked
       
   688 	 * immediately after link-up
       
   689 	 */
       
   690 	e1000e_check_downshift(hw);
       
   691 
       
   692 	/* Enable/Disable EEE after link up */
       
   693 	ret_val = e1000_set_eee_pchlan(hw);
       
   694 	if (ret_val)
       
   695 		goto out;
       
   696 
       
   697 	/*
       
   698 	 * If we are forcing speed/duplex, then we simply return since
       
   699 	 * we have already determined whether we have link or not.
       
   700 	 */
       
   701 	if (!mac->autoneg) {
       
   702 		ret_val = -E1000_ERR_CONFIG;
       
   703 		goto out;
       
   704 	}
       
   705 
       
   706 	/*
       
   707 	 * Auto-Neg is enabled.  Auto Speed Detection takes care
       
   708 	 * of MAC speed/duplex configuration.  So we only need to
       
   709 	 * configure Collision Distance in the MAC.
       
   710 	 */
       
   711 	e1000e_config_collision_dist(hw);
       
   712 
       
   713 	/*
       
   714 	 * Configure Flow Control now that Auto-Neg has completed.
       
   715 	 * First, we need to restore the desired flow control
       
   716 	 * settings because we may have had to re-autoneg with a
       
   717 	 * different link partner.
       
   718 	 */
       
   719 	ret_val = e1000e_config_fc_after_link_up(hw);
       
   720 	if (ret_val)
       
   721 		e_dbg("Error configuring flow control\n");
       
   722 
       
   723 out:
       
   724 	return ret_val;
       
   725 }
       
   726 
       
   727 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
       
   728 {
       
   729 	struct e1000_hw *hw = &adapter->hw;
       
   730 	s32 rc;
       
   731 
       
   732 	rc = e1000_init_mac_params_ich8lan(adapter);
       
   733 	if (rc)
       
   734 		return rc;
       
   735 
       
   736 	rc = e1000_init_nvm_params_ich8lan(hw);
       
   737 	if (rc)
       
   738 		return rc;
       
   739 
       
   740 	switch (hw->mac.type) {
       
   741 	case e1000_ich8lan:
       
   742 	case e1000_ich9lan:
       
   743 	case e1000_ich10lan:
       
   744 		rc = e1000_init_phy_params_ich8lan(hw);
       
   745 		break;
       
   746 	case e1000_pchlan:
       
   747 	case e1000_pch2lan:
       
   748 		rc = e1000_init_phy_params_pchlan(hw);
       
   749 		break;
       
   750 	default:
       
   751 		break;
       
   752 	}
       
   753 	if (rc)
       
   754 		return rc;
       
   755 
       
   756 	if (adapter->hw.phy.type == e1000_phy_ife) {
       
   757 		adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
       
   758 		adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
       
   759 	}
       
   760 
       
   761 	if ((adapter->hw.mac.type == e1000_ich8lan) &&
       
   762 	    (adapter->hw.phy.type == e1000_phy_igp_3))
       
   763 		adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
       
   764 
       
   765 	/* Disable EEE by default until IEEE802.3az spec is finalized */
       
   766 	if (adapter->flags2 & FLAG2_HAS_EEE)
       
   767 		adapter->hw.dev_spec.ich8lan.eee_disable = true;
       
   768 
       
   769 	return 0;
       
   770 }
       
   771 
       
   772 static DEFINE_MUTEX(nvm_mutex);
       
   773 
       
   774 /**
       
   775  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
       
   776  *  @hw: pointer to the HW structure
       
   777  *
       
   778  *  Acquires the mutex for performing NVM operations.
       
   779  **/
       
   780 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
       
   781 {
       
   782 	mutex_lock(&nvm_mutex);
       
   783 
       
   784 	return 0;
       
   785 }
       
   786 
       
   787 /**
       
   788  *  e1000_release_nvm_ich8lan - Release NVM mutex
       
   789  *  @hw: pointer to the HW structure
       
   790  *
       
   791  *  Releases the mutex used while performing NVM operations.
       
   792  **/
       
   793 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
       
   794 {
       
   795 	mutex_unlock(&nvm_mutex);
       
   796 }
       
   797 
       
   798 static DEFINE_MUTEX(swflag_mutex);
       
   799 
       
   800 /**
       
   801  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
       
   802  *  @hw: pointer to the HW structure
       
   803  *
       
   804  *  Acquires the software control flag for performing PHY and select
       
   805  *  MAC CSR accesses.
       
   806  **/
       
   807 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
       
   808 {
       
   809 	u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
       
   810 	s32 ret_val = 0;
       
   811 
       
   812 	mutex_lock(&swflag_mutex);
       
   813 
       
   814 	while (timeout) {
       
   815 		extcnf_ctrl = er32(EXTCNF_CTRL);
       
   816 		if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
       
   817 			break;
       
   818 
       
   819 		mdelay(1);
       
   820 		timeout--;
       
   821 	}
       
   822 
       
   823 	if (!timeout) {
       
   824 		e_dbg("SW/FW/HW has locked the resource for too long.\n");
       
   825 		ret_val = -E1000_ERR_CONFIG;
       
   826 		goto out;
       
   827 	}
       
   828 
       
   829 	timeout = SW_FLAG_TIMEOUT;
       
   830 
       
   831 	extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
       
   832 	ew32(EXTCNF_CTRL, extcnf_ctrl);
       
   833 
       
   834 	while (timeout) {
       
   835 		extcnf_ctrl = er32(EXTCNF_CTRL);
       
   836 		if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
       
   837 			break;
       
   838 
       
   839 		mdelay(1);
       
   840 		timeout--;
       
   841 	}
       
   842 
       
   843 	if (!timeout) {
       
   844 		e_dbg("Failed to acquire the semaphore.\n");
       
   845 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
       
   846 		ew32(EXTCNF_CTRL, extcnf_ctrl);
       
   847 		ret_val = -E1000_ERR_CONFIG;
       
   848 		goto out;
       
   849 	}
       
   850 
       
   851 out:
       
   852 	if (ret_val)
       
   853 		mutex_unlock(&swflag_mutex);
       
   854 
       
   855 	return ret_val;
       
   856 }
       
   857 
       
   858 /**
       
   859  *  e1000_release_swflag_ich8lan - Release software control flag
       
   860  *  @hw: pointer to the HW structure
       
   861  *
       
   862  *  Releases the software control flag for performing PHY and select
       
   863  *  MAC CSR accesses.
       
   864  **/
       
   865 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
       
   866 {
       
   867 	u32 extcnf_ctrl;
       
   868 
       
   869 	extcnf_ctrl = er32(EXTCNF_CTRL);
       
   870 	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
       
   871 	ew32(EXTCNF_CTRL, extcnf_ctrl);
       
   872 
       
   873 	mutex_unlock(&swflag_mutex);
       
   874 }
       
   875 
       
   876 /**
       
   877  *  e1000_check_mng_mode_ich8lan - Checks management mode
       
   878  *  @hw: pointer to the HW structure
       
   879  *
       
   880  *  This checks if the adapter has any manageability enabled.
       
   881  *  This is a function pointer entry point only called by read/write
       
   882  *  routines for the PHY and NVM parts.
       
   883  **/
       
   884 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
       
   885 {
       
   886 	u32 fwsm;
       
   887 
       
   888 	fwsm = er32(FWSM);
       
   889 	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
       
   890 	       ((fwsm & E1000_FWSM_MODE_MASK) ==
       
   891 		(E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
       
   892 }
       
   893 
       
   894 /**
       
   895  *  e1000_check_mng_mode_pchlan - Checks management mode
       
   896  *  @hw: pointer to the HW structure
       
   897  *
       
   898  *  This checks if the adapter has iAMT enabled.
       
   899  *  This is a function pointer entry point only called by read/write
       
   900  *  routines for the PHY and NVM parts.
       
   901  **/
       
   902 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
       
   903 {
       
   904 	u32 fwsm;
       
   905 
       
   906 	fwsm = er32(FWSM);
       
   907 	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
       
   908 	       (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
       
   909 }
       
   910 
       
   911 /**
       
   912  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
       
   913  *  @hw: pointer to the HW structure
       
   914  *
       
   915  *  Checks if firmware is blocking the reset of the PHY.
       
   916  *  This is a function pointer entry point only called by
       
   917  *  reset routines.
       
   918  **/
       
   919 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
       
   920 {
       
   921 	u32 fwsm;
       
   922 
       
   923 	fwsm = er32(FWSM);
       
   924 
       
   925 	return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
       
   926 }
       
   927 
       
   928 /**
       
   929  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
       
   930  *  @hw: pointer to the HW structure
       
   931  *
       
   932  *  Assumes semaphore already acquired.
       
   933  *
       
   934  **/
       
   935 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
       
   936 {
       
   937 	u16 phy_data;
       
   938 	u32 strap = er32(STRAP);
       
   939 	s32 ret_val = 0;
       
   940 
       
   941 	strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
       
   942 
       
   943 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
       
   944 	if (ret_val)
       
   945 		goto out;
       
   946 
       
   947 	phy_data &= ~HV_SMB_ADDR_MASK;
       
   948 	phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
       
   949 	phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
       
   950 	ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
       
   951 
       
   952 out:
       
   953 	return ret_val;
       
   954 }
       
   955 
       
   956 /**
       
   957  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
       
   958  *  @hw:   pointer to the HW structure
       
   959  *
       
   960  *  SW should configure the LCD from the NVM extended configuration region
       
   961  *  as a workaround for certain parts.
       
   962  **/
       
   963 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
       
   964 {
       
   965 	struct e1000_phy_info *phy = &hw->phy;
       
   966 	u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
       
   967 	s32 ret_val = 0;
       
   968 	u16 word_addr, reg_data, reg_addr, phy_page = 0;
       
   969 
       
   970 	/*
       
   971 	 * Initialize the PHY from the NVM on ICH platforms.  This
       
   972 	 * is needed due to an issue where the NVM configuration is
       
   973 	 * not properly autoloaded after power transitions.
       
   974 	 * Therefore, after each PHY reset, we will load the
       
   975 	 * configuration data out of the NVM manually.
       
   976 	 */
       
   977 	switch (hw->mac.type) {
       
   978 	case e1000_ich8lan:
       
   979 		if (phy->type != e1000_phy_igp_3)
       
   980 			return ret_val;
       
   981 
       
   982 		if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
       
   983 		    (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
       
   984 			sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
       
   985 			break;
       
   986 		}
       
   987 		/* Fall-thru */
       
   988 	case e1000_pchlan:
       
   989 	case e1000_pch2lan:
       
   990 		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
       
   991 		break;
       
   992 	default:
       
   993 		return ret_val;
       
   994 	}
       
   995 
       
   996 	ret_val = hw->phy.ops.acquire(hw);
       
   997 	if (ret_val)
       
   998 		return ret_val;
       
   999 
       
  1000 	data = er32(FEXTNVM);
       
  1001 	if (!(data & sw_cfg_mask))
       
  1002 		goto out;
       
  1003 
       
  1004 	/*
       
  1005 	 * Make sure HW does not configure LCD from PHY
       
  1006 	 * extended configuration before SW configuration
       
  1007 	 */
       
  1008 	data = er32(EXTCNF_CTRL);
       
  1009 	if (!(hw->mac.type == e1000_pch2lan)) {
       
  1010 		if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
       
  1011 			goto out;
       
  1012 	}
       
  1013 
       
  1014 	cnf_size = er32(EXTCNF_SIZE);
       
  1015 	cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
       
  1016 	cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
       
  1017 	if (!cnf_size)
       
  1018 		goto out;
       
  1019 
       
  1020 	cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
       
  1021 	cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
       
  1022 
       
  1023 	if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
       
  1024 	    (hw->mac.type == e1000_pchlan)) ||
       
  1025 	     (hw->mac.type == e1000_pch2lan)) {
       
  1026 		/*
       
  1027 		 * HW configures the SMBus address and LEDs when the
       
  1028 		 * OEM and LCD Write Enable bits are set in the NVM.
       
  1029 		 * When both NVM bits are cleared, SW will configure
       
  1030 		 * them instead.
       
  1031 		 */
       
  1032 		ret_val = e1000_write_smbus_addr(hw);
       
  1033 		if (ret_val)
       
  1034 			goto out;
       
  1035 
       
  1036 		data = er32(LEDCTL);
       
  1037 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
       
  1038 							(u16)data);
       
  1039 		if (ret_val)
       
  1040 			goto out;
       
  1041 	}
       
  1042 
       
  1043 	/* Configure LCD from extended configuration region. */
       
  1044 
       
  1045 	/* cnf_base_addr is in DWORD */
       
  1046 	word_addr = (u16)(cnf_base_addr << 1);
       
  1047 
       
  1048 	for (i = 0; i < cnf_size; i++) {
       
  1049 		ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
       
  1050 					 &reg_data);
       
  1051 		if (ret_val)
       
  1052 			goto out;
       
  1053 
       
  1054 		ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
       
  1055 					 1, &reg_addr);
       
  1056 		if (ret_val)
       
  1057 			goto out;
       
  1058 
       
  1059 		/* Save off the PHY page for future writes. */
       
  1060 		if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
       
  1061 			phy_page = reg_data;
       
  1062 			continue;
       
  1063 		}
       
  1064 
       
  1065 		reg_addr &= PHY_REG_MASK;
       
  1066 		reg_addr |= phy_page;
       
  1067 
       
  1068 		ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
       
  1069 						    reg_data);
       
  1070 		if (ret_val)
       
  1071 			goto out;
       
  1072 	}
       
  1073 
       
  1074 out:
       
  1075 	hw->phy.ops.release(hw);
       
  1076 	return ret_val;
       
  1077 }
       
  1078 
       
  1079 /**
       
  1080  *  e1000_k1_gig_workaround_hv - K1 Si workaround
       
  1081  *  @hw:   pointer to the HW structure
       
  1082  *  @link: link up bool flag
       
  1083  *
       
  1084  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
       
  1085  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
       
  1086  *  If link is down, the function will restore the default K1 setting located
       
  1087  *  in the NVM.
       
  1088  **/
       
  1089 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
       
  1090 {
       
  1091 	s32 ret_val = 0;
       
  1092 	u16 status_reg = 0;
       
  1093 	bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
       
  1094 
       
  1095 	if (hw->mac.type != e1000_pchlan)
       
  1096 		goto out;
       
  1097 
       
  1098 	/* Wrap the whole flow with the sw flag */
       
  1099 	ret_val = hw->phy.ops.acquire(hw);
       
  1100 	if (ret_val)
       
  1101 		goto out;
       
  1102 
       
  1103 	/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
       
  1104 	if (link) {
       
  1105 		if (hw->phy.type == e1000_phy_82578) {
       
  1106 			ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
       
  1107 			                                          &status_reg);
       
  1108 			if (ret_val)
       
  1109 				goto release;
       
  1110 
       
  1111 			status_reg &= BM_CS_STATUS_LINK_UP |
       
  1112 			              BM_CS_STATUS_RESOLVED |
       
  1113 			              BM_CS_STATUS_SPEED_MASK;
       
  1114 
       
  1115 			if (status_reg == (BM_CS_STATUS_LINK_UP |
       
  1116 			                   BM_CS_STATUS_RESOLVED |
       
  1117 			                   BM_CS_STATUS_SPEED_1000))
       
  1118 				k1_enable = false;
       
  1119 		}
       
  1120 
       
  1121 		if (hw->phy.type == e1000_phy_82577) {
       
  1122 			ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
       
  1123 			                                          &status_reg);
       
  1124 			if (ret_val)
       
  1125 				goto release;
       
  1126 
       
  1127 			status_reg &= HV_M_STATUS_LINK_UP |
       
  1128 			              HV_M_STATUS_AUTONEG_COMPLETE |
       
  1129 			              HV_M_STATUS_SPEED_MASK;
       
  1130 
       
  1131 			if (status_reg == (HV_M_STATUS_LINK_UP |
       
  1132 			                   HV_M_STATUS_AUTONEG_COMPLETE |
       
  1133 			                   HV_M_STATUS_SPEED_1000))
       
  1134 				k1_enable = false;
       
  1135 		}
       
  1136 
       
  1137 		/* Link stall fix for link up */
       
  1138 		ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
       
  1139 		                                           0x0100);
       
  1140 		if (ret_val)
       
  1141 			goto release;
       
  1142 
       
  1143 	} else {
       
  1144 		/* Link stall fix for link down */
       
  1145 		ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
       
  1146 		                                           0x4100);
       
  1147 		if (ret_val)
       
  1148 			goto release;
       
  1149 	}
       
  1150 
       
  1151 	ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
       
  1152 
       
  1153 release:
       
  1154 	hw->phy.ops.release(hw);
       
  1155 out:
       
  1156 	return ret_val;
       
  1157 }
       
  1158 
       
  1159 /**
       
  1160  *  e1000_configure_k1_ich8lan - Configure K1 power state
       
  1161  *  @hw: pointer to the HW structure
       
  1162  *  @enable: K1 state to configure
       
  1163  *
       
  1164  *  Configure the K1 power state based on the provided parameter.
       
  1165  *  Assumes semaphore already acquired.
       
  1166  *
       
  1167  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
       
  1168  **/
       
  1169 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
       
  1170 {
       
  1171 	s32 ret_val = 0;
       
  1172 	u32 ctrl_reg = 0;
       
  1173 	u32 ctrl_ext = 0;
       
  1174 	u32 reg = 0;
       
  1175 	u16 kmrn_reg = 0;
       
  1176 
       
  1177 	ret_val = e1000e_read_kmrn_reg_locked(hw,
       
  1178 	                                     E1000_KMRNCTRLSTA_K1_CONFIG,
       
  1179 	                                     &kmrn_reg);
       
  1180 	if (ret_val)
       
  1181 		goto out;
       
  1182 
       
  1183 	if (k1_enable)
       
  1184 		kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
       
  1185 	else
       
  1186 		kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
       
  1187 
       
  1188 	ret_val = e1000e_write_kmrn_reg_locked(hw,
       
  1189 	                                      E1000_KMRNCTRLSTA_K1_CONFIG,
       
  1190 	                                      kmrn_reg);
       
  1191 	if (ret_val)
       
  1192 		goto out;
       
  1193 
       
  1194 	udelay(20);
       
  1195 	ctrl_ext = er32(CTRL_EXT);
       
  1196 	ctrl_reg = er32(CTRL);
       
  1197 
       
  1198 	reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
       
  1199 	reg |= E1000_CTRL_FRCSPD;
       
  1200 	ew32(CTRL, reg);
       
  1201 
       
  1202 	ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
       
  1203 	udelay(20);
       
  1204 	ew32(CTRL, ctrl_reg);
       
  1205 	ew32(CTRL_EXT, ctrl_ext);
       
  1206 	udelay(20);
       
  1207 
       
  1208 out:
       
  1209 	return ret_val;
       
  1210 }
       
  1211 
       
  1212 /**
       
  1213  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
       
  1214  *  @hw:       pointer to the HW structure
       
  1215  *  @d0_state: boolean if entering d0 or d3 device state
       
  1216  *
       
  1217  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
       
  1218  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
       
  1219  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
       
  1220  **/
       
  1221 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
       
  1222 {
       
  1223 	s32 ret_val = 0;
       
  1224 	u32 mac_reg;
       
  1225 	u16 oem_reg;
       
  1226 
       
  1227 	if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
       
  1228 		return ret_val;
       
  1229 
       
  1230 	ret_val = hw->phy.ops.acquire(hw);
       
  1231 	if (ret_val)
       
  1232 		return ret_val;
       
  1233 
       
  1234 	if (!(hw->mac.type == e1000_pch2lan)) {
       
  1235 		mac_reg = er32(EXTCNF_CTRL);
       
  1236 		if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
       
  1237 			goto out;
       
  1238 	}
       
  1239 
       
  1240 	mac_reg = er32(FEXTNVM);
       
  1241 	if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
       
  1242 		goto out;
       
  1243 
       
  1244 	mac_reg = er32(PHY_CTRL);
       
  1245 
       
  1246 	ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
       
  1247 	if (ret_val)
       
  1248 		goto out;
       
  1249 
       
  1250 	oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
       
  1251 
       
  1252 	if (d0_state) {
       
  1253 		if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
       
  1254 			oem_reg |= HV_OEM_BITS_GBE_DIS;
       
  1255 
       
  1256 		if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
       
  1257 			oem_reg |= HV_OEM_BITS_LPLU;
       
  1258 	} else {
       
  1259 		if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
       
  1260 			oem_reg |= HV_OEM_BITS_GBE_DIS;
       
  1261 
       
  1262 		if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
       
  1263 			oem_reg |= HV_OEM_BITS_LPLU;
       
  1264 	}
       
  1265 	/* Restart auto-neg to activate the bits */
       
  1266 	if (!e1000_check_reset_block(hw))
       
  1267 		oem_reg |= HV_OEM_BITS_RESTART_AN;
       
  1268 	ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
       
  1269 
       
  1270 out:
       
  1271 	hw->phy.ops.release(hw);
       
  1272 
       
  1273 	return ret_val;
       
  1274 }
       
  1275 
       
  1276 
       
  1277 /**
       
  1278  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
       
  1279  *  @hw:   pointer to the HW structure
       
  1280  **/
       
  1281 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
       
  1282 {
       
  1283 	s32 ret_val;
       
  1284 	u16 data;
       
  1285 
       
  1286 	ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
       
  1287 	if (ret_val)
       
  1288 		return ret_val;
       
  1289 
       
  1290 	data |= HV_KMRN_MDIO_SLOW;
       
  1291 
       
  1292 	ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
       
  1293 
       
  1294 	return ret_val;
       
  1295 }
       
  1296 
       
  1297 /**
       
  1298  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
       
  1299  *  done after every PHY reset.
       
  1300  **/
       
  1301 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
       
  1302 {
       
  1303 	s32 ret_val = 0;
       
  1304 	u16 phy_data;
       
  1305 
       
  1306 	if (hw->mac.type != e1000_pchlan)
       
  1307 		return ret_val;
       
  1308 
       
  1309 	/* Set MDIO slow mode before any other MDIO access */
       
  1310 	if (hw->phy.type == e1000_phy_82577) {
       
  1311 		ret_val = e1000_set_mdio_slow_mode_hv(hw);
       
  1312 		if (ret_val)
       
  1313 			goto out;
       
  1314 	}
       
  1315 
       
  1316 	if (((hw->phy.type == e1000_phy_82577) &&
       
  1317 	     ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
       
  1318 	    ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
       
  1319 		/* Disable generation of early preamble */
       
  1320 		ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
       
  1321 		if (ret_val)
       
  1322 			return ret_val;
       
  1323 
       
  1324 		/* Preamble tuning for SSC */
       
  1325 		ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
       
  1326 		if (ret_val)
       
  1327 			return ret_val;
       
  1328 	}
       
  1329 
       
  1330 	if (hw->phy.type == e1000_phy_82578) {
       
  1331 		/*
       
  1332 		 * Return registers to default by doing a soft reset then
       
  1333 		 * writing 0x3140 to the control register.
       
  1334 		 */
       
  1335 		if (hw->phy.revision < 2) {
       
  1336 			e1000e_phy_sw_reset(hw);
       
  1337 			ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
       
  1338 		}
       
  1339 	}
       
  1340 
       
  1341 	/* Select page 0 */
       
  1342 	ret_val = hw->phy.ops.acquire(hw);
       
  1343 	if (ret_val)
       
  1344 		return ret_val;
       
  1345 
       
  1346 	hw->phy.addr = 1;
       
  1347 	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
       
  1348 	hw->phy.ops.release(hw);
       
  1349 	if (ret_val)
       
  1350 		goto out;
       
  1351 
       
  1352 	/*
       
  1353 	 * Configure the K1 Si workaround during phy reset assuming there is
       
  1354 	 * link so that it disables K1 if link is in 1Gbps.
       
  1355 	 */
       
  1356 	ret_val = e1000_k1_gig_workaround_hv(hw, true);
       
  1357 	if (ret_val)
       
  1358 		goto out;
       
  1359 
       
  1360 	/* Workaround for link disconnects on a busy hub in half duplex */
       
  1361 	ret_val = hw->phy.ops.acquire(hw);
       
  1362 	if (ret_val)
       
  1363 		goto out;
       
  1364 	ret_val = hw->phy.ops.read_reg_locked(hw,
       
  1365 	                                      PHY_REG(BM_PORT_CTRL_PAGE, 17),
       
  1366 	                                      &phy_data);
       
  1367 	if (ret_val)
       
  1368 		goto release;
       
  1369 	ret_val = hw->phy.ops.write_reg_locked(hw,
       
  1370 	                                       PHY_REG(BM_PORT_CTRL_PAGE, 17),
       
  1371 	                                       phy_data & 0x00FF);
       
  1372 release:
       
  1373 	hw->phy.ops.release(hw);
       
  1374 out:
       
  1375 	return ret_val;
       
  1376 }
       
  1377 
       
  1378 /**
       
  1379  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
       
  1380  *  @hw:   pointer to the HW structure
       
  1381  **/
       
  1382 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
       
  1383 {
       
  1384 	u32 mac_reg;
       
  1385 	u16 i;
       
  1386 
       
  1387 	/* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
       
  1388 	for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
       
  1389 		mac_reg = er32(RAL(i));
       
  1390 		e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
       
  1391 		e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
       
  1392 		mac_reg = er32(RAH(i));
       
  1393 		e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
       
  1394 		e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
       
  1395 	}
       
  1396 }
       
  1397 
       
  1398 static u32 e1000_calc_rx_da_crc(u8 mac[])
       
  1399 {
       
  1400 	u32 poly = 0xEDB88320;	/* Polynomial for 802.3 CRC calculation */
       
  1401 	u32 i, j, mask, crc;
       
  1402 
       
  1403 	crc = 0xffffffff;
       
  1404 	for (i = 0; i < 6; i++) {
       
  1405 		crc = crc ^ mac[i];
       
  1406 		for (j = 8; j > 0; j--) {
       
  1407 			mask = (crc & 1) * (-1);
       
  1408 			crc = (crc >> 1) ^ (poly & mask);
       
  1409 		}
       
  1410 	}
       
  1411 	return ~crc;
       
  1412 }
       
  1413 
       
  1414 /**
       
  1415  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
       
  1416  *  with 82579 PHY
       
  1417  *  @hw: pointer to the HW structure
       
  1418  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
       
  1419  **/
       
  1420 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
       
  1421 {
       
  1422 	s32 ret_val = 0;
       
  1423 	u16 phy_reg, data;
       
  1424 	u32 mac_reg;
       
  1425 	u16 i;
       
  1426 
       
  1427 	if (hw->mac.type != e1000_pch2lan)
       
  1428 		goto out;
       
  1429 
       
  1430 	/* disable Rx path while enabling/disabling workaround */
       
  1431 	e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
       
  1432 	ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
       
  1433 	if (ret_val)
       
  1434 		goto out;
       
  1435 
       
  1436 	if (enable) {
       
  1437 		/*
       
  1438 		 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
       
  1439 		 * SHRAL/H) and initial CRC values to the MAC
       
  1440 		 */
       
  1441 		for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
       
  1442 			u8 mac_addr[ETH_ALEN] = {0};
       
  1443 			u32 addr_high, addr_low;
       
  1444 
       
  1445 			addr_high = er32(RAH(i));
       
  1446 			if (!(addr_high & E1000_RAH_AV))
       
  1447 				continue;
       
  1448 			addr_low = er32(RAL(i));
       
  1449 			mac_addr[0] = (addr_low & 0xFF);
       
  1450 			mac_addr[1] = ((addr_low >> 8) & 0xFF);
       
  1451 			mac_addr[2] = ((addr_low >> 16) & 0xFF);
       
  1452 			mac_addr[3] = ((addr_low >> 24) & 0xFF);
       
  1453 			mac_addr[4] = (addr_high & 0xFF);
       
  1454 			mac_addr[5] = ((addr_high >> 8) & 0xFF);
       
  1455 
       
  1456 			ew32(PCH_RAICC(i),
       
  1457 					e1000_calc_rx_da_crc(mac_addr));
       
  1458 		}
       
  1459 
       
  1460 		/* Write Rx addresses to the PHY */
       
  1461 		e1000_copy_rx_addrs_to_phy_ich8lan(hw);
       
  1462 
       
  1463 		/* Enable jumbo frame workaround in the MAC */
       
  1464 		mac_reg = er32(FFLT_DBG);
       
  1465 		mac_reg &= ~(1 << 14);
       
  1466 		mac_reg |= (7 << 15);
       
  1467 		ew32(FFLT_DBG, mac_reg);
       
  1468 
       
  1469 		mac_reg = er32(RCTL);
       
  1470 		mac_reg |= E1000_RCTL_SECRC;
       
  1471 		ew32(RCTL, mac_reg);
       
  1472 
       
  1473 		ret_val = e1000e_read_kmrn_reg(hw,
       
  1474 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
       
  1475 						&data);
       
  1476 		if (ret_val)
       
  1477 			goto out;
       
  1478 		ret_val = e1000e_write_kmrn_reg(hw,
       
  1479 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
       
  1480 						data | (1 << 0));
       
  1481 		if (ret_val)
       
  1482 			goto out;
       
  1483 		ret_val = e1000e_read_kmrn_reg(hw,
       
  1484 						E1000_KMRNCTRLSTA_HD_CTRL,
       
  1485 						&data);
       
  1486 		if (ret_val)
       
  1487 			goto out;
       
  1488 		data &= ~(0xF << 8);
       
  1489 		data |= (0xB << 8);
       
  1490 		ret_val = e1000e_write_kmrn_reg(hw,
       
  1491 						E1000_KMRNCTRLSTA_HD_CTRL,
       
  1492 						data);
       
  1493 		if (ret_val)
       
  1494 			goto out;
       
  1495 
       
  1496 		/* Enable jumbo frame workaround in the PHY */
       
  1497 		e1e_rphy(hw, PHY_REG(769, 23), &data);
       
  1498 		data &= ~(0x7F << 5);
       
  1499 		data |= (0x37 << 5);
       
  1500 		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
       
  1501 		if (ret_val)
       
  1502 			goto out;
       
  1503 		e1e_rphy(hw, PHY_REG(769, 16), &data);
       
  1504 		data &= ~(1 << 13);
       
  1505 		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
       
  1506 		if (ret_val)
       
  1507 			goto out;
       
  1508 		e1e_rphy(hw, PHY_REG(776, 20), &data);
       
  1509 		data &= ~(0x3FF << 2);
       
  1510 		data |= (0x1A << 2);
       
  1511 		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
       
  1512 		if (ret_val)
       
  1513 			goto out;
       
  1514 		ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
       
  1515 		if (ret_val)
       
  1516 			goto out;
       
  1517 		e1e_rphy(hw, HV_PM_CTRL, &data);
       
  1518 		ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
       
  1519 		if (ret_val)
       
  1520 			goto out;
       
  1521 	} else {
       
  1522 		/* Write MAC register values back to h/w defaults */
       
  1523 		mac_reg = er32(FFLT_DBG);
       
  1524 		mac_reg &= ~(0xF << 14);
       
  1525 		ew32(FFLT_DBG, mac_reg);
       
  1526 
       
  1527 		mac_reg = er32(RCTL);
       
  1528 		mac_reg &= ~E1000_RCTL_SECRC;
       
  1529 		ew32(RCTL, mac_reg);
       
  1530 
       
  1531 		ret_val = e1000e_read_kmrn_reg(hw,
       
  1532 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
       
  1533 						&data);
       
  1534 		if (ret_val)
       
  1535 			goto out;
       
  1536 		ret_val = e1000e_write_kmrn_reg(hw,
       
  1537 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
       
  1538 						data & ~(1 << 0));
       
  1539 		if (ret_val)
       
  1540 			goto out;
       
  1541 		ret_val = e1000e_read_kmrn_reg(hw,
       
  1542 						E1000_KMRNCTRLSTA_HD_CTRL,
       
  1543 						&data);
       
  1544 		if (ret_val)
       
  1545 			goto out;
       
  1546 		data &= ~(0xF << 8);
       
  1547 		data |= (0xB << 8);
       
  1548 		ret_val = e1000e_write_kmrn_reg(hw,
       
  1549 						E1000_KMRNCTRLSTA_HD_CTRL,
       
  1550 						data);
       
  1551 		if (ret_val)
       
  1552 			goto out;
       
  1553 
       
  1554 		/* Write PHY register values back to h/w defaults */
       
  1555 		e1e_rphy(hw, PHY_REG(769, 23), &data);
       
  1556 		data &= ~(0x7F << 5);
       
  1557 		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
       
  1558 		if (ret_val)
       
  1559 			goto out;
       
  1560 		e1e_rphy(hw, PHY_REG(769, 16), &data);
       
  1561 		data |= (1 << 13);
       
  1562 		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
       
  1563 		if (ret_val)
       
  1564 			goto out;
       
  1565 		e1e_rphy(hw, PHY_REG(776, 20), &data);
       
  1566 		data &= ~(0x3FF << 2);
       
  1567 		data |= (0x8 << 2);
       
  1568 		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
       
  1569 		if (ret_val)
       
  1570 			goto out;
       
  1571 		ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
       
  1572 		if (ret_val)
       
  1573 			goto out;
       
  1574 		e1e_rphy(hw, HV_PM_CTRL, &data);
       
  1575 		ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
       
  1576 		if (ret_val)
       
  1577 			goto out;
       
  1578 	}
       
  1579 
       
  1580 	/* re-enable Rx path after enabling/disabling workaround */
       
  1581 	ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
       
  1582 
       
  1583 out:
       
  1584 	return ret_val;
       
  1585 }
       
  1586 
       
  1587 /**
       
  1588  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
       
  1589  *  done after every PHY reset.
       
  1590  **/
       
  1591 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
       
  1592 {
       
  1593 	s32 ret_val = 0;
       
  1594 
       
  1595 	if (hw->mac.type != e1000_pch2lan)
       
  1596 		goto out;
       
  1597 
       
  1598 	/* Set MDIO slow mode before any other MDIO access */
       
  1599 	ret_val = e1000_set_mdio_slow_mode_hv(hw);
       
  1600 
       
  1601 out:
       
  1602 	return ret_val;
       
  1603 }
       
  1604 
       
  1605 /**
       
  1606  *  e1000_k1_gig_workaround_lv - K1 Si workaround
       
  1607  *  @hw:   pointer to the HW structure
       
  1608  *
       
  1609  *  Workaround to set the K1 beacon duration for 82579 parts
       
  1610  **/
       
  1611 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
       
  1612 {
       
  1613 	s32 ret_val = 0;
       
  1614 	u16 status_reg = 0;
       
  1615 	u32 mac_reg;
       
  1616 
       
  1617 	if (hw->mac.type != e1000_pch2lan)
       
  1618 		goto out;
       
  1619 
       
  1620 	/* Set K1 beacon duration based on 1Gbps speed or otherwise */
       
  1621 	ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
       
  1622 	if (ret_val)
       
  1623 		goto out;
       
  1624 
       
  1625 	if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
       
  1626 	    == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
       
  1627 		mac_reg = er32(FEXTNVM4);
       
  1628 		mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
       
  1629 
       
  1630 		if (status_reg & HV_M_STATUS_SPEED_1000)
       
  1631 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
       
  1632 		else
       
  1633 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
       
  1634 
       
  1635 		ew32(FEXTNVM4, mac_reg);
       
  1636 	}
       
  1637 
       
  1638 out:
       
  1639 	return ret_val;
       
  1640 }
       
  1641 
       
  1642 /**
       
  1643  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
       
  1644  *  @hw:   pointer to the HW structure
       
  1645  *  @gate: boolean set to true to gate, false to ungate
       
  1646  *
       
  1647  *  Gate/ungate the automatic PHY configuration via hardware; perform
       
  1648  *  the configuration via software instead.
       
  1649  **/
       
  1650 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
       
  1651 {
       
  1652 	u32 extcnf_ctrl;
       
  1653 
       
  1654 	if (hw->mac.type != e1000_pch2lan)
       
  1655 		return;
       
  1656 
       
  1657 	extcnf_ctrl = er32(EXTCNF_CTRL);
       
  1658 
       
  1659 	if (gate)
       
  1660 		extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
       
  1661 	else
       
  1662 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
       
  1663 
       
  1664 	ew32(EXTCNF_CTRL, extcnf_ctrl);
       
  1665 	return;
       
  1666 }
       
  1667 
       
  1668 /**
       
  1669  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
       
  1670  *  @hw: pointer to the HW structure
       
  1671  *
       
  1672  *  Check the appropriate indication the MAC has finished configuring the
       
  1673  *  PHY after a software reset.
       
  1674  **/
       
  1675 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
       
  1676 {
       
  1677 	u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
       
  1678 
       
  1679 	/* Wait for basic configuration completes before proceeding */
       
  1680 	do {
       
  1681 		data = er32(STATUS);
       
  1682 		data &= E1000_STATUS_LAN_INIT_DONE;
       
  1683 		udelay(100);
       
  1684 	} while ((!data) && --loop);
       
  1685 
       
  1686 	/*
       
  1687 	 * If basic configuration is incomplete before the above loop
       
  1688 	 * count reaches 0, loading the configuration from NVM will
       
  1689 	 * leave the PHY in a bad state possibly resulting in no link.
       
  1690 	 */
       
  1691 	if (loop == 0)
       
  1692 		e_dbg("LAN_INIT_DONE not set, increase timeout\n");
       
  1693 
       
  1694 	/* Clear the Init Done bit for the next init event */
       
  1695 	data = er32(STATUS);
       
  1696 	data &= ~E1000_STATUS_LAN_INIT_DONE;
       
  1697 	ew32(STATUS, data);
       
  1698 }
       
  1699 
       
  1700 /**
       
  1701  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
       
  1702  *  @hw: pointer to the HW structure
       
  1703  **/
       
  1704 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
       
  1705 {
       
  1706 	s32 ret_val = 0;
       
  1707 	u16 reg;
       
  1708 
       
  1709 	if (e1000_check_reset_block(hw))
       
  1710 		goto out;
       
  1711 
       
  1712 	/* Allow time for h/w to get to quiescent state after reset */
       
  1713 	msleep(10);
       
  1714 
       
  1715 	/* Perform any necessary post-reset workarounds */
       
  1716 	switch (hw->mac.type) {
       
  1717 	case e1000_pchlan:
       
  1718 		ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
       
  1719 		if (ret_val)
       
  1720 			goto out;
       
  1721 		break;
       
  1722 	case e1000_pch2lan:
       
  1723 		ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
       
  1724 		if (ret_val)
       
  1725 			goto out;
       
  1726 		break;
       
  1727 	default:
       
  1728 		break;
       
  1729 	}
       
  1730 
       
  1731 	/* Dummy read to clear the phy wakeup bit after lcd reset */
       
  1732 	if (hw->mac.type >= e1000_pchlan)
       
  1733 		e1e_rphy(hw, BM_WUC, &reg);
       
  1734 
       
  1735 	/* Configure the LCD with the extended configuration region in NVM */
       
  1736 	ret_val = e1000_sw_lcd_config_ich8lan(hw);
       
  1737 	if (ret_val)
       
  1738 		goto out;
       
  1739 
       
  1740 	/* Configure the LCD with the OEM bits in NVM */
       
  1741 	ret_val = e1000_oem_bits_config_ich8lan(hw, true);
       
  1742 
       
  1743 	/* Ungate automatic PHY configuration on non-managed 82579 */
       
  1744 	if ((hw->mac.type == e1000_pch2lan) &&
       
  1745 	    !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
       
  1746 		msleep(10);
       
  1747 		e1000_gate_hw_phy_config_ich8lan(hw, false);
       
  1748 	}
       
  1749 
       
  1750 out:
       
  1751 	return ret_val;
       
  1752 }
       
  1753 
       
  1754 /**
       
  1755  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
       
  1756  *  @hw: pointer to the HW structure
       
  1757  *
       
  1758  *  Resets the PHY
       
  1759  *  This is a function pointer entry point called by drivers
       
  1760  *  or other shared routines.
       
  1761  **/
       
  1762 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
       
  1763 {
       
  1764 	s32 ret_val = 0;
       
  1765 
       
  1766 	/* Gate automatic PHY configuration by hardware on non-managed 82579 */
       
  1767 	if ((hw->mac.type == e1000_pch2lan) &&
       
  1768 	    !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
       
  1769 		e1000_gate_hw_phy_config_ich8lan(hw, true);
       
  1770 
       
  1771 	ret_val = e1000e_phy_hw_reset_generic(hw);
       
  1772 	if (ret_val)
       
  1773 		goto out;
       
  1774 
       
  1775 	ret_val = e1000_post_phy_reset_ich8lan(hw);
       
  1776 
       
  1777 out:
       
  1778 	return ret_val;
       
  1779 }
       
  1780 
       
  1781 /**
       
  1782  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
       
  1783  *  @hw: pointer to the HW structure
       
  1784  *  @active: true to enable LPLU, false to disable
       
  1785  *
       
  1786  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
       
  1787  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
       
  1788  *  the phy speed. This function will manually set the LPLU bit and restart
       
  1789  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
       
  1790  *  since it configures the same bit.
       
  1791  **/
       
  1792 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
       
  1793 {
       
  1794 	s32 ret_val = 0;
       
  1795 	u16 oem_reg;
       
  1796 
       
  1797 	ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
       
  1798 	if (ret_val)
       
  1799 		goto out;
       
  1800 
       
  1801 	if (active)
       
  1802 		oem_reg |= HV_OEM_BITS_LPLU;
       
  1803 	else
       
  1804 		oem_reg &= ~HV_OEM_BITS_LPLU;
       
  1805 
       
  1806 	oem_reg |= HV_OEM_BITS_RESTART_AN;
       
  1807 	ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
       
  1808 
       
  1809 out:
       
  1810 	return ret_val;
       
  1811 }
       
  1812 
       
  1813 /**
       
  1814  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
       
  1815  *  @hw: pointer to the HW structure
       
  1816  *  @active: true to enable LPLU, false to disable
       
  1817  *
       
  1818  *  Sets the LPLU D0 state according to the active flag.  When
       
  1819  *  activating LPLU this function also disables smart speed
       
  1820  *  and vice versa.  LPLU will not be activated unless the
       
  1821  *  device autonegotiation advertisement meets standards of
       
  1822  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
       
  1823  *  This is a function pointer entry point only called by
       
  1824  *  PHY setup routines.
       
  1825  **/
       
  1826 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
       
  1827 {
       
  1828 	struct e1000_phy_info *phy = &hw->phy;
       
  1829 	u32 phy_ctrl;
       
  1830 	s32 ret_val = 0;
       
  1831 	u16 data;
       
  1832 
       
  1833 	if (phy->type == e1000_phy_ife)
       
  1834 		return ret_val;
       
  1835 
       
  1836 	phy_ctrl = er32(PHY_CTRL);
       
  1837 
       
  1838 	if (active) {
       
  1839 		phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
       
  1840 		ew32(PHY_CTRL, phy_ctrl);
       
  1841 
       
  1842 		if (phy->type != e1000_phy_igp_3)
       
  1843 			return 0;
       
  1844 
       
  1845 		/*
       
  1846 		 * Call gig speed drop workaround on LPLU before accessing
       
  1847 		 * any PHY registers
       
  1848 		 */
       
  1849 		if (hw->mac.type == e1000_ich8lan)
       
  1850 			e1000e_gig_downshift_workaround_ich8lan(hw);
       
  1851 
       
  1852 		/* When LPLU is enabled, we should disable SmartSpeed */
       
  1853 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
       
  1854 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
       
  1855 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
       
  1856 		if (ret_val)
       
  1857 			return ret_val;
       
  1858 	} else {
       
  1859 		phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
       
  1860 		ew32(PHY_CTRL, phy_ctrl);
       
  1861 
       
  1862 		if (phy->type != e1000_phy_igp_3)
       
  1863 			return 0;
       
  1864 
       
  1865 		/*
       
  1866 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
       
  1867 		 * during Dx states where the power conservation is most
       
  1868 		 * important.  During driver activity we should enable
       
  1869 		 * SmartSpeed, so performance is maintained.
       
  1870 		 */
       
  1871 		if (phy->smart_speed == e1000_smart_speed_on) {
       
  1872 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1873 					   &data);
       
  1874 			if (ret_val)
       
  1875 				return ret_val;
       
  1876 
       
  1877 			data |= IGP01E1000_PSCFR_SMART_SPEED;
       
  1878 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1879 					   data);
       
  1880 			if (ret_val)
       
  1881 				return ret_val;
       
  1882 		} else if (phy->smart_speed == e1000_smart_speed_off) {
       
  1883 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1884 					   &data);
       
  1885 			if (ret_val)
       
  1886 				return ret_val;
       
  1887 
       
  1888 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
       
  1889 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1890 					   data);
       
  1891 			if (ret_val)
       
  1892 				return ret_val;
       
  1893 		}
       
  1894 	}
       
  1895 
       
  1896 	return 0;
       
  1897 }
       
  1898 
       
  1899 /**
       
  1900  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
       
  1901  *  @hw: pointer to the HW structure
       
  1902  *  @active: true to enable LPLU, false to disable
       
  1903  *
       
  1904  *  Sets the LPLU D3 state according to the active flag.  When
       
  1905  *  activating LPLU this function also disables smart speed
       
  1906  *  and vice versa.  LPLU will not be activated unless the
       
  1907  *  device autonegotiation advertisement meets standards of
       
  1908  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
       
  1909  *  This is a function pointer entry point only called by
       
  1910  *  PHY setup routines.
       
  1911  **/
       
  1912 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
       
  1913 {
       
  1914 	struct e1000_phy_info *phy = &hw->phy;
       
  1915 	u32 phy_ctrl;
       
  1916 	s32 ret_val;
       
  1917 	u16 data;
       
  1918 
       
  1919 	phy_ctrl = er32(PHY_CTRL);
       
  1920 
       
  1921 	if (!active) {
       
  1922 		phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
       
  1923 		ew32(PHY_CTRL, phy_ctrl);
       
  1924 
       
  1925 		if (phy->type != e1000_phy_igp_3)
       
  1926 			return 0;
       
  1927 
       
  1928 		/*
       
  1929 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
       
  1930 		 * during Dx states where the power conservation is most
       
  1931 		 * important.  During driver activity we should enable
       
  1932 		 * SmartSpeed, so performance is maintained.
       
  1933 		 */
       
  1934 		if (phy->smart_speed == e1000_smart_speed_on) {
       
  1935 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1936 					   &data);
       
  1937 			if (ret_val)
       
  1938 				return ret_val;
       
  1939 
       
  1940 			data |= IGP01E1000_PSCFR_SMART_SPEED;
       
  1941 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1942 					   data);
       
  1943 			if (ret_val)
       
  1944 				return ret_val;
       
  1945 		} else if (phy->smart_speed == e1000_smart_speed_off) {
       
  1946 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1947 					   &data);
       
  1948 			if (ret_val)
       
  1949 				return ret_val;
       
  1950 
       
  1951 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
       
  1952 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1953 					   data);
       
  1954 			if (ret_val)
       
  1955 				return ret_val;
       
  1956 		}
       
  1957 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
       
  1958 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
       
  1959 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
       
  1960 		phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
       
  1961 		ew32(PHY_CTRL, phy_ctrl);
       
  1962 
       
  1963 		if (phy->type != e1000_phy_igp_3)
       
  1964 			return 0;
       
  1965 
       
  1966 		/*
       
  1967 		 * Call gig speed drop workaround on LPLU before accessing
       
  1968 		 * any PHY registers
       
  1969 		 */
       
  1970 		if (hw->mac.type == e1000_ich8lan)
       
  1971 			e1000e_gig_downshift_workaround_ich8lan(hw);
       
  1972 
       
  1973 		/* When LPLU is enabled, we should disable SmartSpeed */
       
  1974 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
       
  1975 		if (ret_val)
       
  1976 			return ret_val;
       
  1977 
       
  1978 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
       
  1979 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
       
  1980 	}
       
  1981 
       
  1982 	return 0;
       
  1983 }
       
  1984 
       
  1985 /**
       
  1986  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
       
  1987  *  @hw: pointer to the HW structure
       
  1988  *  @bank:  pointer to the variable that returns the active bank
       
  1989  *
       
  1990  *  Reads signature byte from the NVM using the flash access registers.
       
  1991  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
       
  1992  **/
       
  1993 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
       
  1994 {
       
  1995 	u32 eecd;
       
  1996 	struct e1000_nvm_info *nvm = &hw->nvm;
       
  1997 	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
       
  1998 	u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
       
  1999 	u8 sig_byte = 0;
       
  2000 	s32 ret_val = 0;
       
  2001 
       
  2002 	switch (hw->mac.type) {
       
  2003 	case e1000_ich8lan:
       
  2004 	case e1000_ich9lan:
       
  2005 		eecd = er32(EECD);
       
  2006 		if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
       
  2007 		    E1000_EECD_SEC1VAL_VALID_MASK) {
       
  2008 			if (eecd & E1000_EECD_SEC1VAL)
       
  2009 				*bank = 1;
       
  2010 			else
       
  2011 				*bank = 0;
       
  2012 
       
  2013 			return 0;
       
  2014 		}
       
  2015 		e_dbg("Unable to determine valid NVM bank via EEC - "
       
  2016 		       "reading flash signature\n");
       
  2017 		/* fall-thru */
       
  2018 	default:
       
  2019 		/* set bank to 0 in case flash read fails */
       
  2020 		*bank = 0;
       
  2021 
       
  2022 		/* Check bank 0 */
       
  2023 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
       
  2024 		                                        &sig_byte);
       
  2025 		if (ret_val)
       
  2026 			return ret_val;
       
  2027 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
       
  2028 		    E1000_ICH_NVM_SIG_VALUE) {
       
  2029 			*bank = 0;
       
  2030 			return 0;
       
  2031 		}
       
  2032 
       
  2033 		/* Check bank 1 */
       
  2034 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
       
  2035 		                                        bank1_offset,
       
  2036 		                                        &sig_byte);
       
  2037 		if (ret_val)
       
  2038 			return ret_val;
       
  2039 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
       
  2040 		    E1000_ICH_NVM_SIG_VALUE) {
       
  2041 			*bank = 1;
       
  2042 			return 0;
       
  2043 		}
       
  2044 
       
  2045 		e_dbg("ERROR: No valid NVM bank present\n");
       
  2046 		return -E1000_ERR_NVM;
       
  2047 	}
       
  2048 
       
  2049 	return 0;
       
  2050 }
       
  2051 
       
  2052 /**
       
  2053  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
       
  2054  *  @hw: pointer to the HW structure
       
  2055  *  @offset: The offset (in bytes) of the word(s) to read.
       
  2056  *  @words: Size of data to read in words
       
  2057  *  @data: Pointer to the word(s) to read at offset.
       
  2058  *
       
  2059  *  Reads a word(s) from the NVM using the flash access registers.
       
  2060  **/
       
  2061 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
       
  2062 				  u16 *data)
       
  2063 {
       
  2064 	struct e1000_nvm_info *nvm = &hw->nvm;
       
  2065 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
       
  2066 	u32 act_offset;
       
  2067 	s32 ret_val = 0;
       
  2068 	u32 bank = 0;
       
  2069 	u16 i, word;
       
  2070 
       
  2071 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
       
  2072 	    (words == 0)) {
       
  2073 		e_dbg("nvm parameter(s) out of bounds\n");
       
  2074 		ret_val = -E1000_ERR_NVM;
       
  2075 		goto out;
       
  2076 	}
       
  2077 
       
  2078 	nvm->ops.acquire(hw);
       
  2079 
       
  2080 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
       
  2081 	if (ret_val) {
       
  2082 		e_dbg("Could not detect valid bank, assuming bank 0\n");
       
  2083 		bank = 0;
       
  2084 	}
       
  2085 
       
  2086 	act_offset = (bank) ? nvm->flash_bank_size : 0;
       
  2087 	act_offset += offset;
       
  2088 
       
  2089 	ret_val = 0;
       
  2090 	for (i = 0; i < words; i++) {
       
  2091 		if ((dev_spec->shadow_ram) &&
       
  2092 		    (dev_spec->shadow_ram[offset+i].modified)) {
       
  2093 			data[i] = dev_spec->shadow_ram[offset+i].value;
       
  2094 		} else {
       
  2095 			ret_val = e1000_read_flash_word_ich8lan(hw,
       
  2096 								act_offset + i,
       
  2097 								&word);
       
  2098 			if (ret_val)
       
  2099 				break;
       
  2100 			data[i] = word;
       
  2101 		}
       
  2102 	}
       
  2103 
       
  2104 	nvm->ops.release(hw);
       
  2105 
       
  2106 out:
       
  2107 	if (ret_val)
       
  2108 		e_dbg("NVM read error: %d\n", ret_val);
       
  2109 
       
  2110 	return ret_val;
       
  2111 }
       
  2112 
       
  2113 /**
       
  2114  *  e1000_flash_cycle_init_ich8lan - Initialize flash
       
  2115  *  @hw: pointer to the HW structure
       
  2116  *
       
  2117  *  This function does initial flash setup so that a new read/write/erase cycle
       
  2118  *  can be started.
       
  2119  **/
       
  2120 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
       
  2121 {
       
  2122 	union ich8_hws_flash_status hsfsts;
       
  2123 	s32 ret_val = -E1000_ERR_NVM;
       
  2124 	s32 i = 0;
       
  2125 
       
  2126 	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
       
  2127 
       
  2128 	/* Check if the flash descriptor is valid */
       
  2129 	if (hsfsts.hsf_status.fldesvalid == 0) {
       
  2130 		e_dbg("Flash descriptor invalid.  "
       
  2131 			 "SW Sequencing must be used.\n");
       
  2132 		return -E1000_ERR_NVM;
       
  2133 	}
       
  2134 
       
  2135 	/* Clear FCERR and DAEL in hw status by writing 1 */
       
  2136 	hsfsts.hsf_status.flcerr = 1;
       
  2137 	hsfsts.hsf_status.dael = 1;
       
  2138 
       
  2139 	ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
       
  2140 
       
  2141 	/*
       
  2142 	 * Either we should have a hardware SPI cycle in progress
       
  2143 	 * bit to check against, in order to start a new cycle or
       
  2144 	 * FDONE bit should be changed in the hardware so that it
       
  2145 	 * is 1 after hardware reset, which can then be used as an
       
  2146 	 * indication whether a cycle is in progress or has been
       
  2147 	 * completed.
       
  2148 	 */
       
  2149 
       
  2150 	if (hsfsts.hsf_status.flcinprog == 0) {
       
  2151 		/*
       
  2152 		 * There is no cycle running at present,
       
  2153 		 * so we can start a cycle.
       
  2154 		 * Begin by setting Flash Cycle Done.
       
  2155 		 */
       
  2156 		hsfsts.hsf_status.flcdone = 1;
       
  2157 		ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
       
  2158 		ret_val = 0;
       
  2159 	} else {
       
  2160 		/*
       
  2161 		 * Otherwise poll for sometime so the current
       
  2162 		 * cycle has a chance to end before giving up.
       
  2163 		 */
       
  2164 		for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
       
  2165 			hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
       
  2166 			if (hsfsts.hsf_status.flcinprog == 0) {
       
  2167 				ret_val = 0;
       
  2168 				break;
       
  2169 			}
       
  2170 			udelay(1);
       
  2171 		}
       
  2172 		if (ret_val == 0) {
       
  2173 			/*
       
  2174 			 * Successful in waiting for previous cycle to timeout,
       
  2175 			 * now set the Flash Cycle Done.
       
  2176 			 */
       
  2177 			hsfsts.hsf_status.flcdone = 1;
       
  2178 			ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
       
  2179 		} else {
       
  2180 			e_dbg("Flash controller busy, cannot get access\n");
       
  2181 		}
       
  2182 	}
       
  2183 
       
  2184 	return ret_val;
       
  2185 }
       
  2186 
       
  2187 /**
       
  2188  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
       
  2189  *  @hw: pointer to the HW structure
       
  2190  *  @timeout: maximum time to wait for completion
       
  2191  *
       
  2192  *  This function starts a flash cycle and waits for its completion.
       
  2193  **/
       
  2194 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
       
  2195 {
       
  2196 	union ich8_hws_flash_ctrl hsflctl;
       
  2197 	union ich8_hws_flash_status hsfsts;
       
  2198 	s32 ret_val = -E1000_ERR_NVM;
       
  2199 	u32 i = 0;
       
  2200 
       
  2201 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
       
  2202 	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
       
  2203 	hsflctl.hsf_ctrl.flcgo = 1;
       
  2204 	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
       
  2205 
       
  2206 	/* wait till FDONE bit is set to 1 */
       
  2207 	do {
       
  2208 		hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
       
  2209 		if (hsfsts.hsf_status.flcdone == 1)
       
  2210 			break;
       
  2211 		udelay(1);
       
  2212 	} while (i++ < timeout);
       
  2213 
       
  2214 	if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
       
  2215 		return 0;
       
  2216 
       
  2217 	return ret_val;
       
  2218 }
       
  2219 
       
  2220 /**
       
  2221  *  e1000_read_flash_word_ich8lan - Read word from flash
       
  2222  *  @hw: pointer to the HW structure
       
  2223  *  @offset: offset to data location
       
  2224  *  @data: pointer to the location for storing the data
       
  2225  *
       
  2226  *  Reads the flash word at offset into data.  Offset is converted
       
  2227  *  to bytes before read.
       
  2228  **/
       
  2229 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
       
  2230 					 u16 *data)
       
  2231 {
       
  2232 	/* Must convert offset into bytes. */
       
  2233 	offset <<= 1;
       
  2234 
       
  2235 	return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
       
  2236 }
       
  2237 
       
  2238 /**
       
  2239  *  e1000_read_flash_byte_ich8lan - Read byte from flash
       
  2240  *  @hw: pointer to the HW structure
       
  2241  *  @offset: The offset of the byte to read.
       
  2242  *  @data: Pointer to a byte to store the value read.
       
  2243  *
       
  2244  *  Reads a single byte from the NVM using the flash access registers.
       
  2245  **/
       
  2246 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
       
  2247 					 u8 *data)
       
  2248 {
       
  2249 	s32 ret_val;
       
  2250 	u16 word = 0;
       
  2251 
       
  2252 	ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
       
  2253 	if (ret_val)
       
  2254 		return ret_val;
       
  2255 
       
  2256 	*data = (u8)word;
       
  2257 
       
  2258 	return 0;
       
  2259 }
       
  2260 
       
  2261 /**
       
  2262  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
       
  2263  *  @hw: pointer to the HW structure
       
  2264  *  @offset: The offset (in bytes) of the byte or word to read.
       
  2265  *  @size: Size of data to read, 1=byte 2=word
       
  2266  *  @data: Pointer to the word to store the value read.
       
  2267  *
       
  2268  *  Reads a byte or word from the NVM using the flash access registers.
       
  2269  **/
       
  2270 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
       
  2271 					 u8 size, u16 *data)
       
  2272 {
       
  2273 	union ich8_hws_flash_status hsfsts;
       
  2274 	union ich8_hws_flash_ctrl hsflctl;
       
  2275 	u32 flash_linear_addr;
       
  2276 	u32 flash_data = 0;
       
  2277 	s32 ret_val = -E1000_ERR_NVM;
       
  2278 	u8 count = 0;
       
  2279 
       
  2280 	if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
       
  2281 		return -E1000_ERR_NVM;
       
  2282 
       
  2283 	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
       
  2284 			    hw->nvm.flash_base_addr;
       
  2285 
       
  2286 	do {
       
  2287 		udelay(1);
       
  2288 		/* Steps */
       
  2289 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
       
  2290 		if (ret_val != 0)
       
  2291 			break;
       
  2292 
       
  2293 		hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
       
  2294 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
       
  2295 		hsflctl.hsf_ctrl.fldbcount = size - 1;
       
  2296 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
       
  2297 		ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
       
  2298 
       
  2299 		ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
       
  2300 
       
  2301 		ret_val = e1000_flash_cycle_ich8lan(hw,
       
  2302 						ICH_FLASH_READ_COMMAND_TIMEOUT);
       
  2303 
       
  2304 		/*
       
  2305 		 * Check if FCERR is set to 1, if set to 1, clear it
       
  2306 		 * and try the whole sequence a few more times, else
       
  2307 		 * read in (shift in) the Flash Data0, the order is
       
  2308 		 * least significant byte first msb to lsb
       
  2309 		 */
       
  2310 		if (ret_val == 0) {
       
  2311 			flash_data = er32flash(ICH_FLASH_FDATA0);
       
  2312 			if (size == 1) {
       
  2313 				*data = (u8)(flash_data & 0x000000FF);
       
  2314 			} else if (size == 2) {
       
  2315 				*data = (u16)(flash_data & 0x0000FFFF);
       
  2316 			}
       
  2317 			break;
       
  2318 		} else {
       
  2319 			/*
       
  2320 			 * If we've gotten here, then things are probably
       
  2321 			 * completely hosed, but if the error condition is
       
  2322 			 * detected, it won't hurt to give it another try...
       
  2323 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
       
  2324 			 */
       
  2325 			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
       
  2326 			if (hsfsts.hsf_status.flcerr == 1) {
       
  2327 				/* Repeat for some time before giving up. */
       
  2328 				continue;
       
  2329 			} else if (hsfsts.hsf_status.flcdone == 0) {
       
  2330 				e_dbg("Timeout error - flash cycle "
       
  2331 					 "did not complete.\n");
       
  2332 				break;
       
  2333 			}
       
  2334 		}
       
  2335 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
       
  2336 
       
  2337 	return ret_val;
       
  2338 }
       
  2339 
       
  2340 /**
       
  2341  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
       
  2342  *  @hw: pointer to the HW structure
       
  2343  *  @offset: The offset (in bytes) of the word(s) to write.
       
  2344  *  @words: Size of data to write in words
       
  2345  *  @data: Pointer to the word(s) to write at offset.
       
  2346  *
       
  2347  *  Writes a byte or word to the NVM using the flash access registers.
       
  2348  **/
       
  2349 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
       
  2350 				   u16 *data)
       
  2351 {
       
  2352 	struct e1000_nvm_info *nvm = &hw->nvm;
       
  2353 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
       
  2354 	u16 i;
       
  2355 
       
  2356 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
       
  2357 	    (words == 0)) {
       
  2358 		e_dbg("nvm parameter(s) out of bounds\n");
       
  2359 		return -E1000_ERR_NVM;
       
  2360 	}
       
  2361 
       
  2362 	nvm->ops.acquire(hw);
       
  2363 
       
  2364 	for (i = 0; i < words; i++) {
       
  2365 		dev_spec->shadow_ram[offset+i].modified = true;
       
  2366 		dev_spec->shadow_ram[offset+i].value = data[i];
       
  2367 	}
       
  2368 
       
  2369 	nvm->ops.release(hw);
       
  2370 
       
  2371 	return 0;
       
  2372 }
       
  2373 
       
  2374 /**
       
  2375  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
       
  2376  *  @hw: pointer to the HW structure
       
  2377  *
       
  2378  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
       
  2379  *  which writes the checksum to the shadow ram.  The changes in the shadow
       
  2380  *  ram are then committed to the EEPROM by processing each bank at a time
       
  2381  *  checking for the modified bit and writing only the pending changes.
       
  2382  *  After a successful commit, the shadow ram is cleared and is ready for
       
  2383  *  future writes.
       
  2384  **/
       
  2385 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
       
  2386 {
       
  2387 	struct e1000_nvm_info *nvm = &hw->nvm;
       
  2388 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
       
  2389 	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
       
  2390 	s32 ret_val;
       
  2391 	u16 data;
       
  2392 
       
  2393 	ret_val = e1000e_update_nvm_checksum_generic(hw);
       
  2394 	if (ret_val)
       
  2395 		goto out;
       
  2396 
       
  2397 	if (nvm->type != e1000_nvm_flash_sw)
       
  2398 		goto out;
       
  2399 
       
  2400 	nvm->ops.acquire(hw);
       
  2401 
       
  2402 	/*
       
  2403 	 * We're writing to the opposite bank so if we're on bank 1,
       
  2404 	 * write to bank 0 etc.  We also need to erase the segment that
       
  2405 	 * is going to be written
       
  2406 	 */
       
  2407 	ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
       
  2408 	if (ret_val) {
       
  2409 		e_dbg("Could not detect valid bank, assuming bank 0\n");
       
  2410 		bank = 0;
       
  2411 	}
       
  2412 
       
  2413 	if (bank == 0) {
       
  2414 		new_bank_offset = nvm->flash_bank_size;
       
  2415 		old_bank_offset = 0;
       
  2416 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
       
  2417 		if (ret_val)
       
  2418 			goto release;
       
  2419 	} else {
       
  2420 		old_bank_offset = nvm->flash_bank_size;
       
  2421 		new_bank_offset = 0;
       
  2422 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
       
  2423 		if (ret_val)
       
  2424 			goto release;
       
  2425 	}
       
  2426 
       
  2427 	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
       
  2428 		/*
       
  2429 		 * Determine whether to write the value stored
       
  2430 		 * in the other NVM bank or a modified value stored
       
  2431 		 * in the shadow RAM
       
  2432 		 */
       
  2433 		if (dev_spec->shadow_ram[i].modified) {
       
  2434 			data = dev_spec->shadow_ram[i].value;
       
  2435 		} else {
       
  2436 			ret_val = e1000_read_flash_word_ich8lan(hw, i +
       
  2437 			                                        old_bank_offset,
       
  2438 			                                        &data);
       
  2439 			if (ret_val)
       
  2440 				break;
       
  2441 		}
       
  2442 
       
  2443 		/*
       
  2444 		 * If the word is 0x13, then make sure the signature bits
       
  2445 		 * (15:14) are 11b until the commit has completed.
       
  2446 		 * This will allow us to write 10b which indicates the
       
  2447 		 * signature is valid.  We want to do this after the write
       
  2448 		 * has completed so that we don't mark the segment valid
       
  2449 		 * while the write is still in progress
       
  2450 		 */
       
  2451 		if (i == E1000_ICH_NVM_SIG_WORD)
       
  2452 			data |= E1000_ICH_NVM_SIG_MASK;
       
  2453 
       
  2454 		/* Convert offset to bytes. */
       
  2455 		act_offset = (i + new_bank_offset) << 1;
       
  2456 
       
  2457 		udelay(100);
       
  2458 		/* Write the bytes to the new bank. */
       
  2459 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
       
  2460 							       act_offset,
       
  2461 							       (u8)data);
       
  2462 		if (ret_val)
       
  2463 			break;
       
  2464 
       
  2465 		udelay(100);
       
  2466 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
       
  2467 							  act_offset + 1,
       
  2468 							  (u8)(data >> 8));
       
  2469 		if (ret_val)
       
  2470 			break;
       
  2471 	}
       
  2472 
       
  2473 	/*
       
  2474 	 * Don't bother writing the segment valid bits if sector
       
  2475 	 * programming failed.
       
  2476 	 */
       
  2477 	if (ret_val) {
       
  2478 		/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
       
  2479 		e_dbg("Flash commit failed.\n");
       
  2480 		goto release;
       
  2481 	}
       
  2482 
       
  2483 	/*
       
  2484 	 * Finally validate the new segment by setting bit 15:14
       
  2485 	 * to 10b in word 0x13 , this can be done without an
       
  2486 	 * erase as well since these bits are 11 to start with
       
  2487 	 * and we need to change bit 14 to 0b
       
  2488 	 */
       
  2489 	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
       
  2490 	ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
       
  2491 	if (ret_val)
       
  2492 		goto release;
       
  2493 
       
  2494 	data &= 0xBFFF;
       
  2495 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
       
  2496 						       act_offset * 2 + 1,
       
  2497 						       (u8)(data >> 8));
       
  2498 	if (ret_val)
       
  2499 		goto release;
       
  2500 
       
  2501 	/*
       
  2502 	 * And invalidate the previously valid segment by setting
       
  2503 	 * its signature word (0x13) high_byte to 0b. This can be
       
  2504 	 * done without an erase because flash erase sets all bits
       
  2505 	 * to 1's. We can write 1's to 0's without an erase
       
  2506 	 */
       
  2507 	act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
       
  2508 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
       
  2509 	if (ret_val)
       
  2510 		goto release;
       
  2511 
       
  2512 	/* Great!  Everything worked, we can now clear the cached entries. */
       
  2513 	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
       
  2514 		dev_spec->shadow_ram[i].modified = false;
       
  2515 		dev_spec->shadow_ram[i].value = 0xFFFF;
       
  2516 	}
       
  2517 
       
  2518 release:
       
  2519 	nvm->ops.release(hw);
       
  2520 
       
  2521 	/*
       
  2522 	 * Reload the EEPROM, or else modifications will not appear
       
  2523 	 * until after the next adapter reset.
       
  2524 	 */
       
  2525 	if (!ret_val) {
       
  2526 		e1000e_reload_nvm(hw);
       
  2527 		msleep(10);
       
  2528 	}
       
  2529 
       
  2530 out:
       
  2531 	if (ret_val)
       
  2532 		e_dbg("NVM update error: %d\n", ret_val);
       
  2533 
       
  2534 	return ret_val;
       
  2535 }
       
  2536 
       
  2537 /**
       
  2538  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
       
  2539  *  @hw: pointer to the HW structure
       
  2540  *
       
  2541  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
       
  2542  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
       
  2543  *  calculated, in which case we need to calculate the checksum and set bit 6.
       
  2544  **/
       
  2545 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
       
  2546 {
       
  2547 	s32 ret_val;
       
  2548 	u16 data;
       
  2549 
       
  2550 	/*
       
  2551 	 * Read 0x19 and check bit 6.  If this bit is 0, the checksum
       
  2552 	 * needs to be fixed.  This bit is an indication that the NVM
       
  2553 	 * was prepared by OEM software and did not calculate the
       
  2554 	 * checksum...a likely scenario.
       
  2555 	 */
       
  2556 	ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
       
  2557 	if (ret_val)
       
  2558 		return ret_val;
       
  2559 
       
  2560 	if ((data & 0x40) == 0) {
       
  2561 		data |= 0x40;
       
  2562 		ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
       
  2563 		if (ret_val)
       
  2564 			return ret_val;
       
  2565 		ret_val = e1000e_update_nvm_checksum(hw);
       
  2566 		if (ret_val)
       
  2567 			return ret_val;
       
  2568 	}
       
  2569 
       
  2570 	return e1000e_validate_nvm_checksum_generic(hw);
       
  2571 }
       
  2572 
       
  2573 /**
       
  2574  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
       
  2575  *  @hw: pointer to the HW structure
       
  2576  *
       
  2577  *  To prevent malicious write/erase of the NVM, set it to be read-only
       
  2578  *  so that the hardware ignores all write/erase cycles of the NVM via
       
  2579  *  the flash control registers.  The shadow-ram copy of the NVM will
       
  2580  *  still be updated, however any updates to this copy will not stick
       
  2581  *  across driver reloads.
       
  2582  **/
       
  2583 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
       
  2584 {
       
  2585 	struct e1000_nvm_info *nvm = &hw->nvm;
       
  2586 	union ich8_flash_protected_range pr0;
       
  2587 	union ich8_hws_flash_status hsfsts;
       
  2588 	u32 gfpreg;
       
  2589 
       
  2590 	nvm->ops.acquire(hw);
       
  2591 
       
  2592 	gfpreg = er32flash(ICH_FLASH_GFPREG);
       
  2593 
       
  2594 	/* Write-protect GbE Sector of NVM */
       
  2595 	pr0.regval = er32flash(ICH_FLASH_PR0);
       
  2596 	pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
       
  2597 	pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
       
  2598 	pr0.range.wpe = true;
       
  2599 	ew32flash(ICH_FLASH_PR0, pr0.regval);
       
  2600 
       
  2601 	/*
       
  2602 	 * Lock down a subset of GbE Flash Control Registers, e.g.
       
  2603 	 * PR0 to prevent the write-protection from being lifted.
       
  2604 	 * Once FLOCKDN is set, the registers protected by it cannot
       
  2605 	 * be written until FLOCKDN is cleared by a hardware reset.
       
  2606 	 */
       
  2607 	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
       
  2608 	hsfsts.hsf_status.flockdn = true;
       
  2609 	ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
       
  2610 
       
  2611 	nvm->ops.release(hw);
       
  2612 }
       
  2613 
       
  2614 /**
       
  2615  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
       
  2616  *  @hw: pointer to the HW structure
       
  2617  *  @offset: The offset (in bytes) of the byte/word to read.
       
  2618  *  @size: Size of data to read, 1=byte 2=word
       
  2619  *  @data: The byte(s) to write to the NVM.
       
  2620  *
       
  2621  *  Writes one/two bytes to the NVM using the flash access registers.
       
  2622  **/
       
  2623 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
       
  2624 					  u8 size, u16 data)
       
  2625 {
       
  2626 	union ich8_hws_flash_status hsfsts;
       
  2627 	union ich8_hws_flash_ctrl hsflctl;
       
  2628 	u32 flash_linear_addr;
       
  2629 	u32 flash_data = 0;
       
  2630 	s32 ret_val;
       
  2631 	u8 count = 0;
       
  2632 
       
  2633 	if (size < 1 || size > 2 || data > size * 0xff ||
       
  2634 	    offset > ICH_FLASH_LINEAR_ADDR_MASK)
       
  2635 		return -E1000_ERR_NVM;
       
  2636 
       
  2637 	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
       
  2638 			    hw->nvm.flash_base_addr;
       
  2639 
       
  2640 	do {
       
  2641 		udelay(1);
       
  2642 		/* Steps */
       
  2643 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
       
  2644 		if (ret_val)
       
  2645 			break;
       
  2646 
       
  2647 		hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
       
  2648 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
       
  2649 		hsflctl.hsf_ctrl.fldbcount = size -1;
       
  2650 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
       
  2651 		ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
       
  2652 
       
  2653 		ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
       
  2654 
       
  2655 		if (size == 1)
       
  2656 			flash_data = (u32)data & 0x00FF;
       
  2657 		else
       
  2658 			flash_data = (u32)data;
       
  2659 
       
  2660 		ew32flash(ICH_FLASH_FDATA0, flash_data);
       
  2661 
       
  2662 		/*
       
  2663 		 * check if FCERR is set to 1 , if set to 1, clear it
       
  2664 		 * and try the whole sequence a few more times else done
       
  2665 		 */
       
  2666 		ret_val = e1000_flash_cycle_ich8lan(hw,
       
  2667 					       ICH_FLASH_WRITE_COMMAND_TIMEOUT);
       
  2668 		if (!ret_val)
       
  2669 			break;
       
  2670 
       
  2671 		/*
       
  2672 		 * If we're here, then things are most likely
       
  2673 		 * completely hosed, but if the error condition
       
  2674 		 * is detected, it won't hurt to give it another
       
  2675 		 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
       
  2676 		 */
       
  2677 		hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
       
  2678 		if (hsfsts.hsf_status.flcerr == 1)
       
  2679 			/* Repeat for some time before giving up. */
       
  2680 			continue;
       
  2681 		if (hsfsts.hsf_status.flcdone == 0) {
       
  2682 			e_dbg("Timeout error - flash cycle "
       
  2683 				 "did not complete.");
       
  2684 			break;
       
  2685 		}
       
  2686 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
       
  2687 
       
  2688 	return ret_val;
       
  2689 }
       
  2690 
       
  2691 /**
       
  2692  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
       
  2693  *  @hw: pointer to the HW structure
       
  2694  *  @offset: The index of the byte to read.
       
  2695  *  @data: The byte to write to the NVM.
       
  2696  *
       
  2697  *  Writes a single byte to the NVM using the flash access registers.
       
  2698  **/
       
  2699 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
       
  2700 					  u8 data)
       
  2701 {
       
  2702 	u16 word = (u16)data;
       
  2703 
       
  2704 	return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
       
  2705 }
       
  2706 
       
  2707 /**
       
  2708  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
       
  2709  *  @hw: pointer to the HW structure
       
  2710  *  @offset: The offset of the byte to write.
       
  2711  *  @byte: The byte to write to the NVM.
       
  2712  *
       
  2713  *  Writes a single byte to the NVM using the flash access registers.
       
  2714  *  Goes through a retry algorithm before giving up.
       
  2715  **/
       
  2716 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
       
  2717 						u32 offset, u8 byte)
       
  2718 {
       
  2719 	s32 ret_val;
       
  2720 	u16 program_retries;
       
  2721 
       
  2722 	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
       
  2723 	if (!ret_val)
       
  2724 		return ret_val;
       
  2725 
       
  2726 	for (program_retries = 0; program_retries < 100; program_retries++) {
       
  2727 		e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
       
  2728 		udelay(100);
       
  2729 		ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
       
  2730 		if (!ret_val)
       
  2731 			break;
       
  2732 	}
       
  2733 	if (program_retries == 100)
       
  2734 		return -E1000_ERR_NVM;
       
  2735 
       
  2736 	return 0;
       
  2737 }
       
  2738 
       
  2739 /**
       
  2740  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
       
  2741  *  @hw: pointer to the HW structure
       
  2742  *  @bank: 0 for first bank, 1 for second bank, etc.
       
  2743  *
       
  2744  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
       
  2745  *  bank N is 4096 * N + flash_reg_addr.
       
  2746  **/
       
  2747 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
       
  2748 {
       
  2749 	struct e1000_nvm_info *nvm = &hw->nvm;
       
  2750 	union ich8_hws_flash_status hsfsts;
       
  2751 	union ich8_hws_flash_ctrl hsflctl;
       
  2752 	u32 flash_linear_addr;
       
  2753 	/* bank size is in 16bit words - adjust to bytes */
       
  2754 	u32 flash_bank_size = nvm->flash_bank_size * 2;
       
  2755 	s32 ret_val;
       
  2756 	s32 count = 0;
       
  2757 	s32 j, iteration, sector_size;
       
  2758 
       
  2759 	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
       
  2760 
       
  2761 	/*
       
  2762 	 * Determine HW Sector size: Read BERASE bits of hw flash status
       
  2763 	 * register
       
  2764 	 * 00: The Hw sector is 256 bytes, hence we need to erase 16
       
  2765 	 *     consecutive sectors.  The start index for the nth Hw sector
       
  2766 	 *     can be calculated as = bank * 4096 + n * 256
       
  2767 	 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
       
  2768 	 *     The start index for the nth Hw sector can be calculated
       
  2769 	 *     as = bank * 4096
       
  2770 	 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
       
  2771 	 *     (ich9 only, otherwise error condition)
       
  2772 	 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
       
  2773 	 */
       
  2774 	switch (hsfsts.hsf_status.berasesz) {
       
  2775 	case 0:
       
  2776 		/* Hw sector size 256 */
       
  2777 		sector_size = ICH_FLASH_SEG_SIZE_256;
       
  2778 		iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
       
  2779 		break;
       
  2780 	case 1:
       
  2781 		sector_size = ICH_FLASH_SEG_SIZE_4K;
       
  2782 		iteration = 1;
       
  2783 		break;
       
  2784 	case 2:
       
  2785 		sector_size = ICH_FLASH_SEG_SIZE_8K;
       
  2786 		iteration = 1;
       
  2787 		break;
       
  2788 	case 3:
       
  2789 		sector_size = ICH_FLASH_SEG_SIZE_64K;
       
  2790 		iteration = 1;
       
  2791 		break;
       
  2792 	default:
       
  2793 		return -E1000_ERR_NVM;
       
  2794 	}
       
  2795 
       
  2796 	/* Start with the base address, then add the sector offset. */
       
  2797 	flash_linear_addr = hw->nvm.flash_base_addr;
       
  2798 	flash_linear_addr += (bank) ? flash_bank_size : 0;
       
  2799 
       
  2800 	for (j = 0; j < iteration ; j++) {
       
  2801 		do {
       
  2802 			/* Steps */
       
  2803 			ret_val = e1000_flash_cycle_init_ich8lan(hw);
       
  2804 			if (ret_val)
       
  2805 				return ret_val;
       
  2806 
       
  2807 			/*
       
  2808 			 * Write a value 11 (block Erase) in Flash
       
  2809 			 * Cycle field in hw flash control
       
  2810 			 */
       
  2811 			hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
       
  2812 			hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
       
  2813 			ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
       
  2814 
       
  2815 			/*
       
  2816 			 * Write the last 24 bits of an index within the
       
  2817 			 * block into Flash Linear address field in Flash
       
  2818 			 * Address.
       
  2819 			 */
       
  2820 			flash_linear_addr += (j * sector_size);
       
  2821 			ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
       
  2822 
       
  2823 			ret_val = e1000_flash_cycle_ich8lan(hw,
       
  2824 					       ICH_FLASH_ERASE_COMMAND_TIMEOUT);
       
  2825 			if (ret_val == 0)
       
  2826 				break;
       
  2827 
       
  2828 			/*
       
  2829 			 * Check if FCERR is set to 1.  If 1,
       
  2830 			 * clear it and try the whole sequence
       
  2831 			 * a few more times else Done
       
  2832 			 */
       
  2833 			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
       
  2834 			if (hsfsts.hsf_status.flcerr == 1)
       
  2835 				/* repeat for some time before giving up */
       
  2836 				continue;
       
  2837 			else if (hsfsts.hsf_status.flcdone == 0)
       
  2838 				return ret_val;
       
  2839 		} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
       
  2840 	}
       
  2841 
       
  2842 	return 0;
       
  2843 }
       
  2844 
       
  2845 /**
       
  2846  *  e1000_valid_led_default_ich8lan - Set the default LED settings
       
  2847  *  @hw: pointer to the HW structure
       
  2848  *  @data: Pointer to the LED settings
       
  2849  *
       
  2850  *  Reads the LED default settings from the NVM to data.  If the NVM LED
       
  2851  *  settings is all 0's or F's, set the LED default to a valid LED default
       
  2852  *  setting.
       
  2853  **/
       
  2854 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
       
  2855 {
       
  2856 	s32 ret_val;
       
  2857 
       
  2858 	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
       
  2859 	if (ret_val) {
       
  2860 		e_dbg("NVM Read Error\n");
       
  2861 		return ret_val;
       
  2862 	}
       
  2863 
       
  2864 	if (*data == ID_LED_RESERVED_0000 ||
       
  2865 	    *data == ID_LED_RESERVED_FFFF)
       
  2866 		*data = ID_LED_DEFAULT_ICH8LAN;
       
  2867 
       
  2868 	return 0;
       
  2869 }
       
  2870 
       
  2871 /**
       
  2872  *  e1000_id_led_init_pchlan - store LED configurations
       
  2873  *  @hw: pointer to the HW structure
       
  2874  *
       
  2875  *  PCH does not control LEDs via the LEDCTL register, rather it uses
       
  2876  *  the PHY LED configuration register.
       
  2877  *
       
  2878  *  PCH also does not have an "always on" or "always off" mode which
       
  2879  *  complicates the ID feature.  Instead of using the "on" mode to indicate
       
  2880  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
       
  2881  *  use "link_up" mode.  The LEDs will still ID on request if there is no
       
  2882  *  link based on logic in e1000_led_[on|off]_pchlan().
       
  2883  **/
       
  2884 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
       
  2885 {
       
  2886 	struct e1000_mac_info *mac = &hw->mac;
       
  2887 	s32 ret_val;
       
  2888 	const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
       
  2889 	const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
       
  2890 	u16 data, i, temp, shift;
       
  2891 
       
  2892 	/* Get default ID LED modes */
       
  2893 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
       
  2894 	if (ret_val)
       
  2895 		goto out;
       
  2896 
       
  2897 	mac->ledctl_default = er32(LEDCTL);
       
  2898 	mac->ledctl_mode1 = mac->ledctl_default;
       
  2899 	mac->ledctl_mode2 = mac->ledctl_default;
       
  2900 
       
  2901 	for (i = 0; i < 4; i++) {
       
  2902 		temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
       
  2903 		shift = (i * 5);
       
  2904 		switch (temp) {
       
  2905 		case ID_LED_ON1_DEF2:
       
  2906 		case ID_LED_ON1_ON2:
       
  2907 		case ID_LED_ON1_OFF2:
       
  2908 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
       
  2909 			mac->ledctl_mode1 |= (ledctl_on << shift);
       
  2910 			break;
       
  2911 		case ID_LED_OFF1_DEF2:
       
  2912 		case ID_LED_OFF1_ON2:
       
  2913 		case ID_LED_OFF1_OFF2:
       
  2914 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
       
  2915 			mac->ledctl_mode1 |= (ledctl_off << shift);
       
  2916 			break;
       
  2917 		default:
       
  2918 			/* Do nothing */
       
  2919 			break;
       
  2920 		}
       
  2921 		switch (temp) {
       
  2922 		case ID_LED_DEF1_ON2:
       
  2923 		case ID_LED_ON1_ON2:
       
  2924 		case ID_LED_OFF1_ON2:
       
  2925 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
       
  2926 			mac->ledctl_mode2 |= (ledctl_on << shift);
       
  2927 			break;
       
  2928 		case ID_LED_DEF1_OFF2:
       
  2929 		case ID_LED_ON1_OFF2:
       
  2930 		case ID_LED_OFF1_OFF2:
       
  2931 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
       
  2932 			mac->ledctl_mode2 |= (ledctl_off << shift);
       
  2933 			break;
       
  2934 		default:
       
  2935 			/* Do nothing */
       
  2936 			break;
       
  2937 		}
       
  2938 	}
       
  2939 
       
  2940 out:
       
  2941 	return ret_val;
       
  2942 }
       
  2943 
       
  2944 /**
       
  2945  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
       
  2946  *  @hw: pointer to the HW structure
       
  2947  *
       
  2948  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
       
  2949  *  register, so the the bus width is hard coded.
       
  2950  **/
       
  2951 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
       
  2952 {
       
  2953 	struct e1000_bus_info *bus = &hw->bus;
       
  2954 	s32 ret_val;
       
  2955 
       
  2956 	ret_val = e1000e_get_bus_info_pcie(hw);
       
  2957 
       
  2958 	/*
       
  2959 	 * ICH devices are "PCI Express"-ish.  They have
       
  2960 	 * a configuration space, but do not contain
       
  2961 	 * PCI Express Capability registers, so bus width
       
  2962 	 * must be hardcoded.
       
  2963 	 */
       
  2964 	if (bus->width == e1000_bus_width_unknown)
       
  2965 		bus->width = e1000_bus_width_pcie_x1;
       
  2966 
       
  2967 	return ret_val;
       
  2968 }
       
  2969 
       
  2970 /**
       
  2971  *  e1000_reset_hw_ich8lan - Reset the hardware
       
  2972  *  @hw: pointer to the HW structure
       
  2973  *
       
  2974  *  Does a full reset of the hardware which includes a reset of the PHY and
       
  2975  *  MAC.
       
  2976  **/
       
  2977 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
       
  2978 {
       
  2979 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
       
  2980 	u16 reg;
       
  2981 	u32 ctrl, icr, kab;
       
  2982 	s32 ret_val;
       
  2983 
       
  2984 	/*
       
  2985 	 * Prevent the PCI-E bus from sticking if there is no TLP connection
       
  2986 	 * on the last TLP read/write transaction when MAC is reset.
       
  2987 	 */
       
  2988 	ret_val = e1000e_disable_pcie_master(hw);
       
  2989 	if (ret_val)
       
  2990 		e_dbg("PCI-E Master disable polling has failed.\n");
       
  2991 
       
  2992 	e_dbg("Masking off all interrupts\n");
       
  2993 	ew32(IMC, 0xffffffff);
       
  2994 
       
  2995 	/*
       
  2996 	 * Disable the Transmit and Receive units.  Then delay to allow
       
  2997 	 * any pending transactions to complete before we hit the MAC
       
  2998 	 * with the global reset.
       
  2999 	 */
       
  3000 	ew32(RCTL, 0);
       
  3001 	ew32(TCTL, E1000_TCTL_PSP);
       
  3002 	e1e_flush();
       
  3003 
       
  3004 	msleep(10);
       
  3005 
       
  3006 	/* Workaround for ICH8 bit corruption issue in FIFO memory */
       
  3007 	if (hw->mac.type == e1000_ich8lan) {
       
  3008 		/* Set Tx and Rx buffer allocation to 8k apiece. */
       
  3009 		ew32(PBA, E1000_PBA_8K);
       
  3010 		/* Set Packet Buffer Size to 16k. */
       
  3011 		ew32(PBS, E1000_PBS_16K);
       
  3012 	}
       
  3013 
       
  3014 	if (hw->mac.type == e1000_pchlan) {
       
  3015 		/* Save the NVM K1 bit setting*/
       
  3016 		ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
       
  3017 		if (ret_val)
       
  3018 			return ret_val;
       
  3019 
       
  3020 		if (reg & E1000_NVM_K1_ENABLE)
       
  3021 			dev_spec->nvm_k1_enabled = true;
       
  3022 		else
       
  3023 			dev_spec->nvm_k1_enabled = false;
       
  3024 	}
       
  3025 
       
  3026 	ctrl = er32(CTRL);
       
  3027 
       
  3028 	if (!e1000_check_reset_block(hw)) {
       
  3029 		/*
       
  3030 		 * Full-chip reset requires MAC and PHY reset at the same
       
  3031 		 * time to make sure the interface between MAC and the
       
  3032 		 * external PHY is reset.
       
  3033 		 */
       
  3034 		ctrl |= E1000_CTRL_PHY_RST;
       
  3035 
       
  3036 		/*
       
  3037 		 * Gate automatic PHY configuration by hardware on
       
  3038 		 * non-managed 82579
       
  3039 		 */
       
  3040 		if ((hw->mac.type == e1000_pch2lan) &&
       
  3041 		    !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
       
  3042 			e1000_gate_hw_phy_config_ich8lan(hw, true);
       
  3043 	}
       
  3044 	ret_val = e1000_acquire_swflag_ich8lan(hw);
       
  3045 	e_dbg("Issuing a global reset to ich8lan\n");
       
  3046 	ew32(CTRL, (ctrl | E1000_CTRL_RST));
       
  3047 	msleep(20);
       
  3048 
       
  3049 	if (!ret_val)
       
  3050 		e1000_release_swflag_ich8lan(hw);
       
  3051 
       
  3052 	if (ctrl & E1000_CTRL_PHY_RST) {
       
  3053 		ret_val = hw->phy.ops.get_cfg_done(hw);
       
  3054 		if (ret_val)
       
  3055 			goto out;
       
  3056 
       
  3057 		ret_val = e1000_post_phy_reset_ich8lan(hw);
       
  3058 		if (ret_val)
       
  3059 			goto out;
       
  3060 	}
       
  3061 
       
  3062 	/*
       
  3063 	 * For PCH, this write will make sure that any noise
       
  3064 	 * will be detected as a CRC error and be dropped rather than show up
       
  3065 	 * as a bad packet to the DMA engine.
       
  3066 	 */
       
  3067 	if (hw->mac.type == e1000_pchlan)
       
  3068 		ew32(CRC_OFFSET, 0x65656565);
       
  3069 
       
  3070 	ew32(IMC, 0xffffffff);
       
  3071 	icr = er32(ICR);
       
  3072 
       
  3073 	kab = er32(KABGTXD);
       
  3074 	kab |= E1000_KABGTXD_BGSQLBIAS;
       
  3075 	ew32(KABGTXD, kab);
       
  3076 
       
  3077 out:
       
  3078 	return ret_val;
       
  3079 }
       
  3080 
       
  3081 /**
       
  3082  *  e1000_init_hw_ich8lan - Initialize the hardware
       
  3083  *  @hw: pointer to the HW structure
       
  3084  *
       
  3085  *  Prepares the hardware for transmit and receive by doing the following:
       
  3086  *   - initialize hardware bits
       
  3087  *   - initialize LED identification
       
  3088  *   - setup receive address registers
       
  3089  *   - setup flow control
       
  3090  *   - setup transmit descriptors
       
  3091  *   - clear statistics
       
  3092  **/
       
  3093 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
       
  3094 {
       
  3095 	struct e1000_mac_info *mac = &hw->mac;
       
  3096 	u32 ctrl_ext, txdctl, snoop;
       
  3097 	s32 ret_val;
       
  3098 	u16 i;
       
  3099 
       
  3100 	e1000_initialize_hw_bits_ich8lan(hw);
       
  3101 
       
  3102 	/* Initialize identification LED */
       
  3103 	ret_val = mac->ops.id_led_init(hw);
       
  3104 	if (ret_val)
       
  3105 		e_dbg("Error initializing identification LED\n");
       
  3106 		/* This is not fatal and we should not stop init due to this */
       
  3107 
       
  3108 	/* Setup the receive address. */
       
  3109 	e1000e_init_rx_addrs(hw, mac->rar_entry_count);
       
  3110 
       
  3111 	/* Zero out the Multicast HASH table */
       
  3112 	e_dbg("Zeroing the MTA\n");
       
  3113 	for (i = 0; i < mac->mta_reg_count; i++)
       
  3114 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
       
  3115 
       
  3116 	/*
       
  3117 	 * The 82578 Rx buffer will stall if wakeup is enabled in host and
       
  3118 	 * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
       
  3119 	 * Reset the phy after disabling host wakeup to reset the Rx buffer.
       
  3120 	 */
       
  3121 	if (hw->phy.type == e1000_phy_82578) {
       
  3122 		hw->phy.ops.read_reg(hw, BM_WUC, &i);
       
  3123 		ret_val = e1000_phy_hw_reset_ich8lan(hw);
       
  3124 		if (ret_val)
       
  3125 			return ret_val;
       
  3126 	}
       
  3127 
       
  3128 	/* Setup link and flow control */
       
  3129 	ret_val = e1000_setup_link_ich8lan(hw);
       
  3130 
       
  3131 	/* Set the transmit descriptor write-back policy for both queues */
       
  3132 	txdctl = er32(TXDCTL(0));
       
  3133 	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
       
  3134 		 E1000_TXDCTL_FULL_TX_DESC_WB;
       
  3135 	txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
       
  3136 		 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
       
  3137 	ew32(TXDCTL(0), txdctl);
       
  3138 	txdctl = er32(TXDCTL(1));
       
  3139 	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
       
  3140 		 E1000_TXDCTL_FULL_TX_DESC_WB;
       
  3141 	txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
       
  3142 		 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
       
  3143 	ew32(TXDCTL(1), txdctl);
       
  3144 
       
  3145 	/*
       
  3146 	 * ICH8 has opposite polarity of no_snoop bits.
       
  3147 	 * By default, we should use snoop behavior.
       
  3148 	 */
       
  3149 	if (mac->type == e1000_ich8lan)
       
  3150 		snoop = PCIE_ICH8_SNOOP_ALL;
       
  3151 	else
       
  3152 		snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
       
  3153 	e1000e_set_pcie_no_snoop(hw, snoop);
       
  3154 
       
  3155 	ctrl_ext = er32(CTRL_EXT);
       
  3156 	ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
       
  3157 	ew32(CTRL_EXT, ctrl_ext);
       
  3158 
       
  3159 	/*
       
  3160 	 * Clear all of the statistics registers (clear on read).  It is
       
  3161 	 * important that we do this after we have tried to establish link
       
  3162 	 * because the symbol error count will increment wildly if there
       
  3163 	 * is no link.
       
  3164 	 */
       
  3165 	e1000_clear_hw_cntrs_ich8lan(hw);
       
  3166 
       
  3167 	return 0;
       
  3168 }
       
  3169 /**
       
  3170  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
       
  3171  *  @hw: pointer to the HW structure
       
  3172  *
       
  3173  *  Sets/Clears required hardware bits necessary for correctly setting up the
       
  3174  *  hardware for transmit and receive.
       
  3175  **/
       
  3176 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
       
  3177 {
       
  3178 	u32 reg;
       
  3179 
       
  3180 	/* Extended Device Control */
       
  3181 	reg = er32(CTRL_EXT);
       
  3182 	reg |= (1 << 22);
       
  3183 	/* Enable PHY low-power state when MAC is at D3 w/o WoL */
       
  3184 	if (hw->mac.type >= e1000_pchlan)
       
  3185 		reg |= E1000_CTRL_EXT_PHYPDEN;
       
  3186 	ew32(CTRL_EXT, reg);
       
  3187 
       
  3188 	/* Transmit Descriptor Control 0 */
       
  3189 	reg = er32(TXDCTL(0));
       
  3190 	reg |= (1 << 22);
       
  3191 	ew32(TXDCTL(0), reg);
       
  3192 
       
  3193 	/* Transmit Descriptor Control 1 */
       
  3194 	reg = er32(TXDCTL(1));
       
  3195 	reg |= (1 << 22);
       
  3196 	ew32(TXDCTL(1), reg);
       
  3197 
       
  3198 	/* Transmit Arbitration Control 0 */
       
  3199 	reg = er32(TARC(0));
       
  3200 	if (hw->mac.type == e1000_ich8lan)
       
  3201 		reg |= (1 << 28) | (1 << 29);
       
  3202 	reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
       
  3203 	ew32(TARC(0), reg);
       
  3204 
       
  3205 	/* Transmit Arbitration Control 1 */
       
  3206 	reg = er32(TARC(1));
       
  3207 	if (er32(TCTL) & E1000_TCTL_MULR)
       
  3208 		reg &= ~(1 << 28);
       
  3209 	else
       
  3210 		reg |= (1 << 28);
       
  3211 	reg |= (1 << 24) | (1 << 26) | (1 << 30);
       
  3212 	ew32(TARC(1), reg);
       
  3213 
       
  3214 	/* Device Status */
       
  3215 	if (hw->mac.type == e1000_ich8lan) {
       
  3216 		reg = er32(STATUS);
       
  3217 		reg &= ~(1 << 31);
       
  3218 		ew32(STATUS, reg);
       
  3219 	}
       
  3220 
       
  3221 	/*
       
  3222 	 * work-around descriptor data corruption issue during nfs v2 udp
       
  3223 	 * traffic, just disable the nfs filtering capability
       
  3224 	 */
       
  3225 	reg = er32(RFCTL);
       
  3226 	reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
       
  3227 	ew32(RFCTL, reg);
       
  3228 }
       
  3229 
       
  3230 /**
       
  3231  *  e1000_setup_link_ich8lan - Setup flow control and link settings
       
  3232  *  @hw: pointer to the HW structure
       
  3233  *
       
  3234  *  Determines which flow control settings to use, then configures flow
       
  3235  *  control.  Calls the appropriate media-specific link configuration
       
  3236  *  function.  Assuming the adapter has a valid link partner, a valid link
       
  3237  *  should be established.  Assumes the hardware has previously been reset
       
  3238  *  and the transmitter and receiver are not enabled.
       
  3239  **/
       
  3240 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
       
  3241 {
       
  3242 	s32 ret_val;
       
  3243 
       
  3244 	if (e1000_check_reset_block(hw))
       
  3245 		return 0;
       
  3246 
       
  3247 	/*
       
  3248 	 * ICH parts do not have a word in the NVM to determine
       
  3249 	 * the default flow control setting, so we explicitly
       
  3250 	 * set it to full.
       
  3251 	 */
       
  3252 	if (hw->fc.requested_mode == e1000_fc_default) {
       
  3253 		/* Workaround h/w hang when Tx flow control enabled */
       
  3254 		if (hw->mac.type == e1000_pchlan)
       
  3255 			hw->fc.requested_mode = e1000_fc_rx_pause;
       
  3256 		else
       
  3257 			hw->fc.requested_mode = e1000_fc_full;
       
  3258 	}
       
  3259 
       
  3260 	/*
       
  3261 	 * Save off the requested flow control mode for use later.  Depending
       
  3262 	 * on the link partner's capabilities, we may or may not use this mode.
       
  3263 	 */
       
  3264 	hw->fc.current_mode = hw->fc.requested_mode;
       
  3265 
       
  3266 	e_dbg("After fix-ups FlowControl is now = %x\n",
       
  3267 		hw->fc.current_mode);
       
  3268 
       
  3269 	/* Continue to configure the copper link. */
       
  3270 	ret_val = e1000_setup_copper_link_ich8lan(hw);
       
  3271 	if (ret_val)
       
  3272 		return ret_val;
       
  3273 
       
  3274 	ew32(FCTTV, hw->fc.pause_time);
       
  3275 	if ((hw->phy.type == e1000_phy_82578) ||
       
  3276 	    (hw->phy.type == e1000_phy_82579) ||
       
  3277 	    (hw->phy.type == e1000_phy_82577)) {
       
  3278 		ew32(FCRTV_PCH, hw->fc.refresh_time);
       
  3279 
       
  3280 		ret_val = hw->phy.ops.write_reg(hw,
       
  3281 		                             PHY_REG(BM_PORT_CTRL_PAGE, 27),
       
  3282 		                             hw->fc.pause_time);
       
  3283 		if (ret_val)
       
  3284 			return ret_val;
       
  3285 	}
       
  3286 
       
  3287 	return e1000e_set_fc_watermarks(hw);
       
  3288 }
       
  3289 
       
  3290 /**
       
  3291  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
       
  3292  *  @hw: pointer to the HW structure
       
  3293  *
       
  3294  *  Configures the kumeran interface to the PHY to wait the appropriate time
       
  3295  *  when polling the PHY, then call the generic setup_copper_link to finish
       
  3296  *  configuring the copper link.
       
  3297  **/
       
  3298 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
       
  3299 {
       
  3300 	u32 ctrl;
       
  3301 	s32 ret_val;
       
  3302 	u16 reg_data;
       
  3303 
       
  3304 	ctrl = er32(CTRL);
       
  3305 	ctrl |= E1000_CTRL_SLU;
       
  3306 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
       
  3307 	ew32(CTRL, ctrl);
       
  3308 
       
  3309 	/*
       
  3310 	 * Set the mac to wait the maximum time between each iteration
       
  3311 	 * and increase the max iterations when polling the phy;
       
  3312 	 * this fixes erroneous timeouts at 10Mbps.
       
  3313 	 */
       
  3314 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
       
  3315 	if (ret_val)
       
  3316 		return ret_val;
       
  3317 	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
       
  3318 	                               &reg_data);
       
  3319 	if (ret_val)
       
  3320 		return ret_val;
       
  3321 	reg_data |= 0x3F;
       
  3322 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
       
  3323 	                                reg_data);
       
  3324 	if (ret_val)
       
  3325 		return ret_val;
       
  3326 
       
  3327 	switch (hw->phy.type) {
       
  3328 	case e1000_phy_igp_3:
       
  3329 		ret_val = e1000e_copper_link_setup_igp(hw);
       
  3330 		if (ret_val)
       
  3331 			return ret_val;
       
  3332 		break;
       
  3333 	case e1000_phy_bm:
       
  3334 	case e1000_phy_82578:
       
  3335 		ret_val = e1000e_copper_link_setup_m88(hw);
       
  3336 		if (ret_val)
       
  3337 			return ret_val;
       
  3338 		break;
       
  3339 	case e1000_phy_82577:
       
  3340 	case e1000_phy_82579:
       
  3341 		ret_val = e1000_copper_link_setup_82577(hw);
       
  3342 		if (ret_val)
       
  3343 			return ret_val;
       
  3344 		break;
       
  3345 	case e1000_phy_ife:
       
  3346 		ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
       
  3347 		                               &reg_data);
       
  3348 		if (ret_val)
       
  3349 			return ret_val;
       
  3350 
       
  3351 		reg_data &= ~IFE_PMC_AUTO_MDIX;
       
  3352 
       
  3353 		switch (hw->phy.mdix) {
       
  3354 		case 1:
       
  3355 			reg_data &= ~IFE_PMC_FORCE_MDIX;
       
  3356 			break;
       
  3357 		case 2:
       
  3358 			reg_data |= IFE_PMC_FORCE_MDIX;
       
  3359 			break;
       
  3360 		case 0:
       
  3361 		default:
       
  3362 			reg_data |= IFE_PMC_AUTO_MDIX;
       
  3363 			break;
       
  3364 		}
       
  3365 		ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
       
  3366 		                                reg_data);
       
  3367 		if (ret_val)
       
  3368 			return ret_val;
       
  3369 		break;
       
  3370 	default:
       
  3371 		break;
       
  3372 	}
       
  3373 	return e1000e_setup_copper_link(hw);
       
  3374 }
       
  3375 
       
  3376 /**
       
  3377  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
       
  3378  *  @hw: pointer to the HW structure
       
  3379  *  @speed: pointer to store current link speed
       
  3380  *  @duplex: pointer to store the current link duplex
       
  3381  *
       
  3382  *  Calls the generic get_speed_and_duplex to retrieve the current link
       
  3383  *  information and then calls the Kumeran lock loss workaround for links at
       
  3384  *  gigabit speeds.
       
  3385  **/
       
  3386 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
       
  3387 					  u16 *duplex)
       
  3388 {
       
  3389 	s32 ret_val;
       
  3390 
       
  3391 	ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
       
  3392 	if (ret_val)
       
  3393 		return ret_val;
       
  3394 
       
  3395 	if ((hw->mac.type == e1000_ich8lan) &&
       
  3396 	    (hw->phy.type == e1000_phy_igp_3) &&
       
  3397 	    (*speed == SPEED_1000)) {
       
  3398 		ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
       
  3399 	}
       
  3400 
       
  3401 	return ret_val;
       
  3402 }
       
  3403 
       
  3404 /**
       
  3405  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
       
  3406  *  @hw: pointer to the HW structure
       
  3407  *
       
  3408  *  Work-around for 82566 Kumeran PCS lock loss:
       
  3409  *  On link status change (i.e. PCI reset, speed change) and link is up and
       
  3410  *  speed is gigabit-
       
  3411  *    0) if workaround is optionally disabled do nothing
       
  3412  *    1) wait 1ms for Kumeran link to come up
       
  3413  *    2) check Kumeran Diagnostic register PCS lock loss bit
       
  3414  *    3) if not set the link is locked (all is good), otherwise...
       
  3415  *    4) reset the PHY
       
  3416  *    5) repeat up to 10 times
       
  3417  *  Note: this is only called for IGP3 copper when speed is 1gb.
       
  3418  **/
       
  3419 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
       
  3420 {
       
  3421 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
       
  3422 	u32 phy_ctrl;
       
  3423 	s32 ret_val;
       
  3424 	u16 i, data;
       
  3425 	bool link;
       
  3426 
       
  3427 	if (!dev_spec->kmrn_lock_loss_workaround_enabled)
       
  3428 		return 0;
       
  3429 
       
  3430 	/*
       
  3431 	 * Make sure link is up before proceeding.  If not just return.
       
  3432 	 * Attempting this while link is negotiating fouled up link
       
  3433 	 * stability
       
  3434 	 */
       
  3435 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
       
  3436 	if (!link)
       
  3437 		return 0;
       
  3438 
       
  3439 	for (i = 0; i < 10; i++) {
       
  3440 		/* read once to clear */
       
  3441 		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
       
  3442 		if (ret_val)
       
  3443 			return ret_val;
       
  3444 		/* and again to get new status */
       
  3445 		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
       
  3446 		if (ret_val)
       
  3447 			return ret_val;
       
  3448 
       
  3449 		/* check for PCS lock */
       
  3450 		if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
       
  3451 			return 0;
       
  3452 
       
  3453 		/* Issue PHY reset */
       
  3454 		e1000_phy_hw_reset(hw);
       
  3455 		mdelay(5);
       
  3456 	}
       
  3457 	/* Disable GigE link negotiation */
       
  3458 	phy_ctrl = er32(PHY_CTRL);
       
  3459 	phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
       
  3460 		     E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
       
  3461 	ew32(PHY_CTRL, phy_ctrl);
       
  3462 
       
  3463 	/*
       
  3464 	 * Call gig speed drop workaround on Gig disable before accessing
       
  3465 	 * any PHY registers
       
  3466 	 */
       
  3467 	e1000e_gig_downshift_workaround_ich8lan(hw);
       
  3468 
       
  3469 	/* unable to acquire PCS lock */
       
  3470 	return -E1000_ERR_PHY;
       
  3471 }
       
  3472 
       
  3473 /**
       
  3474  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
       
  3475  *  @hw: pointer to the HW structure
       
  3476  *  @state: boolean value used to set the current Kumeran workaround state
       
  3477  *
       
  3478  *  If ICH8, set the current Kumeran workaround state (enabled - true
       
  3479  *  /disabled - false).
       
  3480  **/
       
  3481 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
       
  3482 						 bool state)
       
  3483 {
       
  3484 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
       
  3485 
       
  3486 	if (hw->mac.type != e1000_ich8lan) {
       
  3487 		e_dbg("Workaround applies to ICH8 only.\n");
       
  3488 		return;
       
  3489 	}
       
  3490 
       
  3491 	dev_spec->kmrn_lock_loss_workaround_enabled = state;
       
  3492 }
       
  3493 
       
  3494 /**
       
  3495  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
       
  3496  *  @hw: pointer to the HW structure
       
  3497  *
       
  3498  *  Workaround for 82566 power-down on D3 entry:
       
  3499  *    1) disable gigabit link
       
  3500  *    2) write VR power-down enable
       
  3501  *    3) read it back
       
  3502  *  Continue if successful, else issue LCD reset and repeat
       
  3503  **/
       
  3504 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
       
  3505 {
       
  3506 	u32 reg;
       
  3507 	u16 data;
       
  3508 	u8  retry = 0;
       
  3509 
       
  3510 	if (hw->phy.type != e1000_phy_igp_3)
       
  3511 		return;
       
  3512 
       
  3513 	/* Try the workaround twice (if needed) */
       
  3514 	do {
       
  3515 		/* Disable link */
       
  3516 		reg = er32(PHY_CTRL);
       
  3517 		reg |= (E1000_PHY_CTRL_GBE_DISABLE |
       
  3518 			E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
       
  3519 		ew32(PHY_CTRL, reg);
       
  3520 
       
  3521 		/*
       
  3522 		 * Call gig speed drop workaround on Gig disable before
       
  3523 		 * accessing any PHY registers
       
  3524 		 */
       
  3525 		if (hw->mac.type == e1000_ich8lan)
       
  3526 			e1000e_gig_downshift_workaround_ich8lan(hw);
       
  3527 
       
  3528 		/* Write VR power-down enable */
       
  3529 		e1e_rphy(hw, IGP3_VR_CTRL, &data);
       
  3530 		data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
       
  3531 		e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
       
  3532 
       
  3533 		/* Read it back and test */
       
  3534 		e1e_rphy(hw, IGP3_VR_CTRL, &data);
       
  3535 		data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
       
  3536 		if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
       
  3537 			break;
       
  3538 
       
  3539 		/* Issue PHY reset and repeat at most one more time */
       
  3540 		reg = er32(CTRL);
       
  3541 		ew32(CTRL, reg | E1000_CTRL_PHY_RST);
       
  3542 		retry++;
       
  3543 	} while (retry);
       
  3544 }
       
  3545 
       
  3546 /**
       
  3547  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
       
  3548  *  @hw: pointer to the HW structure
       
  3549  *
       
  3550  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
       
  3551  *  LPLU, Gig disable, MDIC PHY reset):
       
  3552  *    1) Set Kumeran Near-end loopback
       
  3553  *    2) Clear Kumeran Near-end loopback
       
  3554  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
       
  3555  **/
       
  3556 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
       
  3557 {
       
  3558 	s32 ret_val;
       
  3559 	u16 reg_data;
       
  3560 
       
  3561 	if ((hw->mac.type != e1000_ich8lan) ||
       
  3562 	    (hw->phy.type != e1000_phy_igp_3))
       
  3563 		return;
       
  3564 
       
  3565 	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
       
  3566 				      &reg_data);
       
  3567 	if (ret_val)
       
  3568 		return;
       
  3569 	reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
       
  3570 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
       
  3571 				       reg_data);
       
  3572 	if (ret_val)
       
  3573 		return;
       
  3574 	reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
       
  3575 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
       
  3576 				       reg_data);
       
  3577 }
       
  3578 
       
  3579 /**
       
  3580  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
       
  3581  *  @hw: pointer to the HW structure
       
  3582  *
       
  3583  *  During S0 to Sx transition, it is possible the link remains at gig
       
  3584  *  instead of negotiating to a lower speed.  Before going to Sx, set
       
  3585  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
       
  3586  *  to a lower speed.
       
  3587  *
       
  3588  *  Should only be called for applicable parts.
       
  3589  **/
       
  3590 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
       
  3591 {
       
  3592 	u32 phy_ctrl;
       
  3593 	s32 ret_val;
       
  3594 
       
  3595 	phy_ctrl = er32(PHY_CTRL);
       
  3596 	phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
       
  3597 	ew32(PHY_CTRL, phy_ctrl);
       
  3598 
       
  3599 	if (hw->mac.type >= e1000_pchlan) {
       
  3600 		e1000_oem_bits_config_ich8lan(hw, true);
       
  3601 		ret_val = hw->phy.ops.acquire(hw);
       
  3602 		if (ret_val)
       
  3603 			return;
       
  3604 		e1000_write_smbus_addr(hw);
       
  3605 		hw->phy.ops.release(hw);
       
  3606 	}
       
  3607 }
       
  3608 
       
  3609 /**
       
  3610  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
       
  3611  *  @hw: pointer to the HW structure
       
  3612  *
       
  3613  *  Return the LED back to the default configuration.
       
  3614  **/
       
  3615 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
       
  3616 {
       
  3617 	if (hw->phy.type == e1000_phy_ife)
       
  3618 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
       
  3619 
       
  3620 	ew32(LEDCTL, hw->mac.ledctl_default);
       
  3621 	return 0;
       
  3622 }
       
  3623 
       
  3624 /**
       
  3625  *  e1000_led_on_ich8lan - Turn LEDs on
       
  3626  *  @hw: pointer to the HW structure
       
  3627  *
       
  3628  *  Turn on the LEDs.
       
  3629  **/
       
  3630 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
       
  3631 {
       
  3632 	if (hw->phy.type == e1000_phy_ife)
       
  3633 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
       
  3634 				(IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
       
  3635 
       
  3636 	ew32(LEDCTL, hw->mac.ledctl_mode2);
       
  3637 	return 0;
       
  3638 }
       
  3639 
       
  3640 /**
       
  3641  *  e1000_led_off_ich8lan - Turn LEDs off
       
  3642  *  @hw: pointer to the HW structure
       
  3643  *
       
  3644  *  Turn off the LEDs.
       
  3645  **/
       
  3646 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
       
  3647 {
       
  3648 	if (hw->phy.type == e1000_phy_ife)
       
  3649 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
       
  3650 			       (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
       
  3651 
       
  3652 	ew32(LEDCTL, hw->mac.ledctl_mode1);
       
  3653 	return 0;
       
  3654 }
       
  3655 
       
  3656 /**
       
  3657  *  e1000_setup_led_pchlan - Configures SW controllable LED
       
  3658  *  @hw: pointer to the HW structure
       
  3659  *
       
  3660  *  This prepares the SW controllable LED for use.
       
  3661  **/
       
  3662 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
       
  3663 {
       
  3664 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
       
  3665 					(u16)hw->mac.ledctl_mode1);
       
  3666 }
       
  3667 
       
  3668 /**
       
  3669  *  e1000_cleanup_led_pchlan - Restore the default LED operation
       
  3670  *  @hw: pointer to the HW structure
       
  3671  *
       
  3672  *  Return the LED back to the default configuration.
       
  3673  **/
       
  3674 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
       
  3675 {
       
  3676 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
       
  3677 					(u16)hw->mac.ledctl_default);
       
  3678 }
       
  3679 
       
  3680 /**
       
  3681  *  e1000_led_on_pchlan - Turn LEDs on
       
  3682  *  @hw: pointer to the HW structure
       
  3683  *
       
  3684  *  Turn on the LEDs.
       
  3685  **/
       
  3686 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
       
  3687 {
       
  3688 	u16 data = (u16)hw->mac.ledctl_mode2;
       
  3689 	u32 i, led;
       
  3690 
       
  3691 	/*
       
  3692 	 * If no link, then turn LED on by setting the invert bit
       
  3693 	 * for each LED that's mode is "link_up" in ledctl_mode2.
       
  3694 	 */
       
  3695 	if (!(er32(STATUS) & E1000_STATUS_LU)) {
       
  3696 		for (i = 0; i < 3; i++) {
       
  3697 			led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
       
  3698 			if ((led & E1000_PHY_LED0_MODE_MASK) !=
       
  3699 			    E1000_LEDCTL_MODE_LINK_UP)
       
  3700 				continue;
       
  3701 			if (led & E1000_PHY_LED0_IVRT)
       
  3702 				data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
       
  3703 			else
       
  3704 				data |= (E1000_PHY_LED0_IVRT << (i * 5));
       
  3705 		}
       
  3706 	}
       
  3707 
       
  3708 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
       
  3709 }
       
  3710 
       
  3711 /**
       
  3712  *  e1000_led_off_pchlan - Turn LEDs off
       
  3713  *  @hw: pointer to the HW structure
       
  3714  *
       
  3715  *  Turn off the LEDs.
       
  3716  **/
       
  3717 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
       
  3718 {
       
  3719 	u16 data = (u16)hw->mac.ledctl_mode1;
       
  3720 	u32 i, led;
       
  3721 
       
  3722 	/*
       
  3723 	 * If no link, then turn LED off by clearing the invert bit
       
  3724 	 * for each LED that's mode is "link_up" in ledctl_mode1.
       
  3725 	 */
       
  3726 	if (!(er32(STATUS) & E1000_STATUS_LU)) {
       
  3727 		for (i = 0; i < 3; i++) {
       
  3728 			led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
       
  3729 			if ((led & E1000_PHY_LED0_MODE_MASK) !=
       
  3730 			    E1000_LEDCTL_MODE_LINK_UP)
       
  3731 				continue;
       
  3732 			if (led & E1000_PHY_LED0_IVRT)
       
  3733 				data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
       
  3734 			else
       
  3735 				data |= (E1000_PHY_LED0_IVRT << (i * 5));
       
  3736 		}
       
  3737 	}
       
  3738 
       
  3739 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
       
  3740 }
       
  3741 
       
  3742 /**
       
  3743  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
       
  3744  *  @hw: pointer to the HW structure
       
  3745  *
       
  3746  *  Read appropriate register for the config done bit for completion status
       
  3747  *  and configure the PHY through s/w for EEPROM-less parts.
       
  3748  *
       
  3749  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
       
  3750  *  config done bit, so only an error is logged and continues.  If we were
       
  3751  *  to return with error, EEPROM-less silicon would not be able to be reset
       
  3752  *  or change link.
       
  3753  **/
       
  3754 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
       
  3755 {
       
  3756 	s32 ret_val = 0;
       
  3757 	u32 bank = 0;
       
  3758 	u32 status;
       
  3759 
       
  3760 	e1000e_get_cfg_done(hw);
       
  3761 
       
  3762 	/* Wait for indication from h/w that it has completed basic config */
       
  3763 	if (hw->mac.type >= e1000_ich10lan) {
       
  3764 		e1000_lan_init_done_ich8lan(hw);
       
  3765 	} else {
       
  3766 		ret_val = e1000e_get_auto_rd_done(hw);
       
  3767 		if (ret_val) {
       
  3768 			/*
       
  3769 			 * When auto config read does not complete, do not
       
  3770 			 * return with an error. This can happen in situations
       
  3771 			 * where there is no eeprom and prevents getting link.
       
  3772 			 */
       
  3773 			e_dbg("Auto Read Done did not complete\n");
       
  3774 			ret_val = 0;
       
  3775 		}
       
  3776 	}
       
  3777 
       
  3778 	/* Clear PHY Reset Asserted bit */
       
  3779 	status = er32(STATUS);
       
  3780 	if (status & E1000_STATUS_PHYRA)
       
  3781 		ew32(STATUS, status & ~E1000_STATUS_PHYRA);
       
  3782 	else
       
  3783 		e_dbg("PHY Reset Asserted not set - needs delay\n");
       
  3784 
       
  3785 	/* If EEPROM is not marked present, init the IGP 3 PHY manually */
       
  3786 	if (hw->mac.type <= e1000_ich9lan) {
       
  3787 		if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
       
  3788 		    (hw->phy.type == e1000_phy_igp_3)) {
       
  3789 			e1000e_phy_init_script_igp3(hw);
       
  3790 		}
       
  3791 	} else {
       
  3792 		if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
       
  3793 			/* Maybe we should do a basic PHY config */
       
  3794 			e_dbg("EEPROM not present\n");
       
  3795 			ret_val = -E1000_ERR_CONFIG;
       
  3796 		}
       
  3797 	}
       
  3798 
       
  3799 	return ret_val;
       
  3800 }
       
  3801 
       
  3802 /**
       
  3803  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
       
  3804  * @hw: pointer to the HW structure
       
  3805  *
       
  3806  * In the case of a PHY power down to save power, or to turn off link during a
       
  3807  * driver unload, or wake on lan is not enabled, remove the link.
       
  3808  **/
       
  3809 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
       
  3810 {
       
  3811 	/* If the management interface is not enabled, then power down */
       
  3812 	if (!(hw->mac.ops.check_mng_mode(hw) ||
       
  3813 	      hw->phy.ops.check_reset_block(hw)))
       
  3814 		e1000_power_down_phy_copper(hw);
       
  3815 }
       
  3816 
       
  3817 /**
       
  3818  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
       
  3819  *  @hw: pointer to the HW structure
       
  3820  *
       
  3821  *  Clears hardware counters specific to the silicon family and calls
       
  3822  *  clear_hw_cntrs_generic to clear all general purpose counters.
       
  3823  **/
       
  3824 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
       
  3825 {
       
  3826 	u16 phy_data;
       
  3827 
       
  3828 	e1000e_clear_hw_cntrs_base(hw);
       
  3829 
       
  3830 	er32(ALGNERRC);
       
  3831 	er32(RXERRC);
       
  3832 	er32(TNCRS);
       
  3833 	er32(CEXTERR);
       
  3834 	er32(TSCTC);
       
  3835 	er32(TSCTFC);
       
  3836 
       
  3837 	er32(MGTPRC);
       
  3838 	er32(MGTPDC);
       
  3839 	er32(MGTPTC);
       
  3840 
       
  3841 	er32(IAC);
       
  3842 	er32(ICRXOC);
       
  3843 
       
  3844 	/* Clear PHY statistics registers */
       
  3845 	if ((hw->phy.type == e1000_phy_82578) ||
       
  3846 	    (hw->phy.type == e1000_phy_82579) ||
       
  3847 	    (hw->phy.type == e1000_phy_82577)) {
       
  3848 		hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
       
  3849 		hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
       
  3850 		hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
       
  3851 		hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
       
  3852 		hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
       
  3853 		hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
       
  3854 		hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
       
  3855 		hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
       
  3856 		hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
       
  3857 		hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
       
  3858 		hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
       
  3859 		hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
       
  3860 		hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
       
  3861 		hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
       
  3862 	}
       
  3863 }
       
  3864 
       
  3865 static struct e1000_mac_operations ich8_mac_ops = {
       
  3866 	.id_led_init		= e1000e_id_led_init,
       
  3867 	/* check_mng_mode dependent on mac type */
       
  3868 	.check_for_link		= e1000_check_for_copper_link_ich8lan,
       
  3869 	/* cleanup_led dependent on mac type */
       
  3870 	.clear_hw_cntrs		= e1000_clear_hw_cntrs_ich8lan,
       
  3871 	.get_bus_info		= e1000_get_bus_info_ich8lan,
       
  3872 	.set_lan_id		= e1000_set_lan_id_single_port,
       
  3873 	.get_link_up_info	= e1000_get_link_up_info_ich8lan,
       
  3874 	/* led_on dependent on mac type */
       
  3875 	/* led_off dependent on mac type */
       
  3876 	.update_mc_addr_list	= e1000e_update_mc_addr_list_generic,
       
  3877 	.reset_hw		= e1000_reset_hw_ich8lan,
       
  3878 	.init_hw		= e1000_init_hw_ich8lan,
       
  3879 	.setup_link		= e1000_setup_link_ich8lan,
       
  3880 	.setup_physical_interface= e1000_setup_copper_link_ich8lan,
       
  3881 	/* id_led_init dependent on mac type */
       
  3882 };
       
  3883 
       
  3884 static struct e1000_phy_operations ich8_phy_ops = {
       
  3885 	.acquire		= e1000_acquire_swflag_ich8lan,
       
  3886 	.check_reset_block	= e1000_check_reset_block_ich8lan,
       
  3887 	.commit			= NULL,
       
  3888 	.get_cfg_done		= e1000_get_cfg_done_ich8lan,
       
  3889 	.get_cable_length	= e1000e_get_cable_length_igp_2,
       
  3890 	.read_reg		= e1000e_read_phy_reg_igp,
       
  3891 	.release		= e1000_release_swflag_ich8lan,
       
  3892 	.reset			= e1000_phy_hw_reset_ich8lan,
       
  3893 	.set_d0_lplu_state	= e1000_set_d0_lplu_state_ich8lan,
       
  3894 	.set_d3_lplu_state	= e1000_set_d3_lplu_state_ich8lan,
       
  3895 	.write_reg		= e1000e_write_phy_reg_igp,
       
  3896 };
       
  3897 
       
  3898 static struct e1000_nvm_operations ich8_nvm_ops = {
       
  3899 	.acquire		= e1000_acquire_nvm_ich8lan,
       
  3900 	.read		 	= e1000_read_nvm_ich8lan,
       
  3901 	.release		= e1000_release_nvm_ich8lan,
       
  3902 	.update			= e1000_update_nvm_checksum_ich8lan,
       
  3903 	.valid_led_default	= e1000_valid_led_default_ich8lan,
       
  3904 	.validate		= e1000_validate_nvm_checksum_ich8lan,
       
  3905 	.write			= e1000_write_nvm_ich8lan,
       
  3906 };
       
  3907 
       
  3908 struct e1000_info e1000_ich8_info = {
       
  3909 	.mac			= e1000_ich8lan,
       
  3910 	.flags			= FLAG_HAS_WOL
       
  3911 				  | FLAG_IS_ICH
       
  3912 				  | FLAG_RX_CSUM_ENABLED
       
  3913 				  | FLAG_HAS_CTRLEXT_ON_LOAD
       
  3914 				  | FLAG_HAS_AMT
       
  3915 				  | FLAG_HAS_FLASH
       
  3916 				  | FLAG_APME_IN_WUC,
       
  3917 	.pba			= 8,
       
  3918 	.max_hw_frame_size	= ETH_FRAME_LEN + ETH_FCS_LEN,
       
  3919 	.get_variants		= e1000_get_variants_ich8lan,
       
  3920 	.mac_ops		= &ich8_mac_ops,
       
  3921 	.phy_ops		= &ich8_phy_ops,
       
  3922 	.nvm_ops		= &ich8_nvm_ops,
       
  3923 };
       
  3924 
       
  3925 struct e1000_info e1000_ich9_info = {
       
  3926 	.mac			= e1000_ich9lan,
       
  3927 	.flags			= FLAG_HAS_JUMBO_FRAMES
       
  3928 				  | FLAG_IS_ICH
       
  3929 				  | FLAG_HAS_WOL
       
  3930 				  | FLAG_RX_CSUM_ENABLED
       
  3931 				  | FLAG_HAS_CTRLEXT_ON_LOAD
       
  3932 				  | FLAG_HAS_AMT
       
  3933 				  | FLAG_HAS_ERT
       
  3934 				  | FLAG_HAS_FLASH
       
  3935 				  | FLAG_APME_IN_WUC,
       
  3936 	.pba			= 10,
       
  3937 	.max_hw_frame_size	= DEFAULT_JUMBO,
       
  3938 	.get_variants		= e1000_get_variants_ich8lan,
       
  3939 	.mac_ops		= &ich8_mac_ops,
       
  3940 	.phy_ops		= &ich8_phy_ops,
       
  3941 	.nvm_ops		= &ich8_nvm_ops,
       
  3942 };
       
  3943 
       
  3944 struct e1000_info e1000_ich10_info = {
       
  3945 	.mac			= e1000_ich10lan,
       
  3946 	.flags			= FLAG_HAS_JUMBO_FRAMES
       
  3947 				  | FLAG_IS_ICH
       
  3948 				  | FLAG_HAS_WOL
       
  3949 				  | FLAG_RX_CSUM_ENABLED
       
  3950 				  | FLAG_HAS_CTRLEXT_ON_LOAD
       
  3951 				  | FLAG_HAS_AMT
       
  3952 				  | FLAG_HAS_ERT
       
  3953 				  | FLAG_HAS_FLASH
       
  3954 				  | FLAG_APME_IN_WUC,
       
  3955 	.pba			= 10,
       
  3956 	.max_hw_frame_size	= DEFAULT_JUMBO,
       
  3957 	.get_variants		= e1000_get_variants_ich8lan,
       
  3958 	.mac_ops		= &ich8_mac_ops,
       
  3959 	.phy_ops		= &ich8_phy_ops,
       
  3960 	.nvm_ops		= &ich8_nvm_ops,
       
  3961 };
       
  3962 
       
  3963 struct e1000_info e1000_pch_info = {
       
  3964 	.mac			= e1000_pchlan,
       
  3965 	.flags			= FLAG_IS_ICH
       
  3966 				  | FLAG_HAS_WOL
       
  3967 				  | FLAG_RX_CSUM_ENABLED
       
  3968 				  | FLAG_HAS_CTRLEXT_ON_LOAD
       
  3969 				  | FLAG_HAS_AMT
       
  3970 				  | FLAG_HAS_FLASH
       
  3971 				  | FLAG_HAS_JUMBO_FRAMES
       
  3972 				  | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
       
  3973 				  | FLAG_APME_IN_WUC,
       
  3974 	.flags2			= FLAG2_HAS_PHY_STATS,
       
  3975 	.pba			= 26,
       
  3976 	.max_hw_frame_size	= 4096,
       
  3977 	.get_variants		= e1000_get_variants_ich8lan,
       
  3978 	.mac_ops		= &ich8_mac_ops,
       
  3979 	.phy_ops		= &ich8_phy_ops,
       
  3980 	.nvm_ops		= &ich8_nvm_ops,
       
  3981 };
       
  3982 
       
  3983 struct e1000_info e1000_pch2_info = {
       
  3984 	.mac			= e1000_pch2lan,
       
  3985 	.flags			= FLAG_IS_ICH
       
  3986 				  | FLAG_HAS_WOL
       
  3987 				  | FLAG_RX_CSUM_ENABLED
       
  3988 				  | FLAG_HAS_CTRLEXT_ON_LOAD
       
  3989 				  | FLAG_HAS_AMT
       
  3990 				  | FLAG_HAS_FLASH
       
  3991 				  | FLAG_HAS_JUMBO_FRAMES
       
  3992 				  | FLAG_APME_IN_WUC,
       
  3993 	.flags2			= FLAG2_HAS_PHY_STATS
       
  3994 				  | FLAG2_HAS_EEE,
       
  3995 	.pba			= 26,
       
  3996 	.max_hw_frame_size	= DEFAULT_JUMBO,
       
  3997 	.get_variants		= e1000_get_variants_ich8lan,
       
  3998 	.mac_ops		= &ich8_mac_ops,
       
  3999 	.phy_ops		= &ich8_phy_ops,
       
  4000 	.nvm_ops		= &ich8_nvm_ops,
       
  4001 };