devices/e1000e/hw-2.6.37-orig.h
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     1 /*******************************************************************************
       
     2 
       
     3   Intel PRO/1000 Linux driver
       
     4   Copyright(c) 1999 - 2010 Intel Corporation.
       
     5 
       
     6   This program is free software; you can redistribute it and/or modify it
       
     7   under the terms and conditions of the GNU General Public License,
       
     8   version 2, as published by the Free Software Foundation.
       
     9 
       
    10   This program is distributed in the hope it will be useful, but WITHOUT
       
    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
       
    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
       
    13   more details.
       
    14 
       
    15   You should have received a copy of the GNU General Public License along with
       
    16   this program; if not, write to the Free Software Foundation, Inc.,
       
    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
       
    18 
       
    19   The full GNU General Public License is included in this distribution in
       
    20   the file called "COPYING".
       
    21 
       
    22   Contact Information:
       
    23   Linux NICS <linux.nics@intel.com>
       
    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
       
    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
       
    26 
       
    27 *******************************************************************************/
       
    28 
       
    29 #ifndef _E1000_HW_H_
       
    30 #define _E1000_HW_H_
       
    31 
       
    32 #include <linux/types.h>
       
    33 
       
    34 struct e1000_hw;
       
    35 struct e1000_adapter;
       
    36 
       
    37 #include "defines.h"
       
    38 
       
    39 #define er32(reg)	__er32(hw, E1000_##reg)
       
    40 #define ew32(reg,val)	__ew32(hw, E1000_##reg, (val))
       
    41 #define e1e_flush()	er32(STATUS)
       
    42 
       
    43 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
       
    44 	(writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
       
    45 
       
    46 #define E1000_READ_REG_ARRAY(a, reg, offset) \
       
    47 	(readl((a)->hw_addr + reg + ((offset) << 2)))
       
    48 
       
    49 enum e1e_registers {
       
    50 	E1000_CTRL     = 0x00000, /* Device Control - RW */
       
    51 	E1000_STATUS   = 0x00008, /* Device Status - RO */
       
    52 	E1000_EECD     = 0x00010, /* EEPROM/Flash Control - RW */
       
    53 	E1000_EERD     = 0x00014, /* EEPROM Read - RW */
       
    54 	E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
       
    55 	E1000_FLA      = 0x0001C, /* Flash Access - RW */
       
    56 	E1000_MDIC     = 0x00020, /* MDI Control - RW */
       
    57 	E1000_SCTL     = 0x00024, /* SerDes Control - RW */
       
    58 	E1000_FCAL     = 0x00028, /* Flow Control Address Low - RW */
       
    59 	E1000_FCAH     = 0x0002C, /* Flow Control Address High -RW */
       
    60 	E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
       
    61 	E1000_FEXTNVM  = 0x00028, /* Future Extended NVM - RW */
       
    62 	E1000_FCT      = 0x00030, /* Flow Control Type - RW */
       
    63 	E1000_VET      = 0x00038, /* VLAN Ether Type - RW */
       
    64 	E1000_ICR      = 0x000C0, /* Interrupt Cause Read - R/clr */
       
    65 	E1000_ITR      = 0x000C4, /* Interrupt Throttling Rate - RW */
       
    66 	E1000_ICS      = 0x000C8, /* Interrupt Cause Set - WO */
       
    67 	E1000_IMS      = 0x000D0, /* Interrupt Mask Set - RW */
       
    68 	E1000_IMC      = 0x000D8, /* Interrupt Mask Clear - WO */
       
    69 	E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
       
    70 	E1000_IAM      = 0x000E0, /* Interrupt Acknowledge Auto Mask */
       
    71 	E1000_IVAR     = 0x000E4, /* Interrupt Vector Allocation - RW */
       
    72 	E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
       
    73 #define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
       
    74 	E1000_RCTL     = 0x00100, /* Rx Control - RW */
       
    75 	E1000_FCTTV    = 0x00170, /* Flow Control Transmit Timer Value - RW */
       
    76 	E1000_TXCW     = 0x00178, /* Tx Configuration Word - RW */
       
    77 	E1000_RXCW     = 0x00180, /* Rx Configuration Word - RO */
       
    78 	E1000_TCTL     = 0x00400, /* Tx Control - RW */
       
    79 	E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
       
    80 	E1000_TIPG     = 0x00410, /* Tx Inter-packet gap -RW */
       
    81 	E1000_AIT      = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
       
    82 	E1000_LEDCTL   = 0x00E00, /* LED Control - RW */
       
    83 	E1000_EXTCNF_CTRL  = 0x00F00, /* Extended Configuration Control */
       
    84 	E1000_EXTCNF_SIZE  = 0x00F08, /* Extended Configuration Size */
       
    85 	E1000_PHY_CTRL     = 0x00F10, /* PHY Control Register in CSR */
       
    86 	E1000_PBA      = 0x01000, /* Packet Buffer Allocation - RW */
       
    87 	E1000_PBS      = 0x01008, /* Packet Buffer Size */
       
    88 	E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
       
    89 	E1000_EEWR     = 0x0102C, /* EEPROM Write Register - RW */
       
    90 	E1000_FLOP     = 0x0103C, /* FLASH Opcode Register */
       
    91 	E1000_PBA_ECC  = 0x01100, /* PBA ECC Register */
       
    92 	E1000_ERT      = 0x02008, /* Early Rx Threshold - RW */
       
    93 	E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */
       
    94 	E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */
       
    95 	E1000_PSRCTL   = 0x02170, /* Packet Split Receive Control - RW */
       
    96 	E1000_RDBAL    = 0x02800, /* Rx Descriptor Base Address Low - RW */
       
    97 	E1000_RDBAH    = 0x02804, /* Rx Descriptor Base Address High - RW */
       
    98 	E1000_RDLEN    = 0x02808, /* Rx Descriptor Length - RW */
       
    99 	E1000_RDH      = 0x02810, /* Rx Descriptor Head - RW */
       
   100 	E1000_RDT      = 0x02818, /* Rx Descriptor Tail - RW */
       
   101 	E1000_RDTR     = 0x02820, /* Rx Delay Timer - RW */
       
   102 	E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
       
   103 #define E1000_RXDCTL(_n)   (E1000_RXDCTL_BASE + (_n << 8))
       
   104 	E1000_RADV     = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
       
   105 
       
   106 /* Convenience macros
       
   107  *
       
   108  * Note: "_n" is the queue number of the register to be written to.
       
   109  *
       
   110  * Example usage:
       
   111  * E1000_RDBAL_REG(current_rx_queue)
       
   112  *
       
   113  */
       
   114 #define E1000_RDBAL_REG(_n)   (E1000_RDBAL + (_n << 8))
       
   115 	E1000_KABGTXD  = 0x03004, /* AFE Band Gap Transmit Ref Data */
       
   116 	E1000_TDBAL    = 0x03800, /* Tx Descriptor Base Address Low - RW */
       
   117 	E1000_TDBAH    = 0x03804, /* Tx Descriptor Base Address High - RW */
       
   118 	E1000_TDLEN    = 0x03808, /* Tx Descriptor Length - RW */
       
   119 	E1000_TDH      = 0x03810, /* Tx Descriptor Head - RW */
       
   120 	E1000_TDT      = 0x03818, /* Tx Descriptor Tail - RW */
       
   121 	E1000_TIDV     = 0x03820, /* Tx Interrupt Delay Value - RW */
       
   122 	E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
       
   123 #define E1000_TXDCTL(_n)   (E1000_TXDCTL_BASE + (_n << 8))
       
   124 	E1000_TADV     = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
       
   125 	E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
       
   126 #define E1000_TARC(_n)   (E1000_TARC_BASE + (_n << 8))
       
   127 	E1000_CRCERRS  = 0x04000, /* CRC Error Count - R/clr */
       
   128 	E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
       
   129 	E1000_SYMERRS  = 0x04008, /* Symbol Error Count - R/clr */
       
   130 	E1000_RXERRC   = 0x0400C, /* Receive Error Count - R/clr */
       
   131 	E1000_MPC      = 0x04010, /* Missed Packet Count - R/clr */
       
   132 	E1000_SCC      = 0x04014, /* Single Collision Count - R/clr */
       
   133 	E1000_ECOL     = 0x04018, /* Excessive Collision Count - R/clr */
       
   134 	E1000_MCC      = 0x0401C, /* Multiple Collision Count - R/clr */
       
   135 	E1000_LATECOL  = 0x04020, /* Late Collision Count - R/clr */
       
   136 	E1000_COLC     = 0x04028, /* Collision Count - R/clr */
       
   137 	E1000_DC       = 0x04030, /* Defer Count - R/clr */
       
   138 	E1000_TNCRS    = 0x04034, /* Tx-No CRS - R/clr */
       
   139 	E1000_SEC      = 0x04038, /* Sequence Error Count - R/clr */
       
   140 	E1000_CEXTERR  = 0x0403C, /* Carrier Extension Error Count - R/clr */
       
   141 	E1000_RLEC     = 0x04040, /* Receive Length Error Count - R/clr */
       
   142 	E1000_XONRXC   = 0x04048, /* XON Rx Count - R/clr */
       
   143 	E1000_XONTXC   = 0x0404C, /* XON Tx Count - R/clr */
       
   144 	E1000_XOFFRXC  = 0x04050, /* XOFF Rx Count - R/clr */
       
   145 	E1000_XOFFTXC  = 0x04054, /* XOFF Tx Count - R/clr */
       
   146 	E1000_FCRUC    = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
       
   147 	E1000_PRC64    = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
       
   148 	E1000_PRC127   = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
       
   149 	E1000_PRC255   = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
       
   150 	E1000_PRC511   = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
       
   151 	E1000_PRC1023  = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
       
   152 	E1000_PRC1522  = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
       
   153 	E1000_GPRC     = 0x04074, /* Good Packets Rx Count - R/clr */
       
   154 	E1000_BPRC     = 0x04078, /* Broadcast Packets Rx Count - R/clr */
       
   155 	E1000_MPRC     = 0x0407C, /* Multicast Packets Rx Count - R/clr */
       
   156 	E1000_GPTC     = 0x04080, /* Good Packets Tx Count - R/clr */
       
   157 	E1000_GORCL    = 0x04088, /* Good Octets Rx Count Low - R/clr */
       
   158 	E1000_GORCH    = 0x0408C, /* Good Octets Rx Count High - R/clr */
       
   159 	E1000_GOTCL    = 0x04090, /* Good Octets Tx Count Low - R/clr */
       
   160 	E1000_GOTCH    = 0x04094, /* Good Octets Tx Count High - R/clr */
       
   161 	E1000_RNBC     = 0x040A0, /* Rx No Buffers Count - R/clr */
       
   162 	E1000_RUC      = 0x040A4, /* Rx Undersize Count - R/clr */
       
   163 	E1000_RFC      = 0x040A8, /* Rx Fragment Count - R/clr */
       
   164 	E1000_ROC      = 0x040AC, /* Rx Oversize Count - R/clr */
       
   165 	E1000_RJC      = 0x040B0, /* Rx Jabber Count - R/clr */
       
   166 	E1000_MGTPRC   = 0x040B4, /* Management Packets Rx Count - R/clr */
       
   167 	E1000_MGTPDC   = 0x040B8, /* Management Packets Dropped Count - R/clr */
       
   168 	E1000_MGTPTC   = 0x040BC, /* Management Packets Tx Count - R/clr */
       
   169 	E1000_TORL     = 0x040C0, /* Total Octets Rx Low - R/clr */
       
   170 	E1000_TORH     = 0x040C4, /* Total Octets Rx High - R/clr */
       
   171 	E1000_TOTL     = 0x040C8, /* Total Octets Tx Low - R/clr */
       
   172 	E1000_TOTH     = 0x040CC, /* Total Octets Tx High - R/clr */
       
   173 	E1000_TPR      = 0x040D0, /* Total Packets Rx - R/clr */
       
   174 	E1000_TPT      = 0x040D4, /* Total Packets Tx - R/clr */
       
   175 	E1000_PTC64    = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
       
   176 	E1000_PTC127   = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
       
   177 	E1000_PTC255   = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
       
   178 	E1000_PTC511   = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
       
   179 	E1000_PTC1023  = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
       
   180 	E1000_PTC1522  = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
       
   181 	E1000_MPTC     = 0x040F0, /* Multicast Packets Tx Count - R/clr */
       
   182 	E1000_BPTC     = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
       
   183 	E1000_TSCTC    = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
       
   184 	E1000_TSCTFC   = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
       
   185 	E1000_IAC      = 0x04100, /* Interrupt Assertion Count */
       
   186 	E1000_ICRXPTC  = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
       
   187 	E1000_ICRXATC  = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
       
   188 	E1000_ICTXPTC  = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
       
   189 	E1000_ICTXATC  = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
       
   190 	E1000_ICTXQEC  = 0x04118, /* Irq Cause Tx Queue Empty Count */
       
   191 	E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
       
   192 	E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
       
   193 	E1000_ICRXOC   = 0x04124, /* Irq Cause Receiver Overrun Count */
       
   194 	E1000_RXCSUM   = 0x05000, /* Rx Checksum Control - RW */
       
   195 	E1000_RFCTL    = 0x05008, /* Receive Filter Control */
       
   196 	E1000_MTA      = 0x05200, /* Multicast Table Array - RW Array */
       
   197 	E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
       
   198 #define E1000_RAL(_n)   (E1000_RAL_BASE + ((_n) * 8))
       
   199 #define E1000_RA        (E1000_RAL(0))
       
   200 	E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
       
   201 #define E1000_RAH(_n)   (E1000_RAH_BASE + ((_n) * 8))
       
   202 	E1000_VFTA     = 0x05600, /* VLAN Filter Table Array - RW Array */
       
   203 	E1000_WUC      = 0x05800, /* Wakeup Control - RW */
       
   204 	E1000_WUFC     = 0x05808, /* Wakeup Filter Control - RW */
       
   205 	E1000_WUS      = 0x05810, /* Wakeup Status - RO */
       
   206 	E1000_MANC     = 0x05820, /* Management Control - RW */
       
   207 	E1000_FFLT     = 0x05F00, /* Flexible Filter Length Table - RW Array */
       
   208 	E1000_HOST_IF  = 0x08800, /* Host Interface */
       
   209 
       
   210 	E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
       
   211 	E1000_MANC2H    = 0x05860, /* Management Control To Host - RW */
       
   212 	E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
       
   213 #define E1000_MDEF(_n)   (E1000_MDEF_BASE + ((_n) * 4))
       
   214 	E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
       
   215 	E1000_GCR	= 0x05B00, /* PCI-Ex Control */
       
   216 	E1000_GCR2      = 0x05B64, /* PCI-Ex Control #2 */
       
   217 	E1000_FACTPS    = 0x05B30, /* Function Active and Power State to MNG */
       
   218 	E1000_SWSM      = 0x05B50, /* SW Semaphore */
       
   219 	E1000_FWSM      = 0x05B54, /* FW Semaphore */
       
   220 	E1000_SWSM2     = 0x05B58, /* Driver-only SW semaphore */
       
   221 	E1000_FFLT_DBG  = 0x05F04, /* Debug Register */
       
   222 	E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
       
   223 #define E1000_PCH_RAICC(_n)	(E1000_PCH_RAICC_BASE + ((_n) * 4))
       
   224 #define E1000_CRC_OFFSET	E1000_PCH_RAICC_BASE
       
   225 	E1000_HICR      = 0x08F00, /* Host Interface Control */
       
   226 };
       
   227 
       
   228 #define E1000_MAX_PHY_ADDR		4
       
   229 
       
   230 /* IGP01E1000 Specific Registers */
       
   231 #define IGP01E1000_PHY_PORT_CONFIG	0x10 /* Port Config */
       
   232 #define IGP01E1000_PHY_PORT_STATUS	0x11 /* Status */
       
   233 #define IGP01E1000_PHY_PORT_CTRL	0x12 /* Control */
       
   234 #define IGP01E1000_PHY_LINK_HEALTH	0x13 /* PHY Link Health */
       
   235 #define IGP02E1000_PHY_POWER_MGMT	0x19 /* Power Management */
       
   236 #define IGP01E1000_PHY_PAGE_SELECT	0x1F /* Page Select */
       
   237 #define BM_PHY_PAGE_SELECT		22   /* Page Select for BM */
       
   238 #define IGP_PAGE_SHIFT			5
       
   239 #define PHY_REG_MASK			0x1F
       
   240 
       
   241 #define BM_WUC_PAGE			800
       
   242 #define BM_WUC_ADDRESS_OPCODE		0x11
       
   243 #define BM_WUC_DATA_OPCODE		0x12
       
   244 #define BM_WUC_ENABLE_PAGE		769
       
   245 #define BM_WUC_ENABLE_REG		17
       
   246 #define BM_WUC_ENABLE_BIT		(1 << 2)
       
   247 #define BM_WUC_HOST_WU_BIT		(1 << 4)
       
   248 
       
   249 #define BM_WUC	PHY_REG(BM_WUC_PAGE, 1)
       
   250 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
       
   251 #define BM_WUS	PHY_REG(BM_WUC_PAGE, 3)
       
   252 
       
   253 #define IGP01E1000_PHY_PCS_INIT_REG	0x00B4
       
   254 #define IGP01E1000_PHY_POLARITY_MASK	0x0078
       
   255 
       
   256 #define IGP01E1000_PSCR_AUTO_MDIX	0x1000
       
   257 #define IGP01E1000_PSCR_FORCE_MDI_MDIX	0x2000 /* 0=MDI, 1=MDIX */
       
   258 
       
   259 #define IGP01E1000_PSCFR_SMART_SPEED	0x0080
       
   260 
       
   261 #define IGP02E1000_PM_SPD		0x0001 /* Smart Power Down */
       
   262 #define IGP02E1000_PM_D0_LPLU		0x0002 /* For D0a states */
       
   263 #define IGP02E1000_PM_D3_LPLU		0x0004 /* For all other states */
       
   264 
       
   265 #define IGP01E1000_PLHR_SS_DOWNGRADE	0x8000
       
   266 
       
   267 #define IGP01E1000_PSSR_POLARITY_REVERSED	0x0002
       
   268 #define IGP01E1000_PSSR_MDIX			0x0800
       
   269 #define IGP01E1000_PSSR_SPEED_MASK		0xC000
       
   270 #define IGP01E1000_PSSR_SPEED_1000MBPS		0xC000
       
   271 
       
   272 #define IGP02E1000_PHY_CHANNEL_NUM		4
       
   273 #define IGP02E1000_PHY_AGC_A			0x11B1
       
   274 #define IGP02E1000_PHY_AGC_B			0x12B1
       
   275 #define IGP02E1000_PHY_AGC_C			0x14B1
       
   276 #define IGP02E1000_PHY_AGC_D			0x18B1
       
   277 
       
   278 #define IGP02E1000_AGC_LENGTH_SHIFT	9 /* Course - 15:13, Fine - 12:9 */
       
   279 #define IGP02E1000_AGC_LENGTH_MASK	0x7F
       
   280 #define IGP02E1000_AGC_RANGE		15
       
   281 
       
   282 /* manage.c */
       
   283 #define E1000_VFTA_ENTRY_SHIFT		5
       
   284 #define E1000_VFTA_ENTRY_MASK		0x7F
       
   285 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK	0x1F
       
   286 
       
   287 #define E1000_HICR_EN			0x01  /* Enable bit - RO */
       
   288 /* Driver sets this bit when done to put command in RAM */
       
   289 #define E1000_HICR_C			0x02
       
   290 #define E1000_HICR_FW_RESET_ENABLE	0x40
       
   291 #define E1000_HICR_FW_RESET		0x80
       
   292 
       
   293 #define E1000_FWSM_MODE_MASK		0xE
       
   294 #define E1000_FWSM_MODE_SHIFT		1
       
   295 
       
   296 #define E1000_MNG_IAMT_MODE		0x3
       
   297 #define E1000_MNG_DHCP_COOKIE_LENGTH	0x10
       
   298 #define E1000_MNG_DHCP_COOKIE_OFFSET	0x6F0
       
   299 #define E1000_MNG_DHCP_COMMAND_TIMEOUT	10
       
   300 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD	64
       
   301 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING	0x1
       
   302 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN	0x2
       
   303 
       
   304 /* nvm.c */
       
   305 #define E1000_STM_OPCODE  0xDB00
       
   306 
       
   307 #define E1000_KMRNCTRLSTA_OFFSET	0x001F0000
       
   308 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT	16
       
   309 #define E1000_KMRNCTRLSTA_REN		0x00200000
       
   310 #define E1000_KMRNCTRLSTA_CTRL_OFFSET	0x1    /* Kumeran Control */
       
   311 #define E1000_KMRNCTRLSTA_DIAG_OFFSET	0x3    /* Kumeran Diagnostic */
       
   312 #define E1000_KMRNCTRLSTA_TIMEOUTS	0x4    /* Kumeran Timeouts */
       
   313 #define E1000_KMRNCTRLSTA_INBAND_PARAM	0x9    /* Kumeran InBand Parameters */
       
   314 #define E1000_KMRNCTRLSTA_DIAG_NELPBK	0x1000 /* Nearend Loopback mode */
       
   315 #define E1000_KMRNCTRLSTA_K1_CONFIG	0x7
       
   316 #define E1000_KMRNCTRLSTA_K1_ENABLE	0x0002
       
   317 #define E1000_KMRNCTRLSTA_HD_CTRL	0x10   /* Kumeran HD Control */
       
   318 
       
   319 #define IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
       
   320 #define IFE_PHY_SPECIAL_CONTROL		0x11 /* 100BaseTx PHY Special Control */
       
   321 #define IFE_PHY_SPECIAL_CONTROL_LED	0x1B /* PHY Special and LED Control */
       
   322 #define IFE_PHY_MDIX_CONTROL		0x1C /* MDI/MDI-X Control */
       
   323 
       
   324 /* IFE PHY Extended Status Control */
       
   325 #define IFE_PESC_POLARITY_REVERSED	0x0100
       
   326 
       
   327 /* IFE PHY Special Control */
       
   328 #define IFE_PSC_AUTO_POLARITY_DISABLE		0x0010
       
   329 #define IFE_PSC_FORCE_POLARITY			0x0020
       
   330 
       
   331 /* IFE PHY Special Control and LED Control */
       
   332 #define IFE_PSCL_PROBE_MODE		0x0020
       
   333 #define IFE_PSCL_PROBE_LEDS_OFF		0x0006 /* Force LEDs 0 and 2 off */
       
   334 #define IFE_PSCL_PROBE_LEDS_ON		0x0007 /* Force LEDs 0 and 2 on */
       
   335 
       
   336 /* IFE PHY MDIX Control */
       
   337 #define IFE_PMC_MDIX_STATUS	0x0020 /* 1=MDI-X, 0=MDI */
       
   338 #define IFE_PMC_FORCE_MDIX	0x0040 /* 1=force MDI-X, 0=force MDI */
       
   339 #define IFE_PMC_AUTO_MDIX	0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
       
   340 
       
   341 #define E1000_CABLE_LENGTH_UNDEFINED	0xFF
       
   342 
       
   343 #define E1000_DEV_ID_82571EB_COPPER		0x105E
       
   344 #define E1000_DEV_ID_82571EB_FIBER		0x105F
       
   345 #define E1000_DEV_ID_82571EB_SERDES		0x1060
       
   346 #define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
       
   347 #define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
       
   348 #define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
       
   349 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
       
   350 #define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
       
   351 #define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
       
   352 #define E1000_DEV_ID_82572EI_COPPER		0x107D
       
   353 #define E1000_DEV_ID_82572EI_FIBER		0x107E
       
   354 #define E1000_DEV_ID_82572EI_SERDES		0x107F
       
   355 #define E1000_DEV_ID_82572EI			0x10B9
       
   356 #define E1000_DEV_ID_82573E			0x108B
       
   357 #define E1000_DEV_ID_82573E_IAMT		0x108C
       
   358 #define E1000_DEV_ID_82573L			0x109A
       
   359 #define E1000_DEV_ID_82574L			0x10D3
       
   360 #define E1000_DEV_ID_82574LA			0x10F6
       
   361 #define E1000_DEV_ID_82583V                     0x150C
       
   362 
       
   363 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
       
   364 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
       
   365 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
       
   366 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
       
   367 
       
   368 #define E1000_DEV_ID_ICH8_82567V_3		0x1501
       
   369 #define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
       
   370 #define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
       
   371 #define E1000_DEV_ID_ICH8_IGP_C			0x104B
       
   372 #define E1000_DEV_ID_ICH8_IFE			0x104C
       
   373 #define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
       
   374 #define E1000_DEV_ID_ICH8_IFE_G			0x10C5
       
   375 #define E1000_DEV_ID_ICH8_IGP_M			0x104D
       
   376 #define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
       
   377 #define E1000_DEV_ID_ICH9_BM			0x10E5
       
   378 #define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
       
   379 #define E1000_DEV_ID_ICH9_IGP_M			0x10BF
       
   380 #define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
       
   381 #define E1000_DEV_ID_ICH9_IGP_C			0x294C
       
   382 #define E1000_DEV_ID_ICH9_IFE			0x10C0
       
   383 #define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
       
   384 #define E1000_DEV_ID_ICH9_IFE_G			0x10C2
       
   385 #define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
       
   386 #define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
       
   387 #define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
       
   388 #define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
       
   389 #define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
       
   390 #define E1000_DEV_ID_ICH10_D_BM_V		0x1525
       
   391 #define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
       
   392 #define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
       
   393 #define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
       
   394 #define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
       
   395 #define E1000_DEV_ID_PCH2_LV_LM			0x1502
       
   396 #define E1000_DEV_ID_PCH2_LV_V			0x1503
       
   397 
       
   398 #define E1000_REVISION_4 4
       
   399 
       
   400 #define E1000_FUNC_1 1
       
   401 
       
   402 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
       
   403 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
       
   404 
       
   405 enum e1000_mac_type {
       
   406 	e1000_82571,
       
   407 	e1000_82572,
       
   408 	e1000_82573,
       
   409 	e1000_82574,
       
   410 	e1000_82583,
       
   411 	e1000_80003es2lan,
       
   412 	e1000_ich8lan,
       
   413 	e1000_ich9lan,
       
   414 	e1000_ich10lan,
       
   415 	e1000_pchlan,
       
   416 	e1000_pch2lan,
       
   417 };
       
   418 
       
   419 enum e1000_media_type {
       
   420 	e1000_media_type_unknown = 0,
       
   421 	e1000_media_type_copper = 1,
       
   422 	e1000_media_type_fiber = 2,
       
   423 	e1000_media_type_internal_serdes = 3,
       
   424 	e1000_num_media_types
       
   425 };
       
   426 
       
   427 enum e1000_nvm_type {
       
   428 	e1000_nvm_unknown = 0,
       
   429 	e1000_nvm_none,
       
   430 	e1000_nvm_eeprom_spi,
       
   431 	e1000_nvm_flash_hw,
       
   432 	e1000_nvm_flash_sw
       
   433 };
       
   434 
       
   435 enum e1000_nvm_override {
       
   436 	e1000_nvm_override_none = 0,
       
   437 	e1000_nvm_override_spi_small,
       
   438 	e1000_nvm_override_spi_large
       
   439 };
       
   440 
       
   441 enum e1000_phy_type {
       
   442 	e1000_phy_unknown = 0,
       
   443 	e1000_phy_none,
       
   444 	e1000_phy_m88,
       
   445 	e1000_phy_igp,
       
   446 	e1000_phy_igp_2,
       
   447 	e1000_phy_gg82563,
       
   448 	e1000_phy_igp_3,
       
   449 	e1000_phy_ife,
       
   450 	e1000_phy_bm,
       
   451 	e1000_phy_82578,
       
   452 	e1000_phy_82577,
       
   453 	e1000_phy_82579,
       
   454 };
       
   455 
       
   456 enum e1000_bus_width {
       
   457 	e1000_bus_width_unknown = 0,
       
   458 	e1000_bus_width_pcie_x1,
       
   459 	e1000_bus_width_pcie_x2,
       
   460 	e1000_bus_width_pcie_x4 = 4,
       
   461 	e1000_bus_width_32,
       
   462 	e1000_bus_width_64,
       
   463 	e1000_bus_width_reserved
       
   464 };
       
   465 
       
   466 enum e1000_1000t_rx_status {
       
   467 	e1000_1000t_rx_status_not_ok = 0,
       
   468 	e1000_1000t_rx_status_ok,
       
   469 	e1000_1000t_rx_status_undefined = 0xFF
       
   470 };
       
   471 
       
   472 enum e1000_rev_polarity{
       
   473 	e1000_rev_polarity_normal = 0,
       
   474 	e1000_rev_polarity_reversed,
       
   475 	e1000_rev_polarity_undefined = 0xFF
       
   476 };
       
   477 
       
   478 enum e1000_fc_mode {
       
   479 	e1000_fc_none = 0,
       
   480 	e1000_fc_rx_pause,
       
   481 	e1000_fc_tx_pause,
       
   482 	e1000_fc_full,
       
   483 	e1000_fc_default = 0xFF
       
   484 };
       
   485 
       
   486 enum e1000_ms_type {
       
   487 	e1000_ms_hw_default = 0,
       
   488 	e1000_ms_force_master,
       
   489 	e1000_ms_force_slave,
       
   490 	e1000_ms_auto
       
   491 };
       
   492 
       
   493 enum e1000_smart_speed {
       
   494 	e1000_smart_speed_default = 0,
       
   495 	e1000_smart_speed_on,
       
   496 	e1000_smart_speed_off
       
   497 };
       
   498 
       
   499 enum e1000_serdes_link_state {
       
   500 	e1000_serdes_link_down = 0,
       
   501 	e1000_serdes_link_autoneg_progress,
       
   502 	e1000_serdes_link_autoneg_complete,
       
   503 	e1000_serdes_link_forced_up
       
   504 };
       
   505 
       
   506 /* Receive Descriptor */
       
   507 struct e1000_rx_desc {
       
   508 	__le64 buffer_addr; /* Address of the descriptor's data buffer */
       
   509 	__le16 length;      /* Length of data DMAed into data buffer */
       
   510 	__le16 csum;	/* Packet checksum */
       
   511 	u8  status;      /* Descriptor status */
       
   512 	u8  errors;      /* Descriptor Errors */
       
   513 	__le16 special;
       
   514 };
       
   515 
       
   516 /* Receive Descriptor - Extended */
       
   517 union e1000_rx_desc_extended {
       
   518 	struct {
       
   519 		__le64 buffer_addr;
       
   520 		__le64 reserved;
       
   521 	} read;
       
   522 	struct {
       
   523 		struct {
       
   524 			__le32 mrq;	      /* Multiple Rx Queues */
       
   525 			union {
       
   526 				__le32 rss;	    /* RSS Hash */
       
   527 				struct {
       
   528 					__le16 ip_id;  /* IP id */
       
   529 					__le16 csum;   /* Packet Checksum */
       
   530 				} csum_ip;
       
   531 			} hi_dword;
       
   532 		} lower;
       
   533 		struct {
       
   534 			__le32 status_error;     /* ext status/error */
       
   535 			__le16 length;
       
   536 			__le16 vlan;	     /* VLAN tag */
       
   537 		} upper;
       
   538 	} wb;  /* writeback */
       
   539 };
       
   540 
       
   541 #define MAX_PS_BUFFERS 4
       
   542 /* Receive Descriptor - Packet Split */
       
   543 union e1000_rx_desc_packet_split {
       
   544 	struct {
       
   545 		/* one buffer for protocol header(s), three data buffers */
       
   546 		__le64 buffer_addr[MAX_PS_BUFFERS];
       
   547 	} read;
       
   548 	struct {
       
   549 		struct {
       
   550 			__le32 mrq;	      /* Multiple Rx Queues */
       
   551 			union {
       
   552 				__le32 rss;	      /* RSS Hash */
       
   553 				struct {
       
   554 					__le16 ip_id;    /* IP id */
       
   555 					__le16 csum;     /* Packet Checksum */
       
   556 				} csum_ip;
       
   557 			} hi_dword;
       
   558 		} lower;
       
   559 		struct {
       
   560 			__le32 status_error;     /* ext status/error */
       
   561 			__le16 length0;	  /* length of buffer 0 */
       
   562 			__le16 vlan;	     /* VLAN tag */
       
   563 		} middle;
       
   564 		struct {
       
   565 			__le16 header_status;
       
   566 			__le16 length[3];	/* length of buffers 1-3 */
       
   567 		} upper;
       
   568 		__le64 reserved;
       
   569 	} wb; /* writeback */
       
   570 };
       
   571 
       
   572 /* Transmit Descriptor */
       
   573 struct e1000_tx_desc {
       
   574 	__le64 buffer_addr;      /* Address of the descriptor's data buffer */
       
   575 	union {
       
   576 		__le32 data;
       
   577 		struct {
       
   578 			__le16 length;    /* Data buffer length */
       
   579 			u8 cso;	/* Checksum offset */
       
   580 			u8 cmd;	/* Descriptor control */
       
   581 		} flags;
       
   582 	} lower;
       
   583 	union {
       
   584 		__le32 data;
       
   585 		struct {
       
   586 			u8 status;     /* Descriptor status */
       
   587 			u8 css;	/* Checksum start */
       
   588 			__le16 special;
       
   589 		} fields;
       
   590 	} upper;
       
   591 };
       
   592 
       
   593 /* Offload Context Descriptor */
       
   594 struct e1000_context_desc {
       
   595 	union {
       
   596 		__le32 ip_config;
       
   597 		struct {
       
   598 			u8 ipcss;      /* IP checksum start */
       
   599 			u8 ipcso;      /* IP checksum offset */
       
   600 			__le16 ipcse;     /* IP checksum end */
       
   601 		} ip_fields;
       
   602 	} lower_setup;
       
   603 	union {
       
   604 		__le32 tcp_config;
       
   605 		struct {
       
   606 			u8 tucss;      /* TCP checksum start */
       
   607 			u8 tucso;      /* TCP checksum offset */
       
   608 			__le16 tucse;     /* TCP checksum end */
       
   609 		} tcp_fields;
       
   610 	} upper_setup;
       
   611 	__le32 cmd_and_length;
       
   612 	union {
       
   613 		__le32 data;
       
   614 		struct {
       
   615 			u8 status;     /* Descriptor status */
       
   616 			u8 hdr_len;    /* Header length */
       
   617 			__le16 mss;       /* Maximum segment size */
       
   618 		} fields;
       
   619 	} tcp_seg_setup;
       
   620 };
       
   621 
       
   622 /* Offload data descriptor */
       
   623 struct e1000_data_desc {
       
   624 	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
       
   625 	union {
       
   626 		__le32 data;
       
   627 		struct {
       
   628 			__le16 length;    /* Data buffer length */
       
   629 			u8 typ_len_ext;
       
   630 			u8 cmd;
       
   631 		} flags;
       
   632 	} lower;
       
   633 	union {
       
   634 		__le32 data;
       
   635 		struct {
       
   636 			u8 status;     /* Descriptor status */
       
   637 			u8 popts;      /* Packet Options */
       
   638 			__le16 special;   /* */
       
   639 		} fields;
       
   640 	} upper;
       
   641 };
       
   642 
       
   643 /* Statistics counters collected by the MAC */
       
   644 struct e1000_hw_stats {
       
   645 	u64 crcerrs;
       
   646 	u64 algnerrc;
       
   647 	u64 symerrs;
       
   648 	u64 rxerrc;
       
   649 	u64 mpc;
       
   650 	u64 scc;
       
   651 	u64 ecol;
       
   652 	u64 mcc;
       
   653 	u64 latecol;
       
   654 	u64 colc;
       
   655 	u64 dc;
       
   656 	u64 tncrs;
       
   657 	u64 sec;
       
   658 	u64 cexterr;
       
   659 	u64 rlec;
       
   660 	u64 xonrxc;
       
   661 	u64 xontxc;
       
   662 	u64 xoffrxc;
       
   663 	u64 xofftxc;
       
   664 	u64 fcruc;
       
   665 	u64 prc64;
       
   666 	u64 prc127;
       
   667 	u64 prc255;
       
   668 	u64 prc511;
       
   669 	u64 prc1023;
       
   670 	u64 prc1522;
       
   671 	u64 gprc;
       
   672 	u64 bprc;
       
   673 	u64 mprc;
       
   674 	u64 gptc;
       
   675 	u64 gorc;
       
   676 	u64 gotc;
       
   677 	u64 rnbc;
       
   678 	u64 ruc;
       
   679 	u64 rfc;
       
   680 	u64 roc;
       
   681 	u64 rjc;
       
   682 	u64 mgprc;
       
   683 	u64 mgpdc;
       
   684 	u64 mgptc;
       
   685 	u64 tor;
       
   686 	u64 tot;
       
   687 	u64 tpr;
       
   688 	u64 tpt;
       
   689 	u64 ptc64;
       
   690 	u64 ptc127;
       
   691 	u64 ptc255;
       
   692 	u64 ptc511;
       
   693 	u64 ptc1023;
       
   694 	u64 ptc1522;
       
   695 	u64 mptc;
       
   696 	u64 bptc;
       
   697 	u64 tsctc;
       
   698 	u64 tsctfc;
       
   699 	u64 iac;
       
   700 	u64 icrxptc;
       
   701 	u64 icrxatc;
       
   702 	u64 ictxptc;
       
   703 	u64 ictxatc;
       
   704 	u64 ictxqec;
       
   705 	u64 ictxqmtc;
       
   706 	u64 icrxdmtc;
       
   707 	u64 icrxoc;
       
   708 };
       
   709 
       
   710 struct e1000_phy_stats {
       
   711 	u32 idle_errors;
       
   712 	u32 receive_errors;
       
   713 };
       
   714 
       
   715 struct e1000_host_mng_dhcp_cookie {
       
   716 	u32 signature;
       
   717 	u8  status;
       
   718 	u8  reserved0;
       
   719 	u16 vlan_id;
       
   720 	u32 reserved1;
       
   721 	u16 reserved2;
       
   722 	u8  reserved3;
       
   723 	u8  checksum;
       
   724 };
       
   725 
       
   726 /* Host Interface "Rev 1" */
       
   727 struct e1000_host_command_header {
       
   728 	u8 command_id;
       
   729 	u8 command_length;
       
   730 	u8 command_options;
       
   731 	u8 checksum;
       
   732 };
       
   733 
       
   734 #define E1000_HI_MAX_DATA_LENGTH     252
       
   735 struct e1000_host_command_info {
       
   736 	struct e1000_host_command_header command_header;
       
   737 	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
       
   738 };
       
   739 
       
   740 /* Host Interface "Rev 2" */
       
   741 struct e1000_host_mng_command_header {
       
   742 	u8  command_id;
       
   743 	u8  checksum;
       
   744 	u16 reserved1;
       
   745 	u16 reserved2;
       
   746 	u16 command_length;
       
   747 };
       
   748 
       
   749 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
       
   750 struct e1000_host_mng_command_info {
       
   751 	struct e1000_host_mng_command_header command_header;
       
   752 	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
       
   753 };
       
   754 
       
   755 /* Function pointers and static data for the MAC. */
       
   756 struct e1000_mac_operations {
       
   757 	s32  (*id_led_init)(struct e1000_hw *);
       
   758 	bool (*check_mng_mode)(struct e1000_hw *);
       
   759 	s32  (*check_for_link)(struct e1000_hw *);
       
   760 	s32  (*cleanup_led)(struct e1000_hw *);
       
   761 	void (*clear_hw_cntrs)(struct e1000_hw *);
       
   762 	void (*clear_vfta)(struct e1000_hw *);
       
   763 	s32  (*get_bus_info)(struct e1000_hw *);
       
   764 	void (*set_lan_id)(struct e1000_hw *);
       
   765 	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
       
   766 	s32  (*led_on)(struct e1000_hw *);
       
   767 	s32  (*led_off)(struct e1000_hw *);
       
   768 	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
       
   769 	s32  (*reset_hw)(struct e1000_hw *);
       
   770 	s32  (*init_hw)(struct e1000_hw *);
       
   771 	s32  (*setup_link)(struct e1000_hw *);
       
   772 	s32  (*setup_physical_interface)(struct e1000_hw *);
       
   773 	s32  (*setup_led)(struct e1000_hw *);
       
   774 	void (*write_vfta)(struct e1000_hw *, u32, u32);
       
   775 	s32  (*read_mac_addr)(struct e1000_hw *);
       
   776 };
       
   777 
       
   778 /* Function pointers for the PHY. */
       
   779 struct e1000_phy_operations {
       
   780 	s32  (*acquire)(struct e1000_hw *);
       
   781 	s32  (*cfg_on_link_up)(struct e1000_hw *);
       
   782 	s32  (*check_polarity)(struct e1000_hw *);
       
   783 	s32  (*check_reset_block)(struct e1000_hw *);
       
   784 	s32  (*commit)(struct e1000_hw *);
       
   785 	s32  (*force_speed_duplex)(struct e1000_hw *);
       
   786 	s32  (*get_cfg_done)(struct e1000_hw *hw);
       
   787 	s32  (*get_cable_length)(struct e1000_hw *);
       
   788 	s32  (*get_info)(struct e1000_hw *);
       
   789 	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
       
   790 	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
       
   791 	void (*release)(struct e1000_hw *);
       
   792 	s32  (*reset)(struct e1000_hw *);
       
   793 	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
       
   794 	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
       
   795 	s32  (*write_reg)(struct e1000_hw *, u32, u16);
       
   796 	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
       
   797 	void (*power_up)(struct e1000_hw *);
       
   798 	void (*power_down)(struct e1000_hw *);
       
   799 };
       
   800 
       
   801 /* Function pointers for the NVM. */
       
   802 struct e1000_nvm_operations {
       
   803 	s32  (*acquire)(struct e1000_hw *);
       
   804 	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
       
   805 	void (*release)(struct e1000_hw *);
       
   806 	s32  (*update)(struct e1000_hw *);
       
   807 	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
       
   808 	s32  (*validate)(struct e1000_hw *);
       
   809 	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
       
   810 };
       
   811 
       
   812 struct e1000_mac_info {
       
   813 	struct e1000_mac_operations ops;
       
   814 
       
   815 	u8 addr[6];
       
   816 	u8 perm_addr[6];
       
   817 
       
   818 	enum e1000_mac_type type;
       
   819 
       
   820 	u32 collision_delta;
       
   821 	u32 ledctl_default;
       
   822 	u32 ledctl_mode1;
       
   823 	u32 ledctl_mode2;
       
   824 	u32 mc_filter_type;
       
   825 	u32 tx_packet_delta;
       
   826 	u32 txcw;
       
   827 
       
   828 	u16 current_ifs_val;
       
   829 	u16 ifs_max_val;
       
   830 	u16 ifs_min_val;
       
   831 	u16 ifs_ratio;
       
   832 	u16 ifs_step_size;
       
   833 	u16 mta_reg_count;
       
   834 
       
   835 	/* Maximum size of the MTA register table in all supported adapters */
       
   836 	#define MAX_MTA_REG 128
       
   837 	u32 mta_shadow[MAX_MTA_REG];
       
   838 	u16 rar_entry_count;
       
   839 
       
   840 	u8  forced_speed_duplex;
       
   841 
       
   842 	bool adaptive_ifs;
       
   843 	bool has_fwsm;
       
   844 	bool arc_subsystem_valid;
       
   845 	bool autoneg;
       
   846 	bool autoneg_failed;
       
   847 	bool get_link_status;
       
   848 	bool in_ifs_mode;
       
   849 	bool serdes_has_link;
       
   850 	bool tx_pkt_filtering;
       
   851 	enum e1000_serdes_link_state serdes_link_state;
       
   852 };
       
   853 
       
   854 struct e1000_phy_info {
       
   855 	struct e1000_phy_operations ops;
       
   856 
       
   857 	enum e1000_phy_type type;
       
   858 
       
   859 	enum e1000_1000t_rx_status local_rx;
       
   860 	enum e1000_1000t_rx_status remote_rx;
       
   861 	enum e1000_ms_type ms_type;
       
   862 	enum e1000_ms_type original_ms_type;
       
   863 	enum e1000_rev_polarity cable_polarity;
       
   864 	enum e1000_smart_speed smart_speed;
       
   865 
       
   866 	u32 addr;
       
   867 	u32 id;
       
   868 	u32 reset_delay_us; /* in usec */
       
   869 	u32 revision;
       
   870 
       
   871 	enum e1000_media_type media_type;
       
   872 
       
   873 	u16 autoneg_advertised;
       
   874 	u16 autoneg_mask;
       
   875 	u16 cable_length;
       
   876 	u16 max_cable_length;
       
   877 	u16 min_cable_length;
       
   878 
       
   879 	u8 mdix;
       
   880 
       
   881 	bool disable_polarity_correction;
       
   882 	bool is_mdix;
       
   883 	bool polarity_correction;
       
   884 	bool speed_downgraded;
       
   885 	bool autoneg_wait_to_complete;
       
   886 };
       
   887 
       
   888 struct e1000_nvm_info {
       
   889 	struct e1000_nvm_operations ops;
       
   890 
       
   891 	enum e1000_nvm_type type;
       
   892 	enum e1000_nvm_override override;
       
   893 
       
   894 	u32 flash_bank_size;
       
   895 	u32 flash_base_addr;
       
   896 
       
   897 	u16 word_size;
       
   898 	u16 delay_usec;
       
   899 	u16 address_bits;
       
   900 	u16 opcode_bits;
       
   901 	u16 page_size;
       
   902 };
       
   903 
       
   904 struct e1000_bus_info {
       
   905 	enum e1000_bus_width width;
       
   906 
       
   907 	u16 func;
       
   908 };
       
   909 
       
   910 struct e1000_fc_info {
       
   911 	u32 high_water;          /* Flow control high-water mark */
       
   912 	u32 low_water;           /* Flow control low-water mark */
       
   913 	u16 pause_time;          /* Flow control pause timer */
       
   914 	u16 refresh_time;        /* Flow control refresh timer */
       
   915 	bool send_xon;           /* Flow control send XON */
       
   916 	bool strict_ieee;        /* Strict IEEE mode */
       
   917 	enum e1000_fc_mode current_mode; /* FC mode in effect */
       
   918 	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
       
   919 };
       
   920 
       
   921 struct e1000_dev_spec_82571 {
       
   922 	bool laa_is_present;
       
   923 	u32 smb_counter;
       
   924 };
       
   925 
       
   926 struct e1000_dev_spec_80003es2lan {
       
   927 	bool  mdic_wa_enable;
       
   928 };
       
   929 
       
   930 struct e1000_shadow_ram {
       
   931 	u16  value;
       
   932 	bool modified;
       
   933 };
       
   934 
       
   935 #define E1000_ICH8_SHADOW_RAM_WORDS		2048
       
   936 
       
   937 struct e1000_dev_spec_ich8lan {
       
   938 	bool kmrn_lock_loss_workaround_enabled;
       
   939 	struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
       
   940 	bool nvm_k1_enabled;
       
   941 	bool eee_disable;
       
   942 };
       
   943 
       
   944 struct e1000_hw {
       
   945 	struct e1000_adapter *adapter;
       
   946 
       
   947 	u8 __iomem *hw_addr;
       
   948 	u8 __iomem *flash_address;
       
   949 
       
   950 	struct e1000_mac_info  mac;
       
   951 	struct e1000_fc_info   fc;
       
   952 	struct e1000_phy_info  phy;
       
   953 	struct e1000_nvm_info  nvm;
       
   954 	struct e1000_bus_info  bus;
       
   955 	struct e1000_host_mng_dhcp_cookie mng_cookie;
       
   956 
       
   957 	union {
       
   958 		struct e1000_dev_spec_82571	e82571;
       
   959 		struct e1000_dev_spec_80003es2lan e80003es2lan;
       
   960 		struct e1000_dev_spec_ich8lan	ich8lan;
       
   961 	} dev_spec;
       
   962 };
       
   963 
       
   964 #endif