devices/e1000e/es2lan-2.6.37-ethercat.c
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     1 /*******************************************************************************
       
     2 
       
     3   Intel PRO/1000 Linux driver
       
     4   Copyright(c) 1999 - 2010 Intel Corporation.
       
     5 
       
     6   This program is free software; you can redistribute it and/or modify it
       
     7   under the terms and conditions of the GNU General Public License,
       
     8   version 2, as published by the Free Software Foundation.
       
     9 
       
    10   This program is distributed in the hope it will be useful, but WITHOUT
       
    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
       
    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
       
    13   more details.
       
    14 
       
    15   You should have received a copy of the GNU General Public License along with
       
    16   this program; if not, write to the Free Software Foundation, Inc.,
       
    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
       
    18 
       
    19   The full GNU General Public License is included in this distribution in
       
    20   the file called "COPYING".
       
    21 
       
    22   Contact Information:
       
    23   Linux NICS <linux.nics@intel.com>
       
    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
       
    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
       
    26 
       
    27 *******************************************************************************/
       
    28 
       
    29 /*
       
    30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
       
    31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
       
    32  */
       
    33 
       
    34 #include "e1000-2.6.37-ethercat.h"
       
    35 
       
    36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	 0x00
       
    37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	 0x02
       
    38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	 0x10
       
    39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	 0x1F
       
    40 
       
    41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	 0x0008
       
    42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	 0x0800
       
    43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	 0x0010
       
    44 
       
    45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
       
    46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	 0x0000
       
    47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		 0x2000
       
    48 
       
    49 #define E1000_KMRNCTRLSTA_OPMODE_MASK		 0x000C
       
    50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	 0x0004
       
    51 
       
    52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
       
    53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	 0x00010000
       
    54 
       
    55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	 0x8
       
    56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	 0x9
       
    57 
       
    58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
       
    59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	 0x0002 /* 1=Reversal Disab. */
       
    60 #define GG82563_PSCR_CROSSOVER_MODE_MASK	 0x0060
       
    61 #define GG82563_PSCR_CROSSOVER_MODE_MDI		 0x0000 /* 00=Manual MDI */
       
    62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX	 0x0020 /* 01=Manual MDIX */
       
    63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO	 0x0060 /* 11=Auto crossover */
       
    64 
       
    65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
       
    66 #define GG82563_PSCR2_REVERSE_AUTO_NEG		 0x2000
       
    67 						/* 1=Reverse Auto-Negotiation */
       
    68 
       
    69 /* MAC Specific Control Register (Page 2, Register 21) */
       
    70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
       
    71 #define GG82563_MSCR_TX_CLK_MASK		 0x0007
       
    72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5		 0x0004
       
    73 #define GG82563_MSCR_TX_CLK_100MBPS_25		 0x0005
       
    74 #define GG82563_MSCR_TX_CLK_1000MBPS_25		 0x0007
       
    75 
       
    76 #define GG82563_MSCR_ASSERT_CRS_ON_TX		 0x0010 /* 1=Assert */
       
    77 
       
    78 /* DSP Distance Register (Page 5, Register 26) */
       
    79 #define GG82563_DSPD_CABLE_LENGTH		 0x0007 /* 0 = <50M
       
    80 							   1 = 50-80M
       
    81 							   2 = 80-110M
       
    82 							   3 = 110-140M
       
    83 							   4 = >140M */
       
    84 
       
    85 /* Kumeran Mode Control Register (Page 193, Register 16) */
       
    86 #define GG82563_KMCR_PASS_FALSE_CARRIER		 0x0800
       
    87 
       
    88 /* Max number of times Kumeran read/write should be validated */
       
    89 #define GG82563_MAX_KMRN_RETRY  0x5
       
    90 
       
    91 /* Power Management Control Register (Page 193, Register 20) */
       
    92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	 0x0001
       
    93 					   /* 1=Enable SERDES Electrical Idle */
       
    94 
       
    95 /* In-Band Control Register (Page 194, Register 18) */
       
    96 #define GG82563_ICR_DIS_PADDING			 0x0010 /* Disable Padding */
       
    97 
       
    98 /*
       
    99  * A table for the GG82563 cable length where the range is defined
       
   100  * with a lower bound at "index" and the upper bound at
       
   101  * "index + 5".
       
   102  */
       
   103 static const u16 e1000_gg82563_cable_length_table[] =
       
   104 	 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
       
   105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
       
   106 		ARRAY_SIZE(e1000_gg82563_cable_length_table)
       
   107 
       
   108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
       
   109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
       
   110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
       
   111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
       
   112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
       
   113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
       
   114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
       
   115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
       
   116 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
       
   117                                             u16 *data);
       
   118 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
       
   119                                              u16 data);
       
   120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
       
   121 
       
   122 /**
       
   123  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
       
   124  *  @hw: pointer to the HW structure
       
   125  **/
       
   126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
       
   127 {
       
   128 	struct e1000_phy_info *phy = &hw->phy;
       
   129 	s32 ret_val;
       
   130 
       
   131 	if (hw->phy.media_type != e1000_media_type_copper) {
       
   132 		phy->type	= e1000_phy_none;
       
   133 		return 0;
       
   134 	} else {
       
   135 		phy->ops.power_up = e1000_power_up_phy_copper;
       
   136 		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
       
   137 	}
       
   138 
       
   139 	phy->addr		= 1;
       
   140 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
       
   141 	phy->reset_delay_us      = 100;
       
   142 	phy->type		= e1000_phy_gg82563;
       
   143 
       
   144 	/* This can only be done after all function pointers are setup. */
       
   145 	ret_val = e1000e_get_phy_id(hw);
       
   146 
       
   147 	/* Verify phy id */
       
   148 	if (phy->id != GG82563_E_PHY_ID)
       
   149 		return -E1000_ERR_PHY;
       
   150 
       
   151 	return ret_val;
       
   152 }
       
   153 
       
   154 /**
       
   155  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
       
   156  *  @hw: pointer to the HW structure
       
   157  **/
       
   158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
       
   159 {
       
   160 	struct e1000_nvm_info *nvm = &hw->nvm;
       
   161 	u32 eecd = er32(EECD);
       
   162 	u16 size;
       
   163 
       
   164 	nvm->opcode_bits	= 8;
       
   165 	nvm->delay_usec	 = 1;
       
   166 	switch (nvm->override) {
       
   167 	case e1000_nvm_override_spi_large:
       
   168 		nvm->page_size    = 32;
       
   169 		nvm->address_bits = 16;
       
   170 		break;
       
   171 	case e1000_nvm_override_spi_small:
       
   172 		nvm->page_size    = 8;
       
   173 		nvm->address_bits = 8;
       
   174 		break;
       
   175 	default:
       
   176 		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
       
   177 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
       
   178 		break;
       
   179 	}
       
   180 
       
   181 	nvm->type = e1000_nvm_eeprom_spi;
       
   182 
       
   183 	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
       
   184 			  E1000_EECD_SIZE_EX_SHIFT);
       
   185 
       
   186 	/*
       
   187 	 * Added to a constant, "size" becomes the left-shift value
       
   188 	 * for setting word_size.
       
   189 	 */
       
   190 	size += NVM_WORD_SIZE_BASE_SHIFT;
       
   191 
       
   192 	/* EEPROM access above 16k is unsupported */
       
   193 	if (size > 14)
       
   194 		size = 14;
       
   195 	nvm->word_size	= 1 << size;
       
   196 
       
   197 	return 0;
       
   198 }
       
   199 
       
   200 /**
       
   201  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
       
   202  *  @hw: pointer to the HW structure
       
   203  **/
       
   204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
       
   205 {
       
   206 	struct e1000_hw *hw = &adapter->hw;
       
   207 	struct e1000_mac_info *mac = &hw->mac;
       
   208 	struct e1000_mac_operations *func = &mac->ops;
       
   209 
       
   210 	/* Set media type */
       
   211 	switch (adapter->pdev->device) {
       
   212 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
       
   213 		hw->phy.media_type = e1000_media_type_internal_serdes;
       
   214 		break;
       
   215 	default:
       
   216 		hw->phy.media_type = e1000_media_type_copper;
       
   217 		break;
       
   218 	}
       
   219 
       
   220 	/* Set mta register count */
       
   221 	mac->mta_reg_count = 128;
       
   222 	/* Set rar entry count */
       
   223 	mac->rar_entry_count = E1000_RAR_ENTRIES;
       
   224 	/* FWSM register */
       
   225 	mac->has_fwsm = true;
       
   226 	/* ARC supported; valid only if manageability features are enabled. */
       
   227 	mac->arc_subsystem_valid =
       
   228 	        (er32(FWSM) & E1000_FWSM_MODE_MASK)
       
   229 	                ? true : false;
       
   230 	/* Adaptive IFS not supported */
       
   231 	mac->adaptive_ifs = false;
       
   232 
       
   233 	/* check for link */
       
   234 	switch (hw->phy.media_type) {
       
   235 	case e1000_media_type_copper:
       
   236 		func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
       
   237 		func->check_for_link = e1000e_check_for_copper_link;
       
   238 		break;
       
   239 	case e1000_media_type_fiber:
       
   240 		func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
       
   241 		func->check_for_link = e1000e_check_for_fiber_link;
       
   242 		break;
       
   243 	case e1000_media_type_internal_serdes:
       
   244 		func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
       
   245 		func->check_for_link = e1000e_check_for_serdes_link;
       
   246 		break;
       
   247 	default:
       
   248 		return -E1000_ERR_CONFIG;
       
   249 		break;
       
   250 	}
       
   251 
       
   252 	/* set lan id for port to determine which phy lock to use */
       
   253 	hw->mac.ops.set_lan_id(hw);
       
   254 
       
   255 	return 0;
       
   256 }
       
   257 
       
   258 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
       
   259 {
       
   260 	struct e1000_hw *hw = &adapter->hw;
       
   261 	s32 rc;
       
   262 
       
   263 	rc = e1000_init_mac_params_80003es2lan(adapter);
       
   264 	if (rc)
       
   265 		return rc;
       
   266 
       
   267 	rc = e1000_init_nvm_params_80003es2lan(hw);
       
   268 	if (rc)
       
   269 		return rc;
       
   270 
       
   271 	rc = e1000_init_phy_params_80003es2lan(hw);
       
   272 	if (rc)
       
   273 		return rc;
       
   274 
       
   275 	return 0;
       
   276 }
       
   277 
       
   278 /**
       
   279  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
       
   280  *  @hw: pointer to the HW structure
       
   281  *
       
   282  *  A wrapper to acquire access rights to the correct PHY.
       
   283  **/
       
   284 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
       
   285 {
       
   286 	u16 mask;
       
   287 
       
   288 	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
       
   289 	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
       
   290 }
       
   291 
       
   292 /**
       
   293  *  e1000_release_phy_80003es2lan - Release rights to access PHY
       
   294  *  @hw: pointer to the HW structure
       
   295  *
       
   296  *  A wrapper to release access rights to the correct PHY.
       
   297  **/
       
   298 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
       
   299 {
       
   300 	u16 mask;
       
   301 
       
   302 	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
       
   303 	e1000_release_swfw_sync_80003es2lan(hw, mask);
       
   304 }
       
   305 
       
   306 /**
       
   307  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
       
   308  *  @hw: pointer to the HW structure
       
   309  *
       
   310  *  Acquire the semaphore to access the Kumeran interface.
       
   311  *
       
   312  **/
       
   313 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
       
   314 {
       
   315 	u16 mask;
       
   316 
       
   317 	mask = E1000_SWFW_CSR_SM;
       
   318 
       
   319 	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
       
   320 }
       
   321 
       
   322 /**
       
   323  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
       
   324  *  @hw: pointer to the HW structure
       
   325  *
       
   326  *  Release the semaphore used to access the Kumeran interface
       
   327  **/
       
   328 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
       
   329 {
       
   330 	u16 mask;
       
   331 
       
   332 	mask = E1000_SWFW_CSR_SM;
       
   333 
       
   334 	e1000_release_swfw_sync_80003es2lan(hw, mask);
       
   335 }
       
   336 
       
   337 /**
       
   338  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
       
   339  *  @hw: pointer to the HW structure
       
   340  *
       
   341  *  Acquire the semaphore to access the EEPROM.
       
   342  **/
       
   343 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
       
   344 {
       
   345 	s32 ret_val;
       
   346 
       
   347 	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
       
   348 	if (ret_val)
       
   349 		return ret_val;
       
   350 
       
   351 	ret_val = e1000e_acquire_nvm(hw);
       
   352 
       
   353 	if (ret_val)
       
   354 		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
       
   355 
       
   356 	return ret_val;
       
   357 }
       
   358 
       
   359 /**
       
   360  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
       
   361  *  @hw: pointer to the HW structure
       
   362  *
       
   363  *  Release the semaphore used to access the EEPROM.
       
   364  **/
       
   365 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
       
   366 {
       
   367 	e1000e_release_nvm(hw);
       
   368 	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
       
   369 }
       
   370 
       
   371 /**
       
   372  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
       
   373  *  @hw: pointer to the HW structure
       
   374  *  @mask: specifies which semaphore to acquire
       
   375  *
       
   376  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
       
   377  *  will also specify which port we're acquiring the lock for.
       
   378  **/
       
   379 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
       
   380 {
       
   381 	u32 swfw_sync;
       
   382 	u32 swmask = mask;
       
   383 	u32 fwmask = mask << 16;
       
   384 	s32 i = 0;
       
   385 	s32 timeout = 50;
       
   386 
       
   387 	while (i < timeout) {
       
   388 		if (e1000e_get_hw_semaphore(hw))
       
   389 			return -E1000_ERR_SWFW_SYNC;
       
   390 
       
   391 		swfw_sync = er32(SW_FW_SYNC);
       
   392 		if (!(swfw_sync & (fwmask | swmask)))
       
   393 			break;
       
   394 
       
   395 		/*
       
   396 		 * Firmware currently using resource (fwmask)
       
   397 		 * or other software thread using resource (swmask)
       
   398 		 */
       
   399 		e1000e_put_hw_semaphore(hw);
       
   400 		mdelay(5);
       
   401 		i++;
       
   402 	}
       
   403 
       
   404 	if (i == timeout) {
       
   405 		e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
       
   406 		return -E1000_ERR_SWFW_SYNC;
       
   407 	}
       
   408 
       
   409 	swfw_sync |= swmask;
       
   410 	ew32(SW_FW_SYNC, swfw_sync);
       
   411 
       
   412 	e1000e_put_hw_semaphore(hw);
       
   413 
       
   414 	return 0;
       
   415 }
       
   416 
       
   417 /**
       
   418  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
       
   419  *  @hw: pointer to the HW structure
       
   420  *  @mask: specifies which semaphore to acquire
       
   421  *
       
   422  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
       
   423  *  will also specify which port we're releasing the lock for.
       
   424  **/
       
   425 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
       
   426 {
       
   427 	u32 swfw_sync;
       
   428 
       
   429 	while (e1000e_get_hw_semaphore(hw) != 0);
       
   430 	/* Empty */
       
   431 
       
   432 	swfw_sync = er32(SW_FW_SYNC);
       
   433 	swfw_sync &= ~mask;
       
   434 	ew32(SW_FW_SYNC, swfw_sync);
       
   435 
       
   436 	e1000e_put_hw_semaphore(hw);
       
   437 }
       
   438 
       
   439 /**
       
   440  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
       
   441  *  @hw: pointer to the HW structure
       
   442  *  @offset: offset of the register to read
       
   443  *  @data: pointer to the data returned from the operation
       
   444  *
       
   445  *  Read the GG82563 PHY register.
       
   446  **/
       
   447 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
       
   448 						  u32 offset, u16 *data)
       
   449 {
       
   450 	s32 ret_val;
       
   451 	u32 page_select;
       
   452 	u16 temp;
       
   453 
       
   454 	ret_val = e1000_acquire_phy_80003es2lan(hw);
       
   455 	if (ret_val)
       
   456 		return ret_val;
       
   457 
       
   458 	/* Select Configuration Page */
       
   459 	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
       
   460 		page_select = GG82563_PHY_PAGE_SELECT;
       
   461 	} else {
       
   462 		/*
       
   463 		 * Use Alternative Page Select register to access
       
   464 		 * registers 30 and 31
       
   465 		 */
       
   466 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
       
   467 	}
       
   468 
       
   469 	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
       
   470 	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
       
   471 	if (ret_val) {
       
   472 		e1000_release_phy_80003es2lan(hw);
       
   473 		return ret_val;
       
   474 	}
       
   475 
       
   476 	if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
       
   477 		/*
       
   478 		 * The "ready" bit in the MDIC register may be incorrectly set
       
   479 		 * before the device has completed the "Page Select" MDI
       
   480 		 * transaction.  So we wait 200us after each MDI command...
       
   481 		 */
       
   482 		udelay(200);
       
   483 
       
   484 		/* ...and verify the command was successful. */
       
   485 		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
       
   486 
       
   487 		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
       
   488 			ret_val = -E1000_ERR_PHY;
       
   489 			e1000_release_phy_80003es2lan(hw);
       
   490 			return ret_val;
       
   491 		}
       
   492 
       
   493 		udelay(200);
       
   494 
       
   495 		ret_val = e1000e_read_phy_reg_mdic(hw,
       
   496 		                                  MAX_PHY_REG_ADDRESS & offset,
       
   497 		                                  data);
       
   498 
       
   499 		udelay(200);
       
   500 	} else {
       
   501 		ret_val = e1000e_read_phy_reg_mdic(hw,
       
   502 		                                  MAX_PHY_REG_ADDRESS & offset,
       
   503 		                                  data);
       
   504 	}
       
   505 
       
   506 	e1000_release_phy_80003es2lan(hw);
       
   507 
       
   508 	return ret_val;
       
   509 }
       
   510 
       
   511 /**
       
   512  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
       
   513  *  @hw: pointer to the HW structure
       
   514  *  @offset: offset of the register to read
       
   515  *  @data: value to write to the register
       
   516  *
       
   517  *  Write to the GG82563 PHY register.
       
   518  **/
       
   519 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
       
   520 						   u32 offset, u16 data)
       
   521 {
       
   522 	s32 ret_val;
       
   523 	u32 page_select;
       
   524 	u16 temp;
       
   525 
       
   526 	ret_val = e1000_acquire_phy_80003es2lan(hw);
       
   527 	if (ret_val)
       
   528 		return ret_val;
       
   529 
       
   530 	/* Select Configuration Page */
       
   531 	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
       
   532 		page_select = GG82563_PHY_PAGE_SELECT;
       
   533 	} else {
       
   534 		/*
       
   535 		 * Use Alternative Page Select register to access
       
   536 		 * registers 30 and 31
       
   537 		 */
       
   538 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
       
   539 	}
       
   540 
       
   541 	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
       
   542 	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
       
   543 	if (ret_val) {
       
   544 		e1000_release_phy_80003es2lan(hw);
       
   545 		return ret_val;
       
   546 	}
       
   547 
       
   548 	if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
       
   549 		/*
       
   550 		 * The "ready" bit in the MDIC register may be incorrectly set
       
   551 		 * before the device has completed the "Page Select" MDI
       
   552 		 * transaction.  So we wait 200us after each MDI command...
       
   553 		 */
       
   554 		udelay(200);
       
   555 
       
   556 		/* ...and verify the command was successful. */
       
   557 		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
       
   558 
       
   559 		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
       
   560 			e1000_release_phy_80003es2lan(hw);
       
   561 			return -E1000_ERR_PHY;
       
   562 		}
       
   563 
       
   564 		udelay(200);
       
   565 
       
   566 		ret_val = e1000e_write_phy_reg_mdic(hw,
       
   567 		                                  MAX_PHY_REG_ADDRESS & offset,
       
   568 		                                  data);
       
   569 
       
   570 		udelay(200);
       
   571 	} else {
       
   572 		ret_val = e1000e_write_phy_reg_mdic(hw,
       
   573 		                                  MAX_PHY_REG_ADDRESS & offset,
       
   574 		                                  data);
       
   575 	}
       
   576 
       
   577 	e1000_release_phy_80003es2lan(hw);
       
   578 
       
   579 	return ret_val;
       
   580 }
       
   581 
       
   582 /**
       
   583  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
       
   584  *  @hw: pointer to the HW structure
       
   585  *  @offset: offset of the register to read
       
   586  *  @words: number of words to write
       
   587  *  @data: buffer of data to write to the NVM
       
   588  *
       
   589  *  Write "words" of data to the ESB2 NVM.
       
   590  **/
       
   591 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
       
   592 				       u16 words, u16 *data)
       
   593 {
       
   594 	return e1000e_write_nvm_spi(hw, offset, words, data);
       
   595 }
       
   596 
       
   597 /**
       
   598  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
       
   599  *  @hw: pointer to the HW structure
       
   600  *
       
   601  *  Wait a specific amount of time for manageability processes to complete.
       
   602  *  This is a function pointer entry point called by the phy module.
       
   603  **/
       
   604 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
       
   605 {
       
   606 	s32 timeout = PHY_CFG_TIMEOUT;
       
   607 	u32 mask = E1000_NVM_CFG_DONE_PORT_0;
       
   608 
       
   609 	if (hw->bus.func == 1)
       
   610 		mask = E1000_NVM_CFG_DONE_PORT_1;
       
   611 
       
   612 	while (timeout) {
       
   613 		if (er32(EEMNGCTL) & mask)
       
   614 			break;
       
   615 		msleep(1);
       
   616 		timeout--;
       
   617 	}
       
   618 	if (!timeout) {
       
   619 		e_dbg("MNG configuration cycle has not completed.\n");
       
   620 		return -E1000_ERR_RESET;
       
   621 	}
       
   622 
       
   623 	return 0;
       
   624 }
       
   625 
       
   626 /**
       
   627  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
       
   628  *  @hw: pointer to the HW structure
       
   629  *
       
   630  *  Force the speed and duplex settings onto the PHY.  This is a
       
   631  *  function pointer entry point called by the phy module.
       
   632  **/
       
   633 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
       
   634 {
       
   635 	s32 ret_val;
       
   636 	u16 phy_data;
       
   637 	bool link;
       
   638 
       
   639 	/*
       
   640 	 * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
       
   641 	 * forced whenever speed and duplex are forced.
       
   642 	 */
       
   643 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
       
   644 	if (ret_val)
       
   645 		return ret_val;
       
   646 
       
   647 	phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
       
   648 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
       
   649 	if (ret_val)
       
   650 		return ret_val;
       
   651 
       
   652 	e_dbg("GG82563 PSCR: %X\n", phy_data);
       
   653 
       
   654 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
       
   655 	if (ret_val)
       
   656 		return ret_val;
       
   657 
       
   658 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
       
   659 
       
   660 	/* Reset the phy to commit changes. */
       
   661 	phy_data |= MII_CR_RESET;
       
   662 
       
   663 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
       
   664 	if (ret_val)
       
   665 		return ret_val;
       
   666 
       
   667 	udelay(1);
       
   668 
       
   669 	if (hw->phy.autoneg_wait_to_complete) {
       
   670 		e_dbg("Waiting for forced speed/duplex link "
       
   671 			 "on GG82563 phy.\n");
       
   672 
       
   673 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
       
   674 						     100000, &link);
       
   675 		if (ret_val)
       
   676 			return ret_val;
       
   677 
       
   678 		if (!link) {
       
   679 			/*
       
   680 			 * We didn't get link.
       
   681 			 * Reset the DSP and cross our fingers.
       
   682 			 */
       
   683 			ret_val = e1000e_phy_reset_dsp(hw);
       
   684 			if (ret_val)
       
   685 				return ret_val;
       
   686 		}
       
   687 
       
   688 		/* Try once more */
       
   689 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
       
   690 						     100000, &link);
       
   691 		if (ret_val)
       
   692 			return ret_val;
       
   693 	}
       
   694 
       
   695 	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
       
   696 	if (ret_val)
       
   697 		return ret_val;
       
   698 
       
   699 	/*
       
   700 	 * Resetting the phy means we need to verify the TX_CLK corresponds
       
   701 	 * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
       
   702 	 */
       
   703 	phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
       
   704 	if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
       
   705 		phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
       
   706 	else
       
   707 		phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
       
   708 
       
   709 	/*
       
   710 	 * In addition, we must re-enable CRS on Tx for both half and full
       
   711 	 * duplex.
       
   712 	 */
       
   713 	phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
       
   714 	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
       
   715 
       
   716 	return ret_val;
       
   717 }
       
   718 
       
   719 /**
       
   720  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
       
   721  *  @hw: pointer to the HW structure
       
   722  *
       
   723  *  Find the approximate cable length as measured by the GG82563 PHY.
       
   724  *  This is a function pointer entry point called by the phy module.
       
   725  **/
       
   726 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
       
   727 {
       
   728 	struct e1000_phy_info *phy = &hw->phy;
       
   729 	s32 ret_val = 0;
       
   730 	u16 phy_data, index;
       
   731 
       
   732 	ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
       
   733 	if (ret_val)
       
   734 		goto out;
       
   735 
       
   736 	index = phy_data & GG82563_DSPD_CABLE_LENGTH;
       
   737 
       
   738 	if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
       
   739 		ret_val = -E1000_ERR_PHY;
       
   740 		goto out;
       
   741 	}
       
   742 
       
   743 	phy->min_cable_length = e1000_gg82563_cable_length_table[index];
       
   744 	phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
       
   745 
       
   746 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
       
   747 
       
   748 out:
       
   749 	return ret_val;
       
   750 }
       
   751 
       
   752 /**
       
   753  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
       
   754  *  @hw: pointer to the HW structure
       
   755  *  @speed: pointer to speed buffer
       
   756  *  @duplex: pointer to duplex buffer
       
   757  *
       
   758  *  Retrieve the current speed and duplex configuration.
       
   759  **/
       
   760 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
       
   761 					      u16 *duplex)
       
   762 {
       
   763 	s32 ret_val;
       
   764 
       
   765 	if (hw->phy.media_type == e1000_media_type_copper) {
       
   766 		ret_val = e1000e_get_speed_and_duplex_copper(hw,
       
   767 								    speed,
       
   768 								    duplex);
       
   769 		hw->phy.ops.cfg_on_link_up(hw);
       
   770 	} else {
       
   771 		ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
       
   772 								  speed,
       
   773 								  duplex);
       
   774 	}
       
   775 
       
   776 	return ret_val;
       
   777 }
       
   778 
       
   779 /**
       
   780  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
       
   781  *  @hw: pointer to the HW structure
       
   782  *
       
   783  *  Perform a global reset to the ESB2 controller.
       
   784  **/
       
   785 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
       
   786 {
       
   787 	u32 ctrl, icr;
       
   788 	s32 ret_val;
       
   789 
       
   790 	/*
       
   791 	 * Prevent the PCI-E bus from sticking if there is no TLP connection
       
   792 	 * on the last TLP read/write transaction when MAC is reset.
       
   793 	 */
       
   794 	ret_val = e1000e_disable_pcie_master(hw);
       
   795 	if (ret_val)
       
   796 		e_dbg("PCI-E Master disable polling has failed.\n");
       
   797 
       
   798 	e_dbg("Masking off all interrupts\n");
       
   799 	ew32(IMC, 0xffffffff);
       
   800 
       
   801 	ew32(RCTL, 0);
       
   802 	ew32(TCTL, E1000_TCTL_PSP);
       
   803 	e1e_flush();
       
   804 
       
   805 	msleep(10);
       
   806 
       
   807 	ctrl = er32(CTRL);
       
   808 
       
   809 	ret_val = e1000_acquire_phy_80003es2lan(hw);
       
   810 	e_dbg("Issuing a global reset to MAC\n");
       
   811 	ew32(CTRL, ctrl | E1000_CTRL_RST);
       
   812 	e1000_release_phy_80003es2lan(hw);
       
   813 
       
   814 	ret_val = e1000e_get_auto_rd_done(hw);
       
   815 	if (ret_val)
       
   816 		/* We don't want to continue accessing MAC registers. */
       
   817 		return ret_val;
       
   818 
       
   819 	/* Clear any pending interrupt events. */
       
   820 	ew32(IMC, 0xffffffff);
       
   821 	icr = er32(ICR);
       
   822 
       
   823 	ret_val = e1000_check_alt_mac_addr_generic(hw);
       
   824 
       
   825 	return ret_val;
       
   826 }
       
   827 
       
   828 /**
       
   829  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
       
   830  *  @hw: pointer to the HW structure
       
   831  *
       
   832  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
       
   833  **/
       
   834 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
       
   835 {
       
   836 	struct e1000_mac_info *mac = &hw->mac;
       
   837 	u32 reg_data;
       
   838 	s32 ret_val;
       
   839 	u16 i;
       
   840 
       
   841 	e1000_initialize_hw_bits_80003es2lan(hw);
       
   842 
       
   843 	/* Initialize identification LED */
       
   844 	ret_val = e1000e_id_led_init(hw);
       
   845 	if (ret_val)
       
   846 		e_dbg("Error initializing identification LED\n");
       
   847 		/* This is not fatal and we should not stop init due to this */
       
   848 
       
   849 	/* Disabling VLAN filtering */
       
   850 	e_dbg("Initializing the IEEE VLAN\n");
       
   851 	mac->ops.clear_vfta(hw);
       
   852 
       
   853 	/* Setup the receive address. */
       
   854 	e1000e_init_rx_addrs(hw, mac->rar_entry_count);
       
   855 
       
   856 	/* Zero out the Multicast HASH table */
       
   857 	e_dbg("Zeroing the MTA\n");
       
   858 	for (i = 0; i < mac->mta_reg_count; i++)
       
   859 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
       
   860 
       
   861 	/* Setup link and flow control */
       
   862 	ret_val = e1000e_setup_link(hw);
       
   863 
       
   864 	/* Set the transmit descriptor write-back policy */
       
   865 	reg_data = er32(TXDCTL(0));
       
   866 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
       
   867 		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
       
   868 	ew32(TXDCTL(0), reg_data);
       
   869 
       
   870 	/* ...for both queues. */
       
   871 	reg_data = er32(TXDCTL(1));
       
   872 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
       
   873 		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
       
   874 	ew32(TXDCTL(1), reg_data);
       
   875 
       
   876 	/* Enable retransmit on late collisions */
       
   877 	reg_data = er32(TCTL);
       
   878 	reg_data |= E1000_TCTL_RTLC;
       
   879 	ew32(TCTL, reg_data);
       
   880 
       
   881 	/* Configure Gigabit Carry Extend Padding */
       
   882 	reg_data = er32(TCTL_EXT);
       
   883 	reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
       
   884 	reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
       
   885 	ew32(TCTL_EXT, reg_data);
       
   886 
       
   887 	/* Configure Transmit Inter-Packet Gap */
       
   888 	reg_data = er32(TIPG);
       
   889 	reg_data &= ~E1000_TIPG_IPGT_MASK;
       
   890 	reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
       
   891 	ew32(TIPG, reg_data);
       
   892 
       
   893 	reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
       
   894 	reg_data &= ~0x00100000;
       
   895 	E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
       
   896 
       
   897 	/* default to true to enable the MDIC W/A */
       
   898 	hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
       
   899 
       
   900 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
       
   901 	                              E1000_KMRNCTRLSTA_OFFSET >>
       
   902 	                              E1000_KMRNCTRLSTA_OFFSET_SHIFT,
       
   903 	                              &i);
       
   904 	if (!ret_val) {
       
   905 		if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
       
   906 		     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
       
   907 			hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
       
   908 	}
       
   909 
       
   910 	/*
       
   911 	 * Clear all of the statistics registers (clear on read).  It is
       
   912 	 * important that we do this after we have tried to establish link
       
   913 	 * because the symbol error count will increment wildly if there
       
   914 	 * is no link.
       
   915 	 */
       
   916 	e1000_clear_hw_cntrs_80003es2lan(hw);
       
   917 
       
   918 	return ret_val;
       
   919 }
       
   920 
       
   921 /**
       
   922  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
       
   923  *  @hw: pointer to the HW structure
       
   924  *
       
   925  *  Initializes required hardware-dependent bits needed for normal operation.
       
   926  **/
       
   927 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
       
   928 {
       
   929 	u32 reg;
       
   930 
       
   931 	/* Transmit Descriptor Control 0 */
       
   932 	reg = er32(TXDCTL(0));
       
   933 	reg |= (1 << 22);
       
   934 	ew32(TXDCTL(0), reg);
       
   935 
       
   936 	/* Transmit Descriptor Control 1 */
       
   937 	reg = er32(TXDCTL(1));
       
   938 	reg |= (1 << 22);
       
   939 	ew32(TXDCTL(1), reg);
       
   940 
       
   941 	/* Transmit Arbitration Control 0 */
       
   942 	reg = er32(TARC(0));
       
   943 	reg &= ~(0xF << 27); /* 30:27 */
       
   944 	if (hw->phy.media_type != e1000_media_type_copper)
       
   945 		reg &= ~(1 << 20);
       
   946 	ew32(TARC(0), reg);
       
   947 
       
   948 	/* Transmit Arbitration Control 1 */
       
   949 	reg = er32(TARC(1));
       
   950 	if (er32(TCTL) & E1000_TCTL_MULR)
       
   951 		reg &= ~(1 << 28);
       
   952 	else
       
   953 		reg |= (1 << 28);
       
   954 	ew32(TARC(1), reg);
       
   955 }
       
   956 
       
   957 /**
       
   958  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
       
   959  *  @hw: pointer to the HW structure
       
   960  *
       
   961  *  Setup some GG82563 PHY registers for obtaining link
       
   962  **/
       
   963 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
       
   964 {
       
   965 	struct e1000_phy_info *phy = &hw->phy;
       
   966 	s32 ret_val;
       
   967 	u32 ctrl_ext;
       
   968 	u16 data;
       
   969 
       
   970 	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
       
   971 	if (ret_val)
       
   972 		return ret_val;
       
   973 
       
   974 	data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
       
   975 	/* Use 25MHz for both link down and 1000Base-T for Tx clock. */
       
   976 	data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
       
   977 
       
   978 	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
       
   979 	if (ret_val)
       
   980 		return ret_val;
       
   981 
       
   982 	/*
       
   983 	 * Options:
       
   984 	 *   MDI/MDI-X = 0 (default)
       
   985 	 *   0 - Auto for all speeds
       
   986 	 *   1 - MDI mode
       
   987 	 *   2 - MDI-X mode
       
   988 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
       
   989 	 */
       
   990 	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
       
   991 	if (ret_val)
       
   992 		return ret_val;
       
   993 
       
   994 	data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
       
   995 
       
   996 	switch (phy->mdix) {
       
   997 	case 1:
       
   998 		data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
       
   999 		break;
       
  1000 	case 2:
       
  1001 		data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
       
  1002 		break;
       
  1003 	case 0:
       
  1004 	default:
       
  1005 		data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
       
  1006 		break;
       
  1007 	}
       
  1008 
       
  1009 	/*
       
  1010 	 * Options:
       
  1011 	 *   disable_polarity_correction = 0 (default)
       
  1012 	 *       Automatic Correction for Reversed Cable Polarity
       
  1013 	 *   0 - Disabled
       
  1014 	 *   1 - Enabled
       
  1015 	 */
       
  1016 	data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
       
  1017 	if (phy->disable_polarity_correction)
       
  1018 		data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
       
  1019 
       
  1020 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
       
  1021 	if (ret_val)
       
  1022 		return ret_val;
       
  1023 
       
  1024 	/* SW Reset the PHY so all changes take effect */
       
  1025 	ret_val = e1000e_commit_phy(hw);
       
  1026 	if (ret_val) {
       
  1027 		e_dbg("Error Resetting the PHY\n");
       
  1028 		return ret_val;
       
  1029 	}
       
  1030 
       
  1031 	/* Bypass Rx and Tx FIFO's */
       
  1032 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
       
  1033 					E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
       
  1034 					E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
       
  1035 					E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
       
  1036 	if (ret_val)
       
  1037 		return ret_val;
       
  1038 
       
  1039 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
       
  1040 				       E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
       
  1041 				       &data);
       
  1042 	if (ret_val)
       
  1043 		return ret_val;
       
  1044 	data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
       
  1045 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
       
  1046 					E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
       
  1047 					data);
       
  1048 	if (ret_val)
       
  1049 		return ret_val;
       
  1050 
       
  1051 	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
       
  1052 	if (ret_val)
       
  1053 		return ret_val;
       
  1054 
       
  1055 	data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
       
  1056 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
       
  1057 	if (ret_val)
       
  1058 		return ret_val;
       
  1059 
       
  1060 	ctrl_ext = er32(CTRL_EXT);
       
  1061 	ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
       
  1062 	ew32(CTRL_EXT, ctrl_ext);
       
  1063 
       
  1064 	ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
       
  1065 	if (ret_val)
       
  1066 		return ret_val;
       
  1067 
       
  1068 	/*
       
  1069 	 * Do not init these registers when the HW is in IAMT mode, since the
       
  1070 	 * firmware will have already initialized them.  We only initialize
       
  1071 	 * them if the HW is not in IAMT mode.
       
  1072 	 */
       
  1073 	if (!e1000e_check_mng_mode(hw)) {
       
  1074 		/* Enable Electrical Idle on the PHY */
       
  1075 		data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
       
  1076 		ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
       
  1077 		if (ret_val)
       
  1078 			return ret_val;
       
  1079 
       
  1080 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
       
  1081 		if (ret_val)
       
  1082 			return ret_val;
       
  1083 
       
  1084 		data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
       
  1085 		ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
       
  1086 		if (ret_val)
       
  1087 			return ret_val;
       
  1088 	}
       
  1089 
       
  1090 	/*
       
  1091 	 * Workaround: Disable padding in Kumeran interface in the MAC
       
  1092 	 * and in the PHY to avoid CRC errors.
       
  1093 	 */
       
  1094 	ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
       
  1095 	if (ret_val)
       
  1096 		return ret_val;
       
  1097 
       
  1098 	data |= GG82563_ICR_DIS_PADDING;
       
  1099 	ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
       
  1100 	if (ret_val)
       
  1101 		return ret_val;
       
  1102 
       
  1103 	return 0;
       
  1104 }
       
  1105 
       
  1106 /**
       
  1107  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
       
  1108  *  @hw: pointer to the HW structure
       
  1109  *
       
  1110  *  Essentially a wrapper for setting up all things "copper" related.
       
  1111  *  This is a function pointer entry point called by the mac module.
       
  1112  **/
       
  1113 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
       
  1114 {
       
  1115 	u32 ctrl;
       
  1116 	s32 ret_val;
       
  1117 	u16 reg_data;
       
  1118 
       
  1119 	ctrl = er32(CTRL);
       
  1120 	ctrl |= E1000_CTRL_SLU;
       
  1121 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
       
  1122 	ew32(CTRL, ctrl);
       
  1123 
       
  1124 	/*
       
  1125 	 * Set the mac to wait the maximum time between each
       
  1126 	 * iteration and increase the max iterations when
       
  1127 	 * polling the phy; this fixes erroneous timeouts at 10Mbps.
       
  1128 	 */
       
  1129 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
       
  1130 	                                           0xFFFF);
       
  1131 	if (ret_val)
       
  1132 		return ret_val;
       
  1133 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
       
  1134 	                                          &reg_data);
       
  1135 	if (ret_val)
       
  1136 		return ret_val;
       
  1137 	reg_data |= 0x3F;
       
  1138 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
       
  1139 	                                           reg_data);
       
  1140 	if (ret_val)
       
  1141 		return ret_val;
       
  1142 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
       
  1143 				      E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
       
  1144 				      &reg_data);
       
  1145 	if (ret_val)
       
  1146 		return ret_val;
       
  1147 	reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
       
  1148 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
       
  1149 					E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
       
  1150 					reg_data);
       
  1151 	if (ret_val)
       
  1152 		return ret_val;
       
  1153 
       
  1154 	ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
       
  1155 	if (ret_val)
       
  1156 		return ret_val;
       
  1157 
       
  1158 	ret_val = e1000e_setup_copper_link(hw);
       
  1159 
       
  1160 	return 0;
       
  1161 }
       
  1162 
       
  1163 /**
       
  1164  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
       
  1165  *  @hw: pointer to the HW structure
       
  1166  *  @duplex: current duplex setting
       
  1167  *
       
  1168  *  Configure the KMRN interface by applying last minute quirks for
       
  1169  *  10/100 operation.
       
  1170  **/
       
  1171 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
       
  1172 {
       
  1173 	s32 ret_val = 0;
       
  1174 	u16 speed;
       
  1175 	u16 duplex;
       
  1176 
       
  1177 	if (hw->phy.media_type == e1000_media_type_copper) {
       
  1178 		ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
       
  1179 		                                             &duplex);
       
  1180 		if (ret_val)
       
  1181 			return ret_val;
       
  1182 
       
  1183 		if (speed == SPEED_1000)
       
  1184 			ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
       
  1185 		else
       
  1186 			ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
       
  1187 	}
       
  1188 
       
  1189 	return ret_val;
       
  1190 }
       
  1191 
       
  1192 /**
       
  1193  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
       
  1194  *  @hw: pointer to the HW structure
       
  1195  *  @duplex: current duplex setting
       
  1196  *
       
  1197  *  Configure the KMRN interface by applying last minute quirks for
       
  1198  *  10/100 operation.
       
  1199  **/
       
  1200 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
       
  1201 {
       
  1202 	s32 ret_val;
       
  1203 	u32 tipg;
       
  1204 	u32 i = 0;
       
  1205 	u16 reg_data, reg_data2;
       
  1206 
       
  1207 	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
       
  1208 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
       
  1209 	                               E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
       
  1210 	                               reg_data);
       
  1211 	if (ret_val)
       
  1212 		return ret_val;
       
  1213 
       
  1214 	/* Configure Transmit Inter-Packet Gap */
       
  1215 	tipg = er32(TIPG);
       
  1216 	tipg &= ~E1000_TIPG_IPGT_MASK;
       
  1217 	tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
       
  1218 	ew32(TIPG, tipg);
       
  1219 
       
  1220 	do {
       
  1221 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
       
  1222 		if (ret_val)
       
  1223 			return ret_val;
       
  1224 
       
  1225 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
       
  1226 		if (ret_val)
       
  1227 			return ret_val;
       
  1228 		i++;
       
  1229 	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
       
  1230 
       
  1231 	if (duplex == HALF_DUPLEX)
       
  1232 		reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
       
  1233 	else
       
  1234 		reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
       
  1235 
       
  1236 	ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
       
  1237 
       
  1238 	return 0;
       
  1239 }
       
  1240 
       
  1241 /**
       
  1242  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
       
  1243  *  @hw: pointer to the HW structure
       
  1244  *
       
  1245  *  Configure the KMRN interface by applying last minute quirks for
       
  1246  *  gigabit operation.
       
  1247  **/
       
  1248 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
       
  1249 {
       
  1250 	s32 ret_val;
       
  1251 	u16 reg_data, reg_data2;
       
  1252 	u32 tipg;
       
  1253 	u32 i = 0;
       
  1254 
       
  1255 	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
       
  1256 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
       
  1257 	                               E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
       
  1258 	                               reg_data);
       
  1259 	if (ret_val)
       
  1260 		return ret_val;
       
  1261 
       
  1262 	/* Configure Transmit Inter-Packet Gap */
       
  1263 	tipg = er32(TIPG);
       
  1264 	tipg &= ~E1000_TIPG_IPGT_MASK;
       
  1265 	tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
       
  1266 	ew32(TIPG, tipg);
       
  1267 
       
  1268 	do {
       
  1269 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
       
  1270 		if (ret_val)
       
  1271 			return ret_val;
       
  1272 
       
  1273 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
       
  1274 		if (ret_val)
       
  1275 			return ret_val;
       
  1276 		i++;
       
  1277 	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
       
  1278 
       
  1279 	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
       
  1280 	ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
       
  1281 
       
  1282 	return ret_val;
       
  1283 }
       
  1284 
       
  1285 /**
       
  1286  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
       
  1287  *  @hw: pointer to the HW structure
       
  1288  *  @offset: register offset to be read
       
  1289  *  @data: pointer to the read data
       
  1290  *
       
  1291  *  Acquire semaphore, then read the PHY register at offset
       
  1292  *  using the kumeran interface.  The information retrieved is stored in data.
       
  1293  *  Release the semaphore before exiting.
       
  1294  **/
       
  1295 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
       
  1296 					   u16 *data)
       
  1297 {
       
  1298 	u32 kmrnctrlsta;
       
  1299 	s32 ret_val = 0;
       
  1300 
       
  1301 	ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
       
  1302 	if (ret_val)
       
  1303 		return ret_val;
       
  1304 
       
  1305 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
       
  1306 	               E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
       
  1307 	ew32(KMRNCTRLSTA, kmrnctrlsta);
       
  1308 
       
  1309 	udelay(2);
       
  1310 
       
  1311 	kmrnctrlsta = er32(KMRNCTRLSTA);
       
  1312 	*data = (u16)kmrnctrlsta;
       
  1313 
       
  1314 	e1000_release_mac_csr_80003es2lan(hw);
       
  1315 
       
  1316 	return ret_val;
       
  1317 }
       
  1318 
       
  1319 /**
       
  1320  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
       
  1321  *  @hw: pointer to the HW structure
       
  1322  *  @offset: register offset to write to
       
  1323  *  @data: data to write at register offset
       
  1324  *
       
  1325  *  Acquire semaphore, then write the data to PHY register
       
  1326  *  at the offset using the kumeran interface.  Release semaphore
       
  1327  *  before exiting.
       
  1328  **/
       
  1329 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
       
  1330 					    u16 data)
       
  1331 {
       
  1332 	u32 kmrnctrlsta;
       
  1333 	s32 ret_val = 0;
       
  1334 
       
  1335 	ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
       
  1336 	if (ret_val)
       
  1337 		return ret_val;
       
  1338 
       
  1339 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
       
  1340 	               E1000_KMRNCTRLSTA_OFFSET) | data;
       
  1341 	ew32(KMRNCTRLSTA, kmrnctrlsta);
       
  1342 
       
  1343 	udelay(2);
       
  1344 
       
  1345 	e1000_release_mac_csr_80003es2lan(hw);
       
  1346 
       
  1347 	return ret_val;
       
  1348 }
       
  1349 
       
  1350 /**
       
  1351  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
       
  1352  *  @hw: pointer to the HW structure
       
  1353  **/
       
  1354 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
       
  1355 {
       
  1356 	s32 ret_val = 0;
       
  1357 
       
  1358 	/*
       
  1359 	 * If there's an alternate MAC address place it in RAR0
       
  1360 	 * so that it will override the Si installed default perm
       
  1361 	 * address.
       
  1362 	 */
       
  1363 	ret_val = e1000_check_alt_mac_addr_generic(hw);
       
  1364 	if (ret_val)
       
  1365 		goto out;
       
  1366 
       
  1367 	ret_val = e1000_read_mac_addr_generic(hw);
       
  1368 
       
  1369 out:
       
  1370 	return ret_val;
       
  1371 }
       
  1372 
       
  1373 /**
       
  1374  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
       
  1375  * @hw: pointer to the HW structure
       
  1376  *
       
  1377  * In the case of a PHY power down to save power, or to turn off link during a
       
  1378  * driver unload, or wake on lan is not enabled, remove the link.
       
  1379  **/
       
  1380 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
       
  1381 {
       
  1382 	/* If the management interface is not enabled, then power down */
       
  1383 	if (!(hw->mac.ops.check_mng_mode(hw) ||
       
  1384 	      hw->phy.ops.check_reset_block(hw)))
       
  1385 		e1000_power_down_phy_copper(hw);
       
  1386 }
       
  1387 
       
  1388 /**
       
  1389  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
       
  1390  *  @hw: pointer to the HW structure
       
  1391  *
       
  1392  *  Clears the hardware counters by reading the counter registers.
       
  1393  **/
       
  1394 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
       
  1395 {
       
  1396 	e1000e_clear_hw_cntrs_base(hw);
       
  1397 
       
  1398 	er32(PRC64);
       
  1399 	er32(PRC127);
       
  1400 	er32(PRC255);
       
  1401 	er32(PRC511);
       
  1402 	er32(PRC1023);
       
  1403 	er32(PRC1522);
       
  1404 	er32(PTC64);
       
  1405 	er32(PTC127);
       
  1406 	er32(PTC255);
       
  1407 	er32(PTC511);
       
  1408 	er32(PTC1023);
       
  1409 	er32(PTC1522);
       
  1410 
       
  1411 	er32(ALGNERRC);
       
  1412 	er32(RXERRC);
       
  1413 	er32(TNCRS);
       
  1414 	er32(CEXTERR);
       
  1415 	er32(TSCTC);
       
  1416 	er32(TSCTFC);
       
  1417 
       
  1418 	er32(MGTPRC);
       
  1419 	er32(MGTPDC);
       
  1420 	er32(MGTPTC);
       
  1421 
       
  1422 	er32(IAC);
       
  1423 	er32(ICRXOC);
       
  1424 
       
  1425 	er32(ICRXPTC);
       
  1426 	er32(ICRXATC);
       
  1427 	er32(ICTXPTC);
       
  1428 	er32(ICTXATC);
       
  1429 	er32(ICTXQEC);
       
  1430 	er32(ICTXQMTC);
       
  1431 	er32(ICRXDMTC);
       
  1432 }
       
  1433 
       
  1434 static struct e1000_mac_operations es2_mac_ops = {
       
  1435 	.read_mac_addr		= e1000_read_mac_addr_80003es2lan,
       
  1436 	.id_led_init		= e1000e_id_led_init,
       
  1437 	.check_mng_mode		= e1000e_check_mng_mode_generic,
       
  1438 	/* check_for_link dependent on media type */
       
  1439 	.cleanup_led		= e1000e_cleanup_led_generic,
       
  1440 	.clear_hw_cntrs		= e1000_clear_hw_cntrs_80003es2lan,
       
  1441 	.get_bus_info		= e1000e_get_bus_info_pcie,
       
  1442 	.set_lan_id		= e1000_set_lan_id_multi_port_pcie,
       
  1443 	.get_link_up_info	= e1000_get_link_up_info_80003es2lan,
       
  1444 	.led_on			= e1000e_led_on_generic,
       
  1445 	.led_off		= e1000e_led_off_generic,
       
  1446 	.update_mc_addr_list	= e1000e_update_mc_addr_list_generic,
       
  1447 	.write_vfta		= e1000_write_vfta_generic,
       
  1448 	.clear_vfta		= e1000_clear_vfta_generic,
       
  1449 	.reset_hw		= e1000_reset_hw_80003es2lan,
       
  1450 	.init_hw		= e1000_init_hw_80003es2lan,
       
  1451 	.setup_link		= e1000e_setup_link,
       
  1452 	/* setup_physical_interface dependent on media type */
       
  1453 	.setup_led		= e1000e_setup_led_generic,
       
  1454 };
       
  1455 
       
  1456 static struct e1000_phy_operations es2_phy_ops = {
       
  1457 	.acquire		= e1000_acquire_phy_80003es2lan,
       
  1458 	.check_polarity		= e1000_check_polarity_m88,
       
  1459 	.check_reset_block	= e1000e_check_reset_block_generic,
       
  1460 	.commit		 	= e1000e_phy_sw_reset,
       
  1461 	.force_speed_duplex 	= e1000_phy_force_speed_duplex_80003es2lan,
       
  1462 	.get_cfg_done       	= e1000_get_cfg_done_80003es2lan,
       
  1463 	.get_cable_length   	= e1000_get_cable_length_80003es2lan,
       
  1464 	.get_info       	= e1000e_get_phy_info_m88,
       
  1465 	.read_reg       	= e1000_read_phy_reg_gg82563_80003es2lan,
       
  1466 	.release		= e1000_release_phy_80003es2lan,
       
  1467 	.reset		  	= e1000e_phy_hw_reset_generic,
       
  1468 	.set_d0_lplu_state  	= NULL,
       
  1469 	.set_d3_lplu_state  	= e1000e_set_d3_lplu_state,
       
  1470 	.write_reg      	= e1000_write_phy_reg_gg82563_80003es2lan,
       
  1471 	.cfg_on_link_up      	= e1000_cfg_on_link_up_80003es2lan,
       
  1472 };
       
  1473 
       
  1474 static struct e1000_nvm_operations es2_nvm_ops = {
       
  1475 	.acquire		= e1000_acquire_nvm_80003es2lan,
       
  1476 	.read			= e1000e_read_nvm_eerd,
       
  1477 	.release		= e1000_release_nvm_80003es2lan,
       
  1478 	.update			= e1000e_update_nvm_checksum_generic,
       
  1479 	.valid_led_default	= e1000e_valid_led_default,
       
  1480 	.validate		= e1000e_validate_nvm_checksum_generic,
       
  1481 	.write			= e1000_write_nvm_80003es2lan,
       
  1482 };
       
  1483 
       
  1484 struct e1000_info e1000_es2_info = {
       
  1485 	.mac			= e1000_80003es2lan,
       
  1486 	.flags			= FLAG_HAS_HW_VLAN_FILTER
       
  1487 				  | FLAG_HAS_JUMBO_FRAMES
       
  1488 				  | FLAG_HAS_WOL
       
  1489 				  | FLAG_APME_IN_CTRL3
       
  1490 				  | FLAG_RX_CSUM_ENABLED
       
  1491 				  | FLAG_HAS_CTRLEXT_ON_LOAD
       
  1492 				  | FLAG_RX_NEEDS_RESTART /* errata */
       
  1493 				  | FLAG_TARC_SET_BIT_ZERO /* errata */
       
  1494 				  | FLAG_APME_CHECK_PORT_B
       
  1495 				  | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
       
  1496 				  | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
       
  1497 	.flags2			= FLAG2_DMA_BURST,
       
  1498 	.pba			= 38,
       
  1499 	.max_hw_frame_size	= DEFAULT_JUMBO,
       
  1500 	.get_variants		= e1000_get_variants_80003es2lan,
       
  1501 	.mac_ops		= &es2_mac_ops,
       
  1502 	.phy_ops		= &es2_phy_ops,
       
  1503 	.nvm_ops		= &es2_nvm_ops,
       
  1504 };
       
  1505