1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it

    10  *  and/or modify it under the terms of the GNU General Public License

    11  *  as published by the Free Software Foundation; either version 2 of the

    12  *  License, or (at your option) any later version.

    13  *

    14  *  The IgH EtherCAT Master is distributed in the hope that it will be

    15  *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  *  GNU General Public License for more details.

    18  *

    19  *  You should have received a copy of the GNU General Public License

    20  *  along with the IgH EtherCAT Master; if not, write to the Free Software

    21  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    22  *

    23  *  The right to use EtherCAT Technology is granted and comes free of

    24  *  charge under condition of compatibility of product made by

    25  *  Licensee. People intending to distribute/sell products based on the

    26  *  code, have to sign an agreement to guarantee that products using

    27  *  software based on IgH EtherCAT master stay compatible with the actual

    28  *  EtherCAT specification (which are released themselves as an open

    29  *  standard) as the (only) precondition to have the right to use EtherCAT

    30  *  Technology, IP and trade marks.

    31  *

    32  *****************************************************************************/

    33 

    34 /**

    35    \file

    36    EtherCAT driver for RTL8139-compatible NICs.

    37 */

    38 

    39 /*****************************************************************************/

    40 

    41 /*

    42   Former documentation:

    43 

    44 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    45 

    46 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    47 	Copyright 2000-2002 Jeff Garzik

    48 

    49 	Much code comes from Donald Becker's rtl8139.c driver,

    50 	versions 1.13 and older.  This driver was originally based

    51 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    52 

    53 	-----<snip>-----

    54 

    55         	Written 1997-2001 by Donald Becker.

    56 		This software may be used and distributed according to the

    57 		terms of the GNU General Public License (GPL), incorporated

    58 		herein by reference.  Drivers based on or derived from this

    59 		code fall under the GPL and must retain the authorship,

    60 		copyright and license notice.  This file is not a complete

    61 		program and may only be used when the entire operating

    62 		system is licensed under the GPL.

    63 

    64 		This driver is for boards based on the RTL8129 and RTL8139

    65 		PCI ethernet chips.

    66 

    67 		The author may be reached as becker@scyld.com, or C/O Scyld

    68 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    69 		MD 21403

    70 

    71 		Support and updates available at

    72 		http://www.scyld.com/network/rtl8139.html

    73 

    74 		Twister-tuning table provided by Kinston

    75 		<shangh@realtek.com.tw>.

    76 

    77 	-----<snip>-----

    78 

    79 	This software may be used and distributed according to the terms

    80 	of the GNU General Public License, incorporated herein by reference.

    81 

    82 	Contributors:

    83 

    84 		Donald Becker - he wrote the original driver, kudos to him!

    85 		(but please don't e-mail him for support, this isn't his driver)

    86 

    87 		Tigran Aivazian - bug fixes, skbuff free cleanup

    88 

    89 		Martin Mares - suggestions for PCI cleanup

    90 

    91 		David S. Miller - PCI DMA and softnet updates

    92 

    93 		Ernst Gill - fixes ported from BSD driver

    94 

    95 		Daniel Kobras - identified specific locations of

    96 			posted MMIO write bugginess

    97 

    98 		Gerard Sharp - bug fix, testing and feedback

    99 

   100 		David Ford - Rx ring wrap fix

   101 

   102 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

   103 		to find and fix a crucial bug on older chipsets.

   104 

   105 		Donald Becker/Chris Butterworth/Marcus Westergren -

   106 		Noticed various Rx packet size-related buglets.

   107 

   108 		Santiago Garcia Mantinan - testing and feedback

   109 

   110 		Jens David - 2.2.x kernel backports

   111 

   112 		Martin Dennett - incredibly helpful insight on undocumented

   113 		features of the 8139 chips

   114 

   115 		Jean-Jacques Michel - bug fix

   116 

   117 		Tobias Ringström - Rx interrupt status checking suggestion

   118 

   119 		Andrew Morton - Clear blocked signals, avoid

   120 		buffer overrun setting current->comm.

   121 

   122 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   123 

   124 		Robert Kuebel - Save kernel thread from dying on any signal.

   125 

   126 	Submitting bug reports:

   127 

   128 		"rtl8139-diag -mmmaaavvveefN" output

   129 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   130 

   131 */

   132 

   133 #define DRV_NAME	"ec_8139too"

   134 #define DRV_VERSION	"0.9.28"

   135 

   136 

   137 #include <linux/module.h>

   138 #include <linux/kernel.h>

   139 #include <linux/compiler.h>

   140 #include <linux/pci.h>

   141 #include <linux/init.h>

   142 #include <linux/ioport.h>

   143 #include <linux/netdevice.h>

   144 #include <linux/etherdevice.h>

   145 #include <linux/rtnetlink.h>

   146 #include <linux/delay.h>

   147 #include <linux/ethtool.h>

   148 #include <linux/mii.h>

   149 #include <linux/completion.h>

   150 #include <linux/crc32.h>

   151 #include <asm/io.h>

   152 #include <asm/uaccess.h>

   153 #include <asm/irq.h>

   154 

   155 #include "../globals.h"

   156 #include "ecdev.h"

   157 

   158 #define RTL8139_DRIVER_NAME DRV_NAME \

   159                             " EtherCAT-capable Fast Ethernet driver " \

   160                             DRV_VERSION ", master " EC_MASTER_VERSION

   161 

   162 #define PFX DRV_NAME ": "

   163 

   164 /* Default Message level */

   165 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   166                                  NETIF_MSG_PROBE  | \

   167                                  NETIF_MSG_LINK)

   168 

   169 

   170 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   171 #ifdef CONFIG_8139TOO_PIO

   172 #define USE_IO_OPS 1

   173 #endif

   174 

   175 /* define to 1, 2 or 3 to enable copious debugging info */

   176 #define RTL8139_DEBUG 0

   177 

   178 /* define to 1 to disable lightweight runtime debugging checks */

   179 #undef RTL8139_NDEBUG

   180 

   181 

   182 #if RTL8139_DEBUG

   183 /* note: prints function name for you */

   184 #  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   185 #else

   186 #  define DPRINTK(fmt, args...)

   187 #endif

   188 

   189 #ifdef RTL8139_NDEBUG

   190 #  define assert(expr) do {} while (0)

   191 #else

   192 #  define assert(expr) \

   193         if(unlikely(!(expr))) {				        \

   194         printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   195         #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   196         }

   197 #endif

   198 

   199 

   200 /* A few user-configurable values. */

   201 /* media options */

   202 #define MAX_UNITS 8

   203 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   204 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   205 

   206 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   207    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   208 static int multicast_filter_limit = 32;

   209 

   210 /* bitmapped message enable number */

   211 static int debug = -1;

   212 

   213 /*

   214  * Receive ring size

   215  * Warning: 64K ring has hardware issues and may lock up.

   216  */

   217 #if defined(CONFIG_SH_DREAMCAST)

   218 #define RX_BUF_IDX 0	/* 8K ring */

   219 #else

   220 #define RX_BUF_IDX	2	/* 32K ring */

   221 #endif

   222 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   223 #define RX_BUF_PAD	16

   224 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   225 

   226 #if RX_BUF_LEN == 65536

   227 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   228 #else

   229 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   230 #endif

   231 

   232 /* Number of Tx descriptor registers. */

   233 #define NUM_TX_DESC	4

   234 

   235 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   236 #define MAX_ETH_FRAME_SIZE	1536

   237 

   238 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   239 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   240 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   241 

   242 /* PCI Tuning Parameters

   243    Threshold is bytes transferred to chip before transmission starts. */

   244 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   245 

   246 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   247 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   248 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   249 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   250 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   251 

   252 /* Operational parameters that usually are not changed. */

   253 /* Time in jiffies before concluding the transmitter is hung. */

   254 #define TX_TIMEOUT  (6*HZ)

   255 

   256 

   257 enum {

   258 	HAS_MII_XCVR = 0x010000,

   259 	HAS_CHIP_XCVR = 0x020000,

   260 	HAS_LNK_CHNG = 0x040000,

   261 };

   262 

   263 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   264 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   265 #define RTL_MIN_IO_SIZE 0x80

   266 #define RTL8139B_IO_SIZE 256

   267 

   268 #define RTL8129_CAPS	HAS_MII_XCVR

   269 #define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   270 

   271 typedef enum {

   272 	RTL8139 = 0,

   273 	RTL8129,

   274 } board_t;

   275 

   276 

   277 /* indexed by board_t, above */

   278 static const struct {

   279 	const char *name;

   280 	u32 hw_flags;

   281 } board_info[] __devinitdata = {

   282 	{ "RealTek RTL8139", RTL8139_CAPS },

   283 	{ "RealTek RTL8129", RTL8129_CAPS },

   284 };

   285 

   286 

   287 static struct pci_device_id rtl8139_pci_tbl[] = {

   288 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   302 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   305 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   306 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307 

   308 #ifdef CONFIG_SH_SECUREEDGE5410

   309 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   310 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   311 #endif

   312 #ifdef CONFIG_8139TOO_8129

   313 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   314 #endif

   315 

   316 	/* some crazy cards report invalid vendor ids like

   317 	 * 0x0001 here.  The other ids are valid and constant,

   318 	 * so we simply don't match on the main vendor id.

   319 	 */

   320 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   321 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   322 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   323 

   324 	{0,}

   325 };

   326 

   327 /* prevent driver from being loaded automatically */

   328 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   329 

   330 static struct {

   331 	const char str[ETH_GSTRING_LEN];

   332 } ethtool_stats_keys[] = {

   333 	{ "early_rx" },

   334 	{ "tx_buf_mapped" },

   335 	{ "tx_timeouts" },

   336 	{ "rx_lost_in_ring" },

   337 };

   338 

   339 /* The rest of these values should never change. */

   340 

   341 /* Symbolic offsets to registers. */

   342 enum RTL8139_registers {

   343 	MAC0		= 0,	 /* Ethernet hardware address. */

   344 	MAR0		= 8,	 /* Multicast filter. */

   345 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   346 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   347 	RxBuf		= 0x30,

   348 	ChipCmd		= 0x37,

   349 	RxBufPtr	= 0x38,

   350 	RxBufAddr	= 0x3A,

   351 	IntrMask	= 0x3C,

   352 	IntrStatus	= 0x3E,

   353 	TxConfig	= 0x40,

   354 	RxConfig	= 0x44,

   355 	Timer		= 0x48,	 /* A general-purpose counter. */

   356 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   357 	Cfg9346		= 0x50,

   358 	Config0		= 0x51,

   359 	Config1		= 0x52,

   360 	FlashReg	= 0x54,

   361 	MediaStatus	= 0x58,

   362 	Config3		= 0x59,

   363 	Config4		= 0x5A,	 /* absent on RTL-8139A */

   364 	HltClk		= 0x5B,

   365 	MultiIntr	= 0x5C,

   366 	TxSummary	= 0x60,

   367 	BasicModeCtrl	= 0x62,

   368 	BasicModeStatus	= 0x64,

   369 	NWayAdvert	= 0x66,

   370 	NWayLPAR	= 0x68,

   371 	NWayExpansion	= 0x6A,

   372 	/* Undocumented registers, but required for proper operation. */

   373 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   374 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   375 	PARA78		= 0x78,

   376 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   377 	Config5		= 0xD8,	 /* absent on RTL-8139A */

   378 };

   379 

   380 enum ClearBitMasks {

   381 	MultiIntrClear	= 0xF000,

   382 	ChipCmdClear	= 0xE2,

   383 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   384 };

   385 

   386 enum ChipCmdBits {

   387 	CmdReset	= 0x10,

   388 	CmdRxEnb	= 0x08,

   389 	CmdTxEnb	= 0x04,

   390 	RxBufEmpty	= 0x01,

   391 };

   392 

   393 /* Interrupt register bits, using my own meaningful names. */

   394 enum IntrStatusBits {

   395 	PCIErr		= 0x8000,

   396 	PCSTimeout	= 0x4000,

   397 	RxFIFOOver	= 0x40,

   398 	RxUnderrun	= 0x20,

   399 	RxOverflow	= 0x10,

   400 	TxErr		= 0x08,

   401 	TxOK		= 0x04,

   402 	RxErr		= 0x02,

   403 	RxOK		= 0x01,

   404 

   405 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   406 };

   407 

   408 enum TxStatusBits {

   409 	TxHostOwns	= 0x2000,

   410 	TxUnderrun	= 0x4000,

   411 	TxStatOK	= 0x8000,

   412 	TxOutOfWindow	= 0x20000000,

   413 	TxAborted	= 0x40000000,

   414 	TxCarrierLost	= 0x80000000,

   415 };

   416 enum RxStatusBits {

   417 	RxMulticast	= 0x8000,

   418 	RxPhysical	= 0x4000,

   419 	RxBroadcast	= 0x2000,

   420 	RxBadSymbol	= 0x0020,

   421 	RxRunt		= 0x0010,

   422 	RxTooLong	= 0x0008,

   423 	RxCRCErr	= 0x0004,

   424 	RxBadAlign	= 0x0002,

   425 	RxStatusOK	= 0x0001,

   426 };

   427 

   428 /* Bits in RxConfig. */

   429 enum rx_mode_bits {

   430 	AcceptErr	= 0x20,

   431 	AcceptRunt	= 0x10,

   432 	AcceptBroadcast	= 0x08,

   433 	AcceptMulticast	= 0x04,

   434 	AcceptMyPhys	= 0x02,

   435 	AcceptAllPhys	= 0x01,

   436 };

   437 

   438 /* Bits in TxConfig. */

   439 enum tx_config_bits {

   440         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   441         TxIFGShift	= 24,

   442         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   443         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   444         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   445         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   446 

   447 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   448 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   449 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   450 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   451 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   452 

   453 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   454 };

   455 

   456 /* Bits in Config1 */

   457 enum Config1Bits {

   458 	Cfg1_PM_Enable	= 0x01,

   459 	Cfg1_VPD_Enable	= 0x02,

   460 	Cfg1_PIO	= 0x04,

   461 	Cfg1_MMIO	= 0x08,

   462 	LWAKE		= 0x10,		/* not on 8139, 8139A */

   463 	Cfg1_Driver_Load = 0x20,

   464 	Cfg1_LED0	= 0x40,

   465 	Cfg1_LED1	= 0x80,

   466 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   467 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   468 };

   469 

   470 /* Bits in Config3 */

   471 enum Config3Bits {

   472 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   473 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   474 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   475 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   476 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   477 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   478 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   479 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   480 };

   481 

   482 /* Bits in Config4 */

   483 enum Config4Bits {

   484 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   485 };

   486 

   487 /* Bits in Config5 */

   488 enum Config5Bits {

   489 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   490 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   491 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   492 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   493 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   494 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   495 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   496 };

   497 

   498 enum RxConfigBits {

   499 	/* rx fifo threshold */

   500 	RxCfgFIFOShift	= 13,

   501 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   502 

   503 	/* Max DMA burst */

   504 	RxCfgDMAShift	= 8,

   505 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   506 

   507 	/* rx ring buffer length */

   508 	RxCfgRcv8K	= 0,

   509 	RxCfgRcv16K	= (1 << 11),

   510 	RxCfgRcv32K	= (1 << 12),

   511 	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   512 

   513 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   514 	RxNoWrap	= (1 << 7),

   515 };

   516 

   517 /* Twister tuning parameters from RealTek.

   518    Completely undocumented, but required to tune bad links on some boards. */

   519 enum CSCRBits {

   520 	CSCR_LinkOKBit		= 0x0400,

   521 	CSCR_LinkChangeBit	= 0x0800,

   522 	CSCR_LinkStatusBits	= 0x0f000,

   523 	CSCR_LinkDownOffCmd	= 0x003c0,

   524 	CSCR_LinkDownCmd	= 0x0f3c0,

   525 };

   526 

   527 enum Cfg9346Bits {

   528 	Cfg9346_Lock	= 0x00,

   529 	Cfg9346_Unlock	= 0xC0,

   530 };

   531 

   532 typedef enum {

   533 	CH_8139	= 0,

   534 	CH_8139_K,

   535 	CH_8139A,

   536 	CH_8139A_G,

   537 	CH_8139B,

   538 	CH_8130,

   539 	CH_8139C,

   540 	CH_8100,

   541 	CH_8100B_8139D,

   542 	CH_8101,

   543 } chip_t;

   544 

   545 enum chip_flags {

   546 	HasHltClk	= (1 << 0),

   547 	HasLWake	= (1 << 1),

   548 };

   549 

   550 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   551 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   552 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   553 

   554 /* directly indexed by chip_t, above */

   555 static const struct {

   556 	const char *name;

   557 	u32 version; /* from RTL8139C/RTL8139D docs */

   558 	u32 flags;

   559 } rtl_chip_info[] = {

   560 	{ "RTL-8139",

   561 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   562 	  HasHltClk,

   563 	},

   564 

   565 	{ "RTL-8139 rev K",

   566 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   567 	  HasHltClk,

   568 	},

   569 

   570 	{ "RTL-8139A",

   571 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   572 	  HasHltClk, /* XXX undocumented? */

   573 	},

   574 

   575 	{ "RTL-8139A rev G",

   576 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   577 	  HasHltClk, /* XXX undocumented? */

   578 	},

   579 

   580 	{ "RTL-8139B",

   581 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   582 	  HasLWake,

   583 	},

   584 

   585 	{ "RTL-8130",

   586 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   587 	  HasLWake,

   588 	},

   589 

   590 	{ "RTL-8139C",

   591 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   592 	  HasLWake,

   593 	},

   594 

   595 	{ "RTL-8100",

   596 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   597  	  HasLWake,

   598  	},

   599 

   600 	{ "RTL-8100B/8139D",

   601 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   602 	  HasHltClk /* XXX undocumented? */

   603 	| HasLWake,

   604 	},

   605 

   606 	{ "RTL-8101",

   607 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   608 	  HasLWake,

   609 	},

   610 };

   611 

   612 struct rtl_extra_stats {

   613 	unsigned long early_rx;

   614 	unsigned long tx_buf_mapped;

   615 	unsigned long tx_timeouts;

   616 	unsigned long rx_lost_in_ring;

   617 };

   618 

   619 struct rtl8139_private {

   620 	void __iomem		*mmio_addr;

   621 	int			drv_flags;

   622 	struct pci_dev		*pci_dev;

   623 	u32			msg_enable;

   624 	struct napi_struct	napi;

   625 	struct net_device	*dev;

   626 	struct net_device_stats	stats;

   627 

   628 	unsigned char		*rx_ring;

   629 	unsigned int		cur_rx;	/* RX buf index of next pkt */

   630 	dma_addr_t		rx_ring_dma;

   631 

   632 	unsigned int		tx_flag;

   633 	unsigned long		cur_tx;

   634 	unsigned long		dirty_tx;

   635 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   636 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */

   637 	dma_addr_t		tx_bufs_dma;

   638 

   639 	signed char		phys[4];	/* MII device addresses. */

   640 

   641 				/* Twister tune state. */

   642 	char			twistie, twist_row, twist_col;

   643 

   644 	unsigned int		watchdog_fired : 1;

   645 	unsigned int		default_port : 4; /* Last dev->if_port value. */

   646 	unsigned int		have_thread : 1;

   647 

   648 	spinlock_t		lock;

   649 	spinlock_t		rx_lock;

   650 

   651 	chip_t			chipset;

   652 	u32			rx_config;

   653 	struct rtl_extra_stats	xstats;

   654 

   655 	struct delayed_work	thread;

   656 

   657 	struct mii_if_info	mii;

   658 	unsigned int		regs_len;

   659 	unsigned long		fifo_copy_timeout;

   660     

   661 	ec_device_t *ecdev;

   662 };

   663 

   664 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   665 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   666 MODULE_LICENSE("GPL");

   667 MODULE_VERSION(EC_MASTER_VERSION);

   668 

   669 module_param(multicast_filter_limit, int, 0);

   670 module_param_array(media, int, NULL, 0);

   671 module_param_array(full_duplex, int, NULL, 0);

   672 module_param(debug, int, 0);

   673 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   674 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   675 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   676 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   677 

   678 void ec_poll(struct net_device *);

   679 

   680 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   681 static int rtl8139_open (struct net_device *dev);

   682 static int mdio_read (struct net_device *dev, int phy_id, int location);

   683 static void mdio_write (struct net_device *dev, int phy_id, int location,

   684 			int val);

   685 static void rtl8139_start_thread(struct rtl8139_private *tp);

   686 static void rtl8139_tx_timeout (struct net_device *dev);

   687 static void rtl8139_init_ring (struct net_device *dev);

   688 static int rtl8139_start_xmit (struct sk_buff *skb,

   689 			       struct net_device *dev);

   690 #ifdef CONFIG_NET_POLL_CONTROLLER

   691 static void rtl8139_poll_controller(struct net_device *dev);

   692 #endif

   693 static int rtl8139_poll(struct napi_struct *napi, int budget);

   694 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);

   695 static int rtl8139_close (struct net_device *dev);

   696 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   697 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   698 static void rtl8139_set_rx_mode (struct net_device *dev);

   699 static void __set_rx_mode (struct net_device *dev);

   700 static void rtl8139_hw_start (struct net_device *dev);

   701 static void rtl8139_thread (struct work_struct *work);

   702 static void rtl8139_tx_timeout_task(struct work_struct *work);

   703 static const struct ethtool_ops rtl8139_ethtool_ops;

   704 

   705 /* write MMIO register, with flush */

   706 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   707 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   708 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   709 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   710 

   711 /* write MMIO register */

   712 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   713 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   714 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   715 

   716 /* read MMIO register */

   717 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   718 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   719 #define RTL_R32(reg)		((unsigned long) ioread32 (ioaddr + (reg)))

   720 

   721 

   722 static const u16 rtl8139_intr_mask =

   723 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   724 	TxErr | TxOK | RxErr | RxOK;

   725 

   726 static const u16 rtl8139_norx_intr_mask =

   727 	PCIErr | PCSTimeout | RxUnderrun |

   728 	TxErr | TxOK | RxErr ;

   729 

   730 #if RX_BUF_IDX == 0

   731 static const unsigned int rtl8139_rx_config =

   732 	RxCfgRcv8K | RxNoWrap |

   733 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   734 	(RX_DMA_BURST << RxCfgDMAShift);

   735 #elif RX_BUF_IDX == 1

   736 static const unsigned int rtl8139_rx_config =

   737 	RxCfgRcv16K | RxNoWrap |

   738 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   739 	(RX_DMA_BURST << RxCfgDMAShift);

   740 #elif RX_BUF_IDX == 2

   741 static const unsigned int rtl8139_rx_config =

   742 	RxCfgRcv32K | RxNoWrap |

   743 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   744 	(RX_DMA_BURST << RxCfgDMAShift);

   745 #elif RX_BUF_IDX == 3

   746 static const unsigned int rtl8139_rx_config =

   747 	RxCfgRcv64K |

   748 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   749 	(RX_DMA_BURST << RxCfgDMAShift);

   750 #else

   751 #error "Invalid configuration for 8139_RXBUF_IDX"

   752 #endif

   753 

   754 static const unsigned int rtl8139_tx_config =

   755 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   756 

   757 static void __rtl8139_cleanup_dev (struct net_device *dev)

   758 {

   759 	struct rtl8139_private *tp = netdev_priv(dev);

   760 	struct pci_dev *pdev;

   761 

   762 	assert (dev != NULL);

   763 	assert (tp->pci_dev != NULL);

   764 	pdev = tp->pci_dev;

   765 

   766 #ifdef USE_IO_OPS

   767 	if (tp->mmio_addr)

   768 		ioport_unmap (tp->mmio_addr);

   769 #else

   770 	if (tp->mmio_addr)

   771 		pci_iounmap (pdev, tp->mmio_addr);

   772 #endif /* USE_IO_OPS */

   773 

   774 	/* it's ok to call this even if we have no regions to free */

   775 	pci_release_regions (pdev);

   776 

   777 	free_netdev(dev);

   778 	pci_set_drvdata (pdev, NULL);

   779 }

   780 

   781 

   782 static void rtl8139_chip_reset (void __iomem *ioaddr)

   783 {

   784 	int i;

   785 

   786 	/* Soft reset the chip. */

   787 	RTL_W8 (ChipCmd, CmdReset);

   788 

   789 	/* Check that the chip has finished the reset. */

   790 	for (i = 1000; i > 0; i--) {

   791 		barrier();

   792 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   793 			break;

   794 		udelay (10);

   795 	}

   796 }

   797 

   798 

   799 static int __devinit rtl8139_init_board (struct pci_dev *pdev,

   800 					 struct net_device **dev_out)

   801 {

   802 	void __iomem *ioaddr;

   803 	struct net_device *dev;

   804 	struct rtl8139_private *tp;

   805 	u8 tmp8;

   806 	int rc, disable_dev_on_err = 0;

   807 	unsigned int i;

   808 	unsigned long pio_start, pio_end, pio_flags, pio_len;

   809 	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;

   810 	u32 version;

   811 

   812 	assert (pdev != NULL);

   813 

   814 	*dev_out = NULL;

   815 

   816 	/* dev and priv zeroed in alloc_etherdev */

   817 	dev = alloc_etherdev (sizeof (*tp));

   818 	if (dev == NULL) {

   819 		dev_err(&pdev->dev, "Unable to alloc new net device\n");

   820 		return -ENOMEM;

   821 	}

   822 	SET_NETDEV_DEV(dev, &pdev->dev);

   823 

   824 	tp = netdev_priv(dev);

   825 	tp->pci_dev = pdev;

   826 

   827 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   828 	rc = pci_enable_device (pdev);

   829 	if (rc)

   830 		goto err_out;

   831 

   832 	pio_start = pci_resource_start (pdev, 0);

   833 	pio_end = pci_resource_end (pdev, 0);

   834 	pio_flags = pci_resource_flags (pdev, 0);

   835 	pio_len = pci_resource_len (pdev, 0);

   836 

   837 	mmio_start = pci_resource_start (pdev, 1);

   838 	mmio_end = pci_resource_end (pdev, 1);

   839 	mmio_flags = pci_resource_flags (pdev, 1);

   840 	mmio_len = pci_resource_len (pdev, 1);

   841 

   842 	/* set this immediately, we need to know before

   843 	 * we talk to the chip directly */

   844 	DPRINTK("PIO region size == 0x%02X\n", pio_len);

   845 	DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);

   846 

   847 #ifdef USE_IO_OPS

   848 	/* make sure PCI base addr 0 is PIO */

   849 	if (!(pio_flags & IORESOURCE_IO)) {

   850 		dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");

   851 		rc = -ENODEV;

   852 		goto err_out;

   853 	}

   854 	/* check for weird/broken PCI region reporting */

   855 	if (pio_len < RTL_MIN_IO_SIZE) {

   856 		dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");

   857 		rc = -ENODEV;

   858 		goto err_out;

   859 	}

   860 #else

   861 	/* make sure PCI base addr 1 is MMIO */

   862 	if (!(mmio_flags & IORESOURCE_MEM)) {

   863 		dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");

   864 		rc = -ENODEV;

   865 		goto err_out;

   866 	}

   867 	if (mmio_len < RTL_MIN_IO_SIZE) {

   868 		dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");

   869 		rc = -ENODEV;

   870 		goto err_out;

   871 	}

   872 #endif

   873 

   874 	rc = pci_request_regions (pdev, DRV_NAME);

   875 	if (rc)

   876 		goto err_out;

   877 	disable_dev_on_err = 1;

   878 

   879 	/* enable PCI bus-mastering */

   880 	pci_set_master (pdev);

   881 

   882 #ifdef USE_IO_OPS

   883 	ioaddr = ioport_map(pio_start, pio_len);

   884 	if (!ioaddr) {

   885 		dev_err(&pdev->dev, "cannot map PIO, aborting\n");

   886 		rc = -EIO;

   887 		goto err_out;

   888 	}

   889 	dev->base_addr = pio_start;

   890 	tp->mmio_addr = ioaddr;

   891 	tp->regs_len = pio_len;

   892 #else

   893 	/* ioremap MMIO region */

   894 	ioaddr = pci_iomap(pdev, 1, 0);

   895 	if (ioaddr == NULL) {

   896 		dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");

   897 		rc = -EIO;

   898 		goto err_out;

   899 	}

   900 	dev->base_addr = (long) ioaddr;

   901 	tp->mmio_addr = ioaddr;

   902 	tp->regs_len = mmio_len;

   903 #endif /* USE_IO_OPS */

   904 

   905 	/* Bring old chips out of low-power mode. */

   906 	RTL_W8 (HltClk, 'R');

   907 

   908 	/* check for missing/broken hardware */

   909 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   910 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");

   911 		rc = -EIO;

   912 		goto err_out;

   913 	}

   914 

   915 	/* identify chip attached to board */

   916 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   917 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   918 		if (version == rtl_chip_info[i].version) {

   919 			tp->chipset = i;

   920 			goto match;

   921 		}

   922 

   923 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   924 	dev_printk (KERN_DEBUG, &pdev->dev,

   925 		    "unknown chip version, assuming RTL-8139\n");

   926 	dev_printk (KERN_DEBUG, &pdev->dev,

   927 		    "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));

   928 	tp->chipset = 0;

   929 

   930 match:

   931 	DPRINTK ("chipset id (%d) == index %d, '%s'\n",

   932 		 version, i, rtl_chip_info[i].name);

   933 

   934 	if (tp->chipset >= CH_8139B) {

   935 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   936 		DPRINTK("PCI PM wakeup\n");

   937 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   938 		    (tmp8 & LWAKE))

   939 			new_tmp8 &= ~LWAKE;

   940 		new_tmp8 |= Cfg1_PM_Enable;

   941 		if (new_tmp8 != tmp8) {

   942 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   943 			RTL_W8 (Config1, tmp8);

   944 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   945 		}

   946 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   947 			tmp8 = RTL_R8 (Config4);

   948 			if (tmp8 & LWPTN) {

   949 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   950 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   951 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   952 			}

   953 		}

   954 	} else {

   955 		DPRINTK("Old chip wakeup\n");

   956 		tmp8 = RTL_R8 (Config1);

   957 		tmp8 &= ~(SLEEP | PWRDN);

   958 		RTL_W8 (Config1, tmp8);

   959 	}

   960 

   961 	rtl8139_chip_reset (ioaddr);

   962 

   963 	*dev_out = dev;

   964 	return 0;

   965 

   966 err_out:

   967 	__rtl8139_cleanup_dev (dev);

   968 	if (disable_dev_on_err)

   969 		pci_disable_device (pdev);

   970 	return rc;

   971 }

   972 

   973 

   974 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

   975 				       const struct pci_device_id *ent)

   976 {

   977 	struct net_device *dev = NULL;

   978 	struct rtl8139_private *tp;

   979 	int i, addr_len, option;

   980 	void __iomem *ioaddr;

   981 	static int board_idx = -1;

   982 	DECLARE_MAC_BUF(mac);

   983 

   984 	assert (pdev != NULL);

   985 	assert (ent != NULL);

   986 

   987 	board_idx++;

   988 

   989 	/* when we're built into the kernel, the driver version message

   990 	 * is only printed if at least one 8139 board has been found

   991 	 */

   992 #ifndef MODULE

   993 	{

   994 		static int printed_version;

   995 		if (!printed_version++)

   996 			printk (KERN_INFO RTL8139_DRIVER_NAME "\n");

   997 	}

   998 #endif

   999 

  1000 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1001 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {

  1002 		dev_info(&pdev->dev,

  1003 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",

  1004 		       	   pdev->vendor, pdev->device, pdev->revision);

  1005 		dev_info(&pdev->dev,

  1006 			   "Use the \"8139cp\" driver for improved performance and stability.\n");

  1007 	}

  1008 

  1009 	i = rtl8139_init_board (pdev, &dev);

  1010 	if (i < 0)

  1011 		return i;

  1012 

  1013 	assert (dev != NULL);

  1014 	tp = netdev_priv(dev);

  1015 	tp->dev = dev;

  1016 

  1017 	ioaddr = tp->mmio_addr;

  1018 	assert (ioaddr != NULL);

  1019 

  1020 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1021 	for (i = 0; i < 3; i++)

  1022 		((u16 *) (dev->dev_addr))[i] =

  1023 		    le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));

  1024 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

  1025 

  1026 	/* The Rtl8139-specific entries in the device structure. */

  1027 	dev->open = rtl8139_open;

  1028 	dev->hard_start_xmit = rtl8139_start_xmit;

  1029 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);

  1030 	dev->stop = rtl8139_close;

  1031 	dev->get_stats = rtl8139_get_stats;

  1032 	dev->set_multicast_list = rtl8139_set_rx_mode;

  1033 	dev->do_ioctl = netdev_ioctl;

  1034 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1035 	dev->tx_timeout = rtl8139_tx_timeout;

  1036 	dev->watchdog_timeo = TX_TIMEOUT;

  1037 #ifdef CONFIG_NET_POLL_CONTROLLER

  1038 	dev->poll_controller = rtl8139_poll_controller;

  1039 #endif

  1040 

  1041 	/* note: the hardware is not capable of sg/csum/highdma, however

  1042 	 * through the use of skb_copy_and_csum_dev we enable these

  1043 	 * features

  1044 	 */

  1045 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1046 

  1047 	dev->irq = pdev->irq;

  1048 

  1049 	/* tp zeroed and aligned in alloc_etherdev */

  1050 	tp = netdev_priv(dev);

  1051 

  1052 	/* note: tp->chipset set in rtl8139_init_board */

  1053 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1054 	tp->mmio_addr = ioaddr;

  1055 	tp->msg_enable =

  1056 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1057 	spin_lock_init (&tp->lock);

  1058 	spin_lock_init (&tp->rx_lock);

  1059 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);

  1060 	tp->mii.dev = dev;

  1061 	tp->mii.mdio_read = mdio_read;

  1062 	tp->mii.mdio_write = mdio_write;

  1063 	tp->mii.phy_id_mask = 0x3f;

  1064 	tp->mii.reg_num_mask = 0x1f;

  1065 

  1066 	/* dev is fully set up and ready to use now */

  1067     

  1068 	// offer device to EtherCAT master module

  1069 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);

  1070 

  1071 	if (!tp->ecdev) {

  1072 		DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);

  1073 		i = register_netdev (dev);

  1074 		if (i) goto err_out;

  1075 	}

  1076 

  1077 	pci_set_drvdata (pdev, dev);

  1078 

  1079 	printk (KERN_INFO "%s: %s at 0x%lx, "

  1080 		"%s, IRQ %d\n",

  1081 		dev->name,

  1082 		board_info[ent->driver_data].name,

  1083 		dev->base_addr,

  1084 		print_mac(mac, dev->dev_addr),

  1085 		dev->irq);

  1086 

  1087 	printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",

  1088 		dev->name, rtl_chip_info[tp->chipset].name);

  1089 

  1090 	/* Find the connected MII xcvrs.

  1091 	   Doing this in open() would allow detecting external xcvrs later, but

  1092 	   takes too much time. */

  1093 #ifdef CONFIG_8139TOO_8129

  1094 	if (tp->drv_flags & HAS_MII_XCVR) {

  1095 		int phy, phy_idx = 0;

  1096 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1097 			int mii_status = mdio_read(dev, phy, 1);

  1098 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1099 				u16 advertising = mdio_read(dev, phy, 4);

  1100 				tp->phys[phy_idx++] = phy;

  1101 				printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "

  1102 					   "advertising %4.4x.\n",

  1103 					   dev->name, phy, mii_status, advertising);

  1104 			}

  1105 		}

  1106 		if (phy_idx == 0) {

  1107 			printk(KERN_INFO "%s: No MII transceivers found!  Assuming SYM "

  1108 				   "transceiver.\n",

  1109 				   dev->name);

  1110 			tp->phys[0] = 32;

  1111 		}

  1112 	} else

  1113 #endif

  1114 		tp->phys[0] = 32;

  1115 	tp->mii.phy_id = tp->phys[0];

  1116 

  1117 	/* The lower four bits are the media type. */

  1118 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];

  1119 	if (option > 0) {

  1120 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;

  1121 		tp->default_port = option & 0xFF;

  1122 		if (tp->default_port)

  1123 			tp->mii.force_media = 1;

  1124 	}

  1125 	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)

  1126 		tp->mii.full_duplex = full_duplex[board_idx];

  1127 	if (tp->mii.full_duplex) {

  1128 		printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);

  1129 		/* Changing the MII-advertised media because might prevent

  1130 		   re-connection. */

  1131 		tp->mii.force_media = 1;

  1132 	}

  1133 	if (tp->default_port) {

  1134 		printk(KERN_INFO "  Forcing %dMbps %s-duplex operation.\n",

  1135 			   (option & 0x20 ? 100 : 10),

  1136 			   (option & 0x10 ? "full" : "half"));