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1 /* |
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2 * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
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3 * |
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4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> |
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5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> |
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6 * Copyright (c) a lot of people too. Please respect their work. |
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7 * |
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8 * See MAINTAINERS file for support contact information. |
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9 * |
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10 * vim: noexpandtab |
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11 */ |
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12 |
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13 #include <linux/module.h> |
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14 #include <linux/moduleparam.h> |
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15 #include <linux/pci.h> |
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16 #include <linux/netdevice.h> |
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17 #include <linux/etherdevice.h> |
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18 #include <linux/delay.h> |
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19 #include <linux/ethtool.h> |
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20 #include <linux/mii.h> |
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21 #include <linux/if_vlan.h> |
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22 #include <linux/crc32.h> |
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23 #include <linux/in.h> |
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24 #include <linux/ip.h> |
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25 #include <linux/tcp.h> |
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26 #include <linux/init.h> |
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27 #include <linux/dma-mapping.h> |
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28 |
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29 #include <asm/system.h> |
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30 #include <asm/io.h> |
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31 #include <asm/irq.h> |
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32 |
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33 #include "../globals.h" |
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34 #include "ecdev.h" |
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35 |
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36 #define RTL8169_VERSION "2.3LK-NAPI" |
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37 #define MODULENAME "ec_r8169" |
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38 #define PFX MODULENAME ": " |
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39 |
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40 #ifdef RTL8169_DEBUG |
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41 #define assert(expr) \ |
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42 if (!(expr)) { \ |
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43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
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44 #expr,__FILE__,__FUNCTION__,__LINE__); \ |
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45 } |
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46 #define dprintk(fmt, args...) \ |
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47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) |
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48 #else |
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49 #define assert(expr) do {} while (0) |
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50 #define dprintk(fmt, args...) do {} while (0) |
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51 #endif /* RTL8169_DEBUG */ |
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52 |
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53 #define R8169_MSG_DEFAULT \ |
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54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
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55 |
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56 #define TX_BUFFS_AVAIL(tp) \ |
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57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) |
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58 |
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59 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
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60 static const int max_interrupt_work = 20; |
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61 |
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62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
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63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
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64 static const int multicast_filter_limit = 32; |
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65 |
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66 /* MAC address length */ |
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67 #define MAC_ADDR_LEN 6 |
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68 |
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69 #define MAX_READ_REQUEST_SHIFT 12 |
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70 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
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71 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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72 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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73 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
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74 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
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75 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
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76 |
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77 #define R8169_REGS_SIZE 256 |
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78 #define R8169_NAPI_WEIGHT 64 |
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79 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
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80 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
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81 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
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82 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
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83 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
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84 |
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85 #define RTL8169_TX_TIMEOUT (6*HZ) |
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86 #define RTL8169_PHY_TIMEOUT (10*HZ) |
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87 |
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88 /* write/read MMIO register */ |
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89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
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90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
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91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
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92 #define RTL_R8(reg) readb (ioaddr + (reg)) |
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93 #define RTL_R16(reg) readw (ioaddr + (reg)) |
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94 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) |
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95 |
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96 enum mac_version { |
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97 RTL_GIGA_MAC_NONE = 0x00, |
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98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
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99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S |
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100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S |
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101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB |
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102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd |
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103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
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104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e |
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105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e |
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106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e |
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107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e |
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108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
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109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
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110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb |
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111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? |
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112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? |
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113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec |
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114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf |
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115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP |
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116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C |
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117 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C |
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118 }; |
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119 |
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120 #define _R(NAME,MAC,MASK) \ |
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121 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } |
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122 |
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123 static const struct { |
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124 const char *name; |
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125 u8 mac_version; |
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126 u32 RxConfigMask; /* Clears the bits supported by this chip */ |
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127 } rtl_chip_info[] = { |
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128 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
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129 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S |
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130 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S |
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131 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB |
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132 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd |
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133 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
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134 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E |
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135 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E |
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136 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E |
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137 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E |
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138 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
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139 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E |
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140 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 |
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141 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 |
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142 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 |
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143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E |
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144 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E |
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145 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E |
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146 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E |
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147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E |
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148 }; |
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149 #undef _R |
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150 |
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151 enum cfg_version { |
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152 RTL_CFG_0 = 0x00, |
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153 RTL_CFG_1, |
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154 RTL_CFG_2 |
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155 }; |
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156 |
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157 static void rtl_hw_start_8169(struct net_device *); |
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158 static void rtl_hw_start_8168(struct net_device *); |
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159 static void rtl_hw_start_8101(struct net_device *); |
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160 |
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161 static struct pci_device_id rtl8169_pci_tbl[] = { |
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162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
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163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
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164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
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165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
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166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
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167 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
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168 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
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169 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
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170 { PCI_VENDOR_ID_LINKSYS, 0x1032, |
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171 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
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172 { 0x0001, 0x8168, |
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173 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, |
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174 {0,}, |
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175 }; |
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176 |
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177 /* prevent driver from being loaded automatically */ |
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178 //MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); |
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179 |
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180 static int rx_copybreak = 200; |
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181 static int use_dac; |
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182 static struct { |
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183 u32 msg_enable; |
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184 } debug = { -1 }; |
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185 |
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186 enum rtl_registers { |
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187 MAC0 = 0, /* Ethernet hardware address. */ |
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188 MAC4 = 4, |
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189 MAR0 = 8, /* Multicast filter. */ |
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190 CounterAddrLow = 0x10, |
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191 CounterAddrHigh = 0x14, |
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192 TxDescStartAddrLow = 0x20, |
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193 TxDescStartAddrHigh = 0x24, |
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194 TxHDescStartAddrLow = 0x28, |
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195 TxHDescStartAddrHigh = 0x2c, |
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196 FLASH = 0x30, |
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197 ERSR = 0x36, |
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198 ChipCmd = 0x37, |
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199 TxPoll = 0x38, |
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200 IntrMask = 0x3c, |
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201 IntrStatus = 0x3e, |
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202 TxConfig = 0x40, |
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203 RxConfig = 0x44, |
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204 RxMissed = 0x4c, |
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205 Cfg9346 = 0x50, |
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206 Config0 = 0x51, |
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207 Config1 = 0x52, |
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208 Config2 = 0x53, |
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209 Config3 = 0x54, |
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210 Config4 = 0x55, |
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211 Config5 = 0x56, |
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212 MultiIntr = 0x5c, |
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213 PHYAR = 0x60, |
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214 PHYstatus = 0x6c, |
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215 RxMaxSize = 0xda, |
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216 CPlusCmd = 0xe0, |
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217 IntrMitigate = 0xe2, |
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218 RxDescAddrLow = 0xe4, |
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219 RxDescAddrHigh = 0xe8, |
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220 EarlyTxThres = 0xec, |
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221 FuncEvent = 0xf0, |
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222 FuncEventMask = 0xf4, |
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223 FuncPresetState = 0xf8, |
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224 FuncForceEvent = 0xfc, |
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225 }; |
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226 |
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227 enum rtl8110_registers { |
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228 TBICSR = 0x64, |
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229 TBI_ANAR = 0x68, |
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230 TBI_LPAR = 0x6a, |
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231 }; |
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232 |
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233 enum rtl8168_8101_registers { |
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234 CSIDR = 0x64, |
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235 CSIAR = 0x68, |
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236 #define CSIAR_FLAG 0x80000000 |
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237 #define CSIAR_WRITE_CMD 0x80000000 |
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238 #define CSIAR_BYTE_ENABLE 0x0f |
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239 #define CSIAR_BYTE_ENABLE_SHIFT 12 |
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240 #define CSIAR_ADDR_MASK 0x0fff |
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241 |
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242 EPHYAR = 0x80, |
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243 #define EPHYAR_FLAG 0x80000000 |
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244 #define EPHYAR_WRITE_CMD 0x80000000 |
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245 #define EPHYAR_REG_MASK 0x1f |
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246 #define EPHYAR_REG_SHIFT 16 |
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247 #define EPHYAR_DATA_MASK 0xffff |
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248 DBG_REG = 0xd1, |
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249 #define FIX_NAK_1 (1 << 4) |
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250 #define FIX_NAK_2 (1 << 3) |
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251 }; |
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252 |
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253 enum rtl_register_content { |
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254 /* InterruptStatusBits */ |
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255 SYSErr = 0x8000, |
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256 PCSTimeout = 0x4000, |
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257 SWInt = 0x0100, |
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258 TxDescUnavail = 0x0080, |
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259 RxFIFOOver = 0x0040, |
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260 LinkChg = 0x0020, |
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261 RxOverflow = 0x0010, |
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262 TxErr = 0x0008, |
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263 TxOK = 0x0004, |
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264 RxErr = 0x0002, |
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265 RxOK = 0x0001, |
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266 |
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267 /* RxStatusDesc */ |
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268 RxFOVF = (1 << 23), |
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269 RxRWT = (1 << 22), |
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270 RxRES = (1 << 21), |
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271 RxRUNT = (1 << 20), |
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272 RxCRC = (1 << 19), |
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273 |
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274 /* ChipCmdBits */ |
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275 CmdReset = 0x10, |
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276 CmdRxEnb = 0x08, |
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277 CmdTxEnb = 0x04, |
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278 RxBufEmpty = 0x01, |
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279 |
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280 /* TXPoll register p.5 */ |
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281 HPQ = 0x80, /* Poll cmd on the high prio queue */ |
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282 NPQ = 0x40, /* Poll cmd on the low prio queue */ |
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283 FSWInt = 0x01, /* Forced software interrupt */ |
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284 |
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285 /* Cfg9346Bits */ |
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286 Cfg9346_Lock = 0x00, |
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287 Cfg9346_Unlock = 0xc0, |
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288 |
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289 /* rx_mode_bits */ |
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290 AcceptErr = 0x20, |
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291 AcceptRunt = 0x10, |
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292 AcceptBroadcast = 0x08, |
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293 AcceptMulticast = 0x04, |
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294 AcceptMyPhys = 0x02, |
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295 AcceptAllPhys = 0x01, |
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296 |
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297 /* RxConfigBits */ |
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298 RxCfgFIFOShift = 13, |
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299 RxCfgDMAShift = 8, |
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300 |
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301 /* TxConfigBits */ |
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302 TxInterFrameGapShift = 24, |
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303 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
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304 |
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305 /* Config1 register p.24 */ |
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306 LEDS1 = (1 << 7), |
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307 LEDS0 = (1 << 6), |
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308 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
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309 Speed_down = (1 << 4), |
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310 MEMMAP = (1 << 3), |
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311 IOMAP = (1 << 2), |
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312 VPD = (1 << 1), |
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313 PMEnable = (1 << 0), /* Power Management Enable */ |
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314 |
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315 /* Config2 register p. 25 */ |
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316 PCI_Clock_66MHz = 0x01, |
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317 PCI_Clock_33MHz = 0x00, |
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318 |
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319 /* Config3 register p.25 */ |
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320 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ |
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321 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ |
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322 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
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323 |
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324 /* Config5 register p.27 */ |
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325 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
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326 MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
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327 UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
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328 LanWake = (1 << 1), /* LanWake enable/disable */ |
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329 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
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330 |
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331 /* TBICSR p.28 */ |
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332 TBIReset = 0x80000000, |
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333 TBILoopback = 0x40000000, |
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334 TBINwEnable = 0x20000000, |
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335 TBINwRestart = 0x10000000, |
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336 TBILinkOk = 0x02000000, |
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337 TBINwComplete = 0x01000000, |
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338 |
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339 /* CPlusCmd p.31 */ |
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340 EnableBist = (1 << 15), // 8168 8101 |
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341 Mac_dbgo_oe = (1 << 14), // 8168 8101 |
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342 Normal_mode = (1 << 13), // unused |
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343 Force_half_dup = (1 << 12), // 8168 8101 |
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344 Force_rxflow_en = (1 << 11), // 8168 8101 |
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345 Force_txflow_en = (1 << 10), // 8168 8101 |
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346 Cxpl_dbg_sel = (1 << 9), // 8168 8101 |
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347 ASF = (1 << 8), // 8168 8101 |
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348 PktCntrDisable = (1 << 7), // 8168 8101 |
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349 Mac_dbgo_sel = 0x001c, // 8168 |
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350 RxVlan = (1 << 6), |
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351 RxChkSum = (1 << 5), |
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352 PCIDAC = (1 << 4), |
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353 PCIMulRW = (1 << 3), |
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354 INTT_0 = 0x0000, // 8168 |
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355 INTT_1 = 0x0001, // 8168 |
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356 INTT_2 = 0x0002, // 8168 |
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357 INTT_3 = 0x0003, // 8168 |
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358 |
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359 /* rtl8169_PHYstatus */ |
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360 TBI_Enable = 0x80, |
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361 TxFlowCtrl = 0x40, |
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362 RxFlowCtrl = 0x20, |
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363 _1000bpsF = 0x10, |
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364 _100bps = 0x08, |
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365 _10bps = 0x04, |
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366 LinkStatus = 0x02, |
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367 FullDup = 0x01, |
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368 |
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369 /* _TBICSRBit */ |
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370 TBILinkOK = 0x02000000, |
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371 |
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372 /* DumpCounterCommand */ |
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373 CounterDump = 0x8, |
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374 }; |
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375 |
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376 enum desc_status_bit { |
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377 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
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378 RingEnd = (1 << 30), /* End of descriptor ring */ |
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379 FirstFrag = (1 << 29), /* First segment of a packet */ |
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380 LastFrag = (1 << 28), /* Final segment of a packet */ |
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381 |
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382 /* Tx private */ |
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383 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ |
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384 MSSShift = 16, /* MSS value position */ |
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385 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ |
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386 IPCS = (1 << 18), /* Calculate IP checksum */ |
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387 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ |
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388 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ |
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389 TxVlanTag = (1 << 17), /* Add VLAN tag */ |
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390 |
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391 /* Rx private */ |
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392 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ |
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393 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ |
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394 |
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395 #define RxProtoUDP (PID1) |
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396 #define RxProtoTCP (PID0) |
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397 #define RxProtoIP (PID1 | PID0) |
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398 #define RxProtoMask RxProtoIP |
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399 |
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400 IPFail = (1 << 16), /* IP checksum failed */ |
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401 UDPFail = (1 << 15), /* UDP/IP checksum failed */ |
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402 TCPFail = (1 << 14), /* TCP/IP checksum failed */ |
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403 RxVlanTag = (1 << 16), /* VLAN tag available */ |
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404 }; |
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405 |
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406 #define RsvdMask 0x3fffc000 |
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407 |
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408 struct TxDesc { |
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409 __le32 opts1; |
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410 __le32 opts2; |
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411 __le64 addr; |
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412 }; |
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413 |
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414 struct RxDesc { |
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415 __le32 opts1; |
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416 __le32 opts2; |
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417 __le64 addr; |
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418 }; |
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419 |
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420 struct ring_info { |
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421 struct sk_buff *skb; |
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422 u32 len; |
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423 u8 __pad[sizeof(void *) - sizeof(u32)]; |
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424 }; |
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425 |
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426 enum features { |
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427 RTL_FEATURE_WOL = (1 << 0), |
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428 RTL_FEATURE_MSI = (1 << 1), |
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429 RTL_FEATURE_GMII = (1 << 2), |
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430 }; |
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431 |
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432 struct rtl8169_counters { |
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433 __le64 tx_packets; |
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434 __le64 rx_packets; |
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435 __le64 tx_errors; |
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436 __le32 rx_errors; |
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437 __le16 rx_missed; |
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438 __le16 align_errors; |
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439 __le32 tx_one_collision; |
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440 __le32 tx_multi_collision; |
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441 __le64 rx_unicast; |
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442 __le64 rx_broadcast; |
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443 __le32 rx_multicast; |
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444 __le16 tx_aborted; |
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445 __le16 tx_underun; |
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446 }; |
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447 |
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448 struct rtl8169_private { |
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449 void __iomem *mmio_addr; /* memory map physical address */ |
|
450 struct pci_dev *pci_dev; /* Index of PCI device */ |
|
451 struct net_device *dev; |
|
452 struct napi_struct napi; |
|
453 spinlock_t lock; /* spin lock flag */ |
|
454 u32 msg_enable; |
|
455 int chipset; |
|
456 int mac_version; |
|
457 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
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458 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
|
459 u32 dirty_rx; |
|
460 u32 dirty_tx; |
|
461 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
|
462 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ |
|
463 dma_addr_t TxPhyAddr; |
|
464 dma_addr_t RxPhyAddr; |
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465 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ |
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466 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
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467 unsigned align; |
|
468 unsigned rx_buf_sz; |
|
469 struct timer_list timer; |
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470 u16 cp_cmd; |
|
471 u16 intr_event; |
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472 u16 napi_event; |
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473 u16 intr_mask; |
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474 int phy_auto_nego_reg; |
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475 int phy_1000_ctrl_reg; |
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476 #ifdef CONFIG_R8169_VLAN |
|
477 struct vlan_group *vlgrp; |
|
478 #endif |
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479 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); |
|
480 int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
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481 void (*phy_reset_enable)(void __iomem *); |
|
482 void (*hw_start)(struct net_device *); |
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483 unsigned int (*phy_reset_pending)(void __iomem *); |
|
484 unsigned int (*link_ok)(void __iomem *); |
|
485 int pcie_cap; |
|
486 struct delayed_work task; |
|
487 unsigned features; |
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488 |
|
489 struct mii_if_info mii; |
|
490 struct rtl8169_counters counters; |
|
491 |
|
492 ec_device_t *ecdev; |
|
493 unsigned long ec_watchdog_jiffies; |
|
494 }; |
|
495 |
|
496 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>"); |
|
497 MODULE_DESCRIPTION("EtherCAT-capable RealTek RTL-8169 Gigabit Ethernet driver"); |
|
498 module_param(rx_copybreak, int, 0); |
|
499 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); |
|
500 module_param(use_dac, int, 0); |
|
501 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
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502 module_param_named(debug, debug.msg_enable, int, 0); |
|
503 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); |
|
504 MODULE_LICENSE("GPL"); |
|
505 MODULE_VERSION(EC_MASTER_VERSION); |
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506 |
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507 static int rtl8169_open(struct net_device *dev); |
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508 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev); |
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509 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
|
510 static int rtl8169_init_ring(struct net_device *dev); |
|
511 static void rtl_hw_start(struct net_device *dev); |
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512 static int rtl8169_close(struct net_device *dev); |
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513 static void rtl_set_rx_mode(struct net_device *dev); |
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514 static void rtl8169_tx_timeout(struct net_device *dev); |
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515 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
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516 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
|
517 void __iomem *, u32 budget); |
|
518 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
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519 static void rtl8169_down(struct net_device *dev); |
|
520 static void rtl8169_rx_clear(struct rtl8169_private *tp); |
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521 static int rtl8169_poll(struct napi_struct *napi, int budget); |
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522 |
|
523 static const unsigned int rtl8169_rx_config = |
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524 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
|
525 |
|
526 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
527 { |
|
528 int i; |
|
529 |
|
530 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
|
531 |
|
532 for (i = 20; i > 0; i--) { |
|
533 /* |
|
534 * Check if the RTL8169 has completed writing to the specified |
|
535 * MII register. |
|
536 */ |
|
537 if (!(RTL_R32(PHYAR) & 0x80000000)) |
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538 break; |
|
539 udelay(25); |
|
540 } |
|
541 } |
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542 |
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543 static int mdio_read(void __iomem *ioaddr, int reg_addr) |
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544 { |
|
545 int i, value = -1; |
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546 |
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547 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
|
548 |
|
549 for (i = 20; i > 0; i--) { |
|
550 /* |
|
551 * Check if the RTL8169 has completed retrieving data from |
|
552 * the specified MII register. |
|
553 */ |
|
554 if (RTL_R32(PHYAR) & 0x80000000) { |
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555 value = RTL_R32(PHYAR) & 0xffff; |
|
556 break; |
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557 } |
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558 udelay(25); |
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559 } |
|
560 return value; |
|
561 } |
|
562 |
|
563 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) |
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564 { |
|
565 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); |
|
566 } |
|
567 |
|
568 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
|
569 int val) |
|
570 { |
|
571 struct rtl8169_private *tp = netdev_priv(dev); |
|
572 void __iomem *ioaddr = tp->mmio_addr; |
|
573 |
|
574 mdio_write(ioaddr, location, val); |
|
575 } |
|
576 |
|
577 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) |
|
578 { |
|
579 struct rtl8169_private *tp = netdev_priv(dev); |
|
580 void __iomem *ioaddr = tp->mmio_addr; |
|
581 |
|
582 return mdio_read(ioaddr, location); |
|
583 } |
|
584 |
|
585 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
|
586 { |
|
587 unsigned int i; |
|
588 |
|
589 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | |
|
590 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
591 |
|
592 for (i = 0; i < 100; i++) { |
|
593 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) |
|
594 break; |
|
595 udelay(10); |
|
596 } |
|
597 } |
|
598 |
|
599 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) |
|
600 { |
|
601 u16 value = 0xffff; |
|
602 unsigned int i; |
|
603 |
|
604 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
605 |
|
606 for (i = 0; i < 100; i++) { |
|
607 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { |
|
608 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; |
|
609 break; |
|
610 } |
|
611 udelay(10); |
|
612 } |
|
613 |
|
614 return value; |
|
615 } |
|
616 |
|
617 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) |
|
618 { |
|
619 unsigned int i; |
|
620 |
|
621 RTL_W32(CSIDR, value); |
|
622 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | |
|
623 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
624 |
|
625 for (i = 0; i < 100; i++) { |
|
626 if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) |
|
627 break; |
|
628 udelay(10); |
|
629 } |
|
630 } |
|
631 |
|
632 static u32 rtl_csi_read(void __iomem *ioaddr, int addr) |
|
633 { |
|
634 u32 value = ~0x00; |
|
635 unsigned int i; |
|
636 |
|
637 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | |
|
638 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
639 |
|
640 for (i = 0; i < 100; i++) { |
|
641 if (RTL_R32(CSIAR) & CSIAR_FLAG) { |
|
642 value = RTL_R32(CSIDR); |
|
643 break; |
|
644 } |
|
645 udelay(10); |
|
646 } |
|
647 |
|
648 return value; |
|
649 } |
|
650 |
|
651 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
|
652 { |
|
653 RTL_W16(IntrMask, 0x0000); |
|
654 |
|
655 RTL_W16(IntrStatus, 0xffff); |
|
656 } |
|
657 |
|
658 static void rtl8169_asic_down(void __iomem *ioaddr) |
|
659 { |
|
660 RTL_W8(ChipCmd, 0x00); |
|
661 rtl8169_irq_mask_and_ack(ioaddr); |
|
662 RTL_R16(CPlusCmd); |
|
663 } |
|
664 |
|
665 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) |
|
666 { |
|
667 return RTL_R32(TBICSR) & TBIReset; |
|
668 } |
|
669 |
|
670 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) |
|
671 { |
|
672 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; |
|
673 } |
|
674 |
|
675 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) |
|
676 { |
|
677 return RTL_R32(TBICSR) & TBILinkOk; |
|
678 } |
|
679 |
|
680 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) |
|
681 { |
|
682 return RTL_R8(PHYstatus) & LinkStatus; |
|
683 } |
|
684 |
|
685 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) |
|
686 { |
|
687 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
|
688 } |
|
689 |
|
690 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) |
|
691 { |
|
692 unsigned int val; |
|
693 |
|
694 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; |
|
695 mdio_write(ioaddr, MII_BMCR, val & 0xffff); |
|
696 } |
|
697 |
|
698 static void rtl8169_check_link_status(struct net_device *dev, |
|
699 struct rtl8169_private *tp, |
|
700 void __iomem *ioaddr) |
|
701 { |
|
702 unsigned long flags; |
|
703 |
|
704 if (tp->ecdev) { |
|
705 ecdev_set_link(tp->ecdev, tp->link_ok(ioaddr) ? 1 : 0); |
|
706 } else { |
|
707 spin_lock_irqsave(&tp->lock, flags); |
|
708 if (tp->link_ok(ioaddr)) { |
|
709 netif_carrier_on(dev); |
|
710 if (netif_msg_ifup(tp)) |
|
711 printk(KERN_INFO PFX "%s: link up\n", dev->name); |
|
712 } else { |
|
713 if (netif_msg_ifdown(tp)) |
|
714 printk(KERN_INFO PFX "%s: link down\n", dev->name); |
|
715 netif_carrier_off(dev); |
|
716 } |
|
717 spin_unlock_irqrestore(&tp->lock, flags); |
|
718 } |
|
719 } |
|
720 |
|
721 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
722 { |
|
723 struct rtl8169_private *tp = netdev_priv(dev); |
|
724 void __iomem *ioaddr = tp->mmio_addr; |
|
725 u8 options; |
|
726 |
|
727 wol->wolopts = 0; |
|
728 |
|
729 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
|
730 wol->supported = WAKE_ANY; |
|
731 |
|
732 spin_lock_irq(&tp->lock); |
|
733 |
|
734 options = RTL_R8(Config1); |
|
735 if (!(options & PMEnable)) |
|
736 goto out_unlock; |
|
737 |
|
738 options = RTL_R8(Config3); |
|
739 if (options & LinkUp) |
|
740 wol->wolopts |= WAKE_PHY; |
|
741 if (options & MagicPacket) |
|
742 wol->wolopts |= WAKE_MAGIC; |
|
743 |
|
744 options = RTL_R8(Config5); |
|
745 if (options & UWF) |
|
746 wol->wolopts |= WAKE_UCAST; |
|
747 if (options & BWF) |
|
748 wol->wolopts |= WAKE_BCAST; |
|
749 if (options & MWF) |
|
750 wol->wolopts |= WAKE_MCAST; |
|
751 |
|
752 out_unlock: |
|
753 spin_unlock_irq(&tp->lock); |
|
754 } |
|
755 |
|
756 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
757 { |
|
758 struct rtl8169_private *tp = netdev_priv(dev); |
|
759 void __iomem *ioaddr = tp->mmio_addr; |
|
760 unsigned int i; |
|
761 static struct { |
|
762 u32 opt; |
|
763 u16 reg; |
|
764 u8 mask; |
|
765 } cfg[] = { |
|
766 { WAKE_ANY, Config1, PMEnable }, |
|
767 { WAKE_PHY, Config3, LinkUp }, |
|
768 { WAKE_MAGIC, Config3, MagicPacket }, |
|
769 { WAKE_UCAST, Config5, UWF }, |
|
770 { WAKE_BCAST, Config5, BWF }, |
|
771 { WAKE_MCAST, Config5, MWF }, |
|
772 { WAKE_ANY, Config5, LanWake } |
|
773 }; |
|
774 |
|
775 spin_lock_irq(&tp->lock); |
|
776 |
|
777 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
778 |
|
779 for (i = 0; i < ARRAY_SIZE(cfg); i++) { |
|
780 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
|
781 if (wol->wolopts & cfg[i].opt) |
|
782 options |= cfg[i].mask; |
|
783 RTL_W8(cfg[i].reg, options); |
|
784 } |
|
785 |
|
786 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
787 |
|
788 if (wol->wolopts) |
|
789 tp->features |= RTL_FEATURE_WOL; |
|
790 else |
|
791 tp->features &= ~RTL_FEATURE_WOL; |
|
792 |
|
793 spin_unlock_irq(&tp->lock); |
|
794 |
|
795 return 0; |
|
796 } |
|
797 |
|
798 static void rtl8169_get_drvinfo(struct net_device *dev, |
|
799 struct ethtool_drvinfo *info) |
|
800 { |
|
801 struct rtl8169_private *tp = netdev_priv(dev); |
|
802 |
|
803 strcpy(info->driver, MODULENAME); |
|
804 strcpy(info->version, RTL8169_VERSION); |
|
805 strcpy(info->bus_info, pci_name(tp->pci_dev)); |
|
806 } |
|
807 |
|
808 static int rtl8169_get_regs_len(struct net_device *dev) |
|
809 { |
|
810 return R8169_REGS_SIZE; |
|
811 } |
|
812 |
|
813 static int rtl8169_set_speed_tbi(struct net_device *dev, |
|
814 u8 autoneg, u16 speed, u8 duplex) |
|
815 { |
|
816 struct rtl8169_private *tp = netdev_priv(dev); |
|
817 void __iomem *ioaddr = tp->mmio_addr; |
|
818 int ret = 0; |
|
819 u32 reg; |
|
820 |
|
821 reg = RTL_R32(TBICSR); |
|
822 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
|
823 (duplex == DUPLEX_FULL)) { |
|
824 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
|
825 } else if (autoneg == AUTONEG_ENABLE) |
|
826 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); |
|
827 else { |
|
828 if (netif_msg_link(tp)) { |
|
829 printk(KERN_WARNING "%s: " |
|
830 "incorrect speed setting refused in TBI mode\n", |
|
831 dev->name); |
|
832 } |
|
833 ret = -EOPNOTSUPP; |
|
834 } |
|
835 |
|
836 return ret; |
|
837 } |
|
838 |
|
839 static int rtl8169_set_speed_xmii(struct net_device *dev, |
|
840 u8 autoneg, u16 speed, u8 duplex) |
|
841 { |
|
842 struct rtl8169_private *tp = netdev_priv(dev); |
|
843 void __iomem *ioaddr = tp->mmio_addr; |
|
844 int giga_ctrl, bmcr; |
|
845 |
|
846 if (autoneg == AUTONEG_ENABLE) { |
|
847 int auto_nego; |
|
848 |
|
849 auto_nego = mdio_read(ioaddr, MII_ADVERTISE); |
|
850 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
851 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
852 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
853 |
|
854 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); |
|
855 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
856 |
|
857 /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
|
858 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) && |
|
859 (tp->mac_version != RTL_GIGA_MAC_VER_08) && |
|
860 (tp->mac_version != RTL_GIGA_MAC_VER_09) && |
|
861 (tp->mac_version != RTL_GIGA_MAC_VER_10) && |
|
862 (tp->mac_version != RTL_GIGA_MAC_VER_13) && |
|
863 (tp->mac_version != RTL_GIGA_MAC_VER_14) && |
|
864 (tp->mac_version != RTL_GIGA_MAC_VER_15) && |
|
865 (tp->mac_version != RTL_GIGA_MAC_VER_16)) { |
|
866 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
|
867 } else if (netif_msg_link(tp)) { |
|
868 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", |
|
869 dev->name); |
|
870 } |
|
871 |
|
872 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
|
873 |
|
874 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
|
875 (tp->mac_version == RTL_GIGA_MAC_VER_12) || |
|
876 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { |
|
877 /* |
|
878 * Wake up the PHY. |
|
879 * Vendor specific (0x1f) and reserved (0x0e) MII |
|
880 * registers. |
|
881 */ |
|
882 mdio_write(ioaddr, 0x1f, 0x0000); |
|
883 mdio_write(ioaddr, 0x0e, 0x0000); |
|
884 } |
|
885 |
|
886 tp->phy_auto_nego_reg = auto_nego; |
|
887 |
|
888 mdio_write(ioaddr, MII_ADVERTISE, auto_nego); |
|
889 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); |
|
890 } else { |
|
891 giga_ctrl = 0; |
|
892 |
|
893 if (speed == SPEED_10) |
|
894 bmcr = 0; |
|
895 else if (speed == SPEED_100) |
|
896 bmcr = BMCR_SPEED100; |
|
897 else |
|
898 return -EINVAL; |
|
899 |
|
900 if (duplex == DUPLEX_FULL) |
|
901 bmcr |= BMCR_FULLDPLX; |
|
902 |
|
903 mdio_write(ioaddr, 0x1f, 0x0000); |
|
904 } |
|
905 |
|
906 tp->phy_1000_ctrl_reg = giga_ctrl; |
|
907 |
|
908 mdio_write(ioaddr, MII_BMCR, bmcr); |
|
909 |
|
910 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
911 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { |
|
912 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
|
913 mdio_write(ioaddr, 0x17, 0x2138); |
|
914 mdio_write(ioaddr, 0x0e, 0x0260); |
|
915 } else { |
|
916 mdio_write(ioaddr, 0x17, 0x2108); |
|
917 mdio_write(ioaddr, 0x0e, 0x0000); |
|
918 } |
|
919 } |
|
920 |
|
921 return 0; |
|
922 } |
|
923 |
|
924 static int rtl8169_set_speed(struct net_device *dev, |
|
925 u8 autoneg, u16 speed, u8 duplex) |
|
926 { |
|
927 struct rtl8169_private *tp = netdev_priv(dev); |
|
928 int ret; |
|
929 |
|
930 ret = tp->set_speed(dev, autoneg, speed, duplex); |
|
931 |
|
932 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
933 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
934 |
|
935 return ret; |
|
936 } |
|
937 |
|
938 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
939 { |
|
940 struct rtl8169_private *tp = netdev_priv(dev); |
|
941 unsigned long flags; |
|
942 int ret; |
|
943 |
|
944 spin_lock_irqsave(&tp->lock, flags); |
|
945 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); |
|
946 spin_unlock_irqrestore(&tp->lock, flags); |
|
947 |
|
948 return ret; |
|
949 } |
|
950 |
|
951 static u32 rtl8169_get_rx_csum(struct net_device *dev) |
|
952 { |
|
953 struct rtl8169_private *tp = netdev_priv(dev); |
|
954 |
|
955 return tp->cp_cmd & RxChkSum; |
|
956 } |
|
957 |
|
958 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) |
|
959 { |
|
960 struct rtl8169_private *tp = netdev_priv(dev); |
|
961 void __iomem *ioaddr = tp->mmio_addr; |
|
962 unsigned long flags; |
|
963 |
|
964 spin_lock_irqsave(&tp->lock, flags); |
|
965 |
|
966 if (data) |
|
967 tp->cp_cmd |= RxChkSum; |
|
968 else |
|
969 tp->cp_cmd &= ~RxChkSum; |
|
970 |
|
971 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
972 RTL_R16(CPlusCmd); |
|
973 |
|
974 spin_unlock_irqrestore(&tp->lock, flags); |
|
975 |
|
976 return 0; |
|
977 } |
|
978 |
|
979 #ifdef CONFIG_R8169_VLAN |
|
980 |
|
981 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
982 struct sk_buff *skb) |
|
983 { |
|
984 return (tp->vlgrp && vlan_tx_tag_present(skb)) ? |
|
985 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
|
986 } |
|
987 |
|
988 static void rtl8169_vlan_rx_register(struct net_device *dev, |
|
989 struct vlan_group *grp) |
|
990 { |
|
991 struct rtl8169_private *tp = netdev_priv(dev); |
|
992 void __iomem *ioaddr = tp->mmio_addr; |
|
993 unsigned long flags; |
|
994 |
|
995 spin_lock_irqsave(&tp->lock, flags); |
|
996 tp->vlgrp = grp; |
|
997 if (tp->vlgrp) |
|
998 tp->cp_cmd |= RxVlan; |
|
999 else |
|
1000 tp->cp_cmd &= ~RxVlan; |
|
1001 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
1002 RTL_R16(CPlusCmd); |
|
1003 spin_unlock_irqrestore(&tp->lock, flags); |
|
1004 } |
|
1005 |
|
1006 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
1007 struct sk_buff *skb) |
|
1008 { |
|
1009 u32 opts2 = le32_to_cpu(desc->opts2); |
|
1010 struct vlan_group *vlgrp = tp->vlgrp; |
|
1011 int ret; |
|
1012 |
|
1013 if (vlgrp && (opts2 & RxVlanTag)) { |
|
1014 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff)); |
|
1015 ret = 0; |
|
1016 } else |
|
1017 ret = -1; |
|
1018 desc->opts2 = 0; |
|
1019 return ret; |
|
1020 } |
|
1021 |
|
1022 #else /* !CONFIG_R8169_VLAN */ |
|
1023 |
|
1024 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
1025 struct sk_buff *skb) |
|
1026 { |
|
1027 return 0; |
|
1028 } |
|
1029 |
|
1030 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
1031 struct sk_buff *skb) |
|
1032 { |
|
1033 return -1; |
|
1034 } |
|
1035 |
|
1036 #endif |
|
1037 |
|
1038 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1039 { |
|
1040 struct rtl8169_private *tp = netdev_priv(dev); |
|
1041 void __iomem *ioaddr = tp->mmio_addr; |
|
1042 u32 status; |
|
1043 |
|
1044 cmd->supported = |
|
1045 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
|
1046 cmd->port = PORT_FIBRE; |
|
1047 cmd->transceiver = XCVR_INTERNAL; |
|
1048 |
|
1049 status = RTL_R32(TBICSR); |
|
1050 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
|
1051 cmd->autoneg = !!(status & TBINwEnable); |
|
1052 |
|
1053 cmd->speed = SPEED_1000; |
|
1054 cmd->duplex = DUPLEX_FULL; /* Always set */ |
|
1055 |
|
1056 return 0; |
|
1057 } |
|
1058 |
|
1059 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1060 { |
|
1061 struct rtl8169_private *tp = netdev_priv(dev); |
|
1062 |
|
1063 return mii_ethtool_gset(&tp->mii, cmd); |
|
1064 } |
|
1065 |
|
1066 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1067 { |
|
1068 struct rtl8169_private *tp = netdev_priv(dev); |
|
1069 unsigned long flags; |
|
1070 int rc; |
|
1071 |
|
1072 spin_lock_irqsave(&tp->lock, flags); |
|
1073 |
|
1074 rc = tp->get_settings(dev, cmd); |
|
1075 |
|
1076 spin_unlock_irqrestore(&tp->lock, flags); |
|
1077 return rc; |
|
1078 } |
|
1079 |
|
1080 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
|
1081 void *p) |
|
1082 { |
|
1083 struct rtl8169_private *tp = netdev_priv(dev); |
|
1084 unsigned long flags; |
|
1085 |
|
1086 if (regs->len > R8169_REGS_SIZE) |
|
1087 regs->len = R8169_REGS_SIZE; |
|
1088 |
|
1089 spin_lock_irqsave(&tp->lock, flags); |
|
1090 memcpy_fromio(p, tp->mmio_addr, regs->len); |
|
1091 spin_unlock_irqrestore(&tp->lock, flags); |
|
1092 } |
|
1093 |
|
1094 static u32 rtl8169_get_msglevel(struct net_device *dev) |
|
1095 { |
|
1096 struct rtl8169_private *tp = netdev_priv(dev); |
|
1097 |
|
1098 return tp->msg_enable; |
|
1099 } |
|
1100 |
|
1101 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) |
|
1102 { |
|
1103 struct rtl8169_private *tp = netdev_priv(dev); |
|
1104 |
|
1105 tp->msg_enable = value; |
|
1106 } |
|
1107 |
|
1108 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
|
1109 "tx_packets", |
|
1110 "rx_packets", |
|
1111 "tx_errors", |
|
1112 "rx_errors", |
|
1113 "rx_missed", |
|
1114 "align_errors", |
|
1115 "tx_single_collisions", |
|
1116 "tx_multi_collisions", |
|
1117 "unicast", |
|
1118 "broadcast", |
|
1119 "multicast", |
|
1120 "tx_aborted", |
|
1121 "tx_underrun", |
|
1122 }; |
|
1123 |
|
1124 static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
|
1125 { |
|
1126 switch (sset) { |
|
1127 case ETH_SS_STATS: |
|
1128 return ARRAY_SIZE(rtl8169_gstrings); |
|
1129 default: |
|
1130 return -EOPNOTSUPP; |
|
1131 } |
|
1132 } |
|
1133 |
|
1134 static void rtl8169_update_counters(struct net_device *dev) |
|
1135 { |
|
1136 struct rtl8169_private *tp = netdev_priv(dev); |
|
1137 void __iomem *ioaddr = tp->mmio_addr; |
|
1138 struct rtl8169_counters *counters; |
|
1139 dma_addr_t paddr; |
|
1140 u32 cmd; |
|
1141 int wait = 1000; |
|
1142 |
|
1143 /* |
|
1144 * Some chips are unable to dump tally counters when the receiver |
|
1145 * is disabled. |
|
1146 */ |
|
1147 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) |
|
1148 return; |
|
1149 |
|
1150 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); |
|
1151 if (!counters) |
|
1152 return; |
|
1153 |
|
1154 RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
|
1155 cmd = (u64)paddr & DMA_32BIT_MASK; |
|
1156 RTL_W32(CounterAddrLow, cmd); |
|
1157 RTL_W32(CounterAddrLow, cmd | CounterDump); |
|
1158 |
|
1159 while (wait--) { |
|
1160 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { |
|
1161 /* copy updated counters */ |
|
1162 memcpy(&tp->counters, counters, sizeof(*counters)); |
|
1163 break; |
|
1164 } |
|
1165 udelay(10); |
|
1166 } |
|
1167 |
|
1168 RTL_W32(CounterAddrLow, 0); |
|
1169 RTL_W32(CounterAddrHigh, 0); |
|
1170 |
|
1171 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); |
|
1172 } |
|
1173 |
|
1174 static void rtl8169_get_ethtool_stats(struct net_device *dev, |
|
1175 struct ethtool_stats *stats, u64 *data) |
|
1176 { |
|
1177 struct rtl8169_private *tp = netdev_priv(dev); |
|
1178 |
|
1179 ASSERT_RTNL(); |
|
1180 |
|
1181 rtl8169_update_counters(dev); |
|
1182 |
|
1183 data[0] = le64_to_cpu(tp->counters.tx_packets); |
|
1184 data[1] = le64_to_cpu(tp->counters.rx_packets); |
|
1185 data[2] = le64_to_cpu(tp->counters.tx_errors); |
|
1186 data[3] = le32_to_cpu(tp->counters.rx_errors); |
|
1187 data[4] = le16_to_cpu(tp->counters.rx_missed); |
|
1188 data[5] = le16_to_cpu(tp->counters.align_errors); |
|
1189 data[6] = le32_to_cpu(tp->counters.tx_one_collision); |
|
1190 data[7] = le32_to_cpu(tp->counters.tx_multi_collision); |
|
1191 data[8] = le64_to_cpu(tp->counters.rx_unicast); |
|
1192 data[9] = le64_to_cpu(tp->counters.rx_broadcast); |
|
1193 data[10] = le32_to_cpu(tp->counters.rx_multicast); |
|
1194 data[11] = le16_to_cpu(tp->counters.tx_aborted); |
|
1195 data[12] = le16_to_cpu(tp->counters.tx_underun); |
|
1196 } |
|
1197 |
|
1198 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
1199 { |
|
1200 switch(stringset) { |
|
1201 case ETH_SS_STATS: |
|
1202 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
|
1203 break; |
|
1204 } |
|
1205 } |
|
1206 |
|
1207 static const struct ethtool_ops rtl8169_ethtool_ops = { |
|
1208 .get_drvinfo = rtl8169_get_drvinfo, |
|
1209 .get_regs_len = rtl8169_get_regs_len, |
|
1210 .get_link = ethtool_op_get_link, |
|
1211 .get_settings = rtl8169_get_settings, |
|
1212 .set_settings = rtl8169_set_settings, |
|
1213 .get_msglevel = rtl8169_get_msglevel, |
|
1214 .set_msglevel = rtl8169_set_msglevel, |
|
1215 .get_rx_csum = rtl8169_get_rx_csum, |
|
1216 .set_rx_csum = rtl8169_set_rx_csum, |
|
1217 .set_tx_csum = ethtool_op_set_tx_csum, |
|
1218 .set_sg = ethtool_op_set_sg, |
|
1219 .set_tso = ethtool_op_set_tso, |
|
1220 .get_regs = rtl8169_get_regs, |
|
1221 .get_wol = rtl8169_get_wol, |
|
1222 .set_wol = rtl8169_set_wol, |
|
1223 .get_strings = rtl8169_get_strings, |
|
1224 .get_sset_count = rtl8169_get_sset_count, |
|
1225 .get_ethtool_stats = rtl8169_get_ethtool_stats, |
|
1226 }; |
|
1227 |
|
1228 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, |
|
1229 int bitnum, int bitval) |
|
1230 { |
|
1231 int val; |
|
1232 |
|
1233 val = mdio_read(ioaddr, reg); |
|
1234 val = (bitval == 1) ? |
|
1235 val | (bitval << bitnum) : val & ~(0x0001 << bitnum); |
|
1236 mdio_write(ioaddr, reg, val & 0xffff); |
|
1237 } |
|
1238 |
|
1239 static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
|
1240 void __iomem *ioaddr) |
|
1241 { |
|
1242 /* |
|
1243 * The driver currently handles the 8168Bf and the 8168Be identically |
|
1244 * but they can be identified more specifically through the test below |
|
1245 * if needed: |
|
1246 * |
|
1247 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
|
1248 * |
|
1249 * Same thing for the 8101Eb and the 8101Ec: |
|
1250 * |
|
1251 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
|
1252 */ |
|
1253 const struct { |
|
1254 u32 mask; |
|
1255 u32 val; |
|
1256 int mac_version; |
|
1257 } mac_info[] = { |
|
1258 /* 8168B family. */ |
|
1259 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
|
1260 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
|
1261 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, |
|
1262 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 }, |
|
1263 |
|
1264 /* 8168B family. */ |
|
1265 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, |
|
1266 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, |
|
1267 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, |
|
1268 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, |
|
1269 |
|
1270 /* 8101 family. */ |
|
1271 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
|
1272 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, |
|
1273 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, |
|
1274 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, |
|
1275 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, |
|
1276 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, |
|
1277 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
|
1278 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
|
1279 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
|
1280 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
|
1281 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, |
|
1282 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
|
1283 /* FIXME: where did these entries come from ? -- FR */ |
|
1284 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, |
|
1285 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, |
|
1286 |
|
1287 /* 8110 family. */ |
|
1288 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, |
|
1289 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, |
|
1290 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, |
|
1291 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, |
|
1292 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, |
|
1293 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, |
|
1294 |
|
1295 /* Catch-all */ |
|
1296 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } |
|
1297 }, *p = mac_info; |
|
1298 u32 reg; |
|
1299 |
|
1300 reg = RTL_R32(TxConfig); |
|
1301 while ((reg & p->mask) != p->val) |
|
1302 p++; |
|
1303 tp->mac_version = p->mac_version; |
|
1304 } |
|
1305 |
|
1306 static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
|
1307 { |
|
1308 dprintk("mac_version = 0x%02x\n", tp->mac_version); |
|
1309 } |
|
1310 |
|
1311 struct phy_reg { |
|
1312 u16 reg; |
|
1313 u16 val; |
|
1314 }; |
|
1315 |
|
1316 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len) |
|
1317 { |
|
1318 while (len-- > 0) { |
|
1319 mdio_write(ioaddr, regs->reg, regs->val); |
|
1320 regs++; |
|
1321 } |
|
1322 } |
|
1323 |
|
1324 static void rtl8169s_hw_phy_config(void __iomem *ioaddr) |
|
1325 { |
|
1326 struct { |
|
1327 u16 regs[5]; /* Beware of bit-sign propagation */ |
|
1328 } phy_magic[5] = { { |
|
1329 { 0x0000, //w 4 15 12 0 |
|
1330 0x00a1, //w 3 15 0 00a1 |
|
1331 0x0008, //w 2 15 0 0008 |
|
1332 0x1020, //w 1 15 0 1020 |
|
1333 0x1000 } },{ //w 0 15 0 1000 |
|
1334 { 0x7000, //w 4 15 12 7 |
|
1335 0xff41, //w 3 15 0 ff41 |
|
1336 0xde60, //w 2 15 0 de60 |
|
1337 0x0140, //w 1 15 0 0140 |
|
1338 0x0077 } },{ //w 0 15 0 0077 |
|
1339 { 0xa000, //w 4 15 12 a |
|
1340 0xdf01, //w 3 15 0 df01 |
|
1341 0xdf20, //w 2 15 0 df20 |
|
1342 0xff95, //w 1 15 0 ff95 |
|
1343 0xfa00 } },{ //w 0 15 0 fa00 |
|
1344 { 0xb000, //w 4 15 12 b |
|
1345 0xff41, //w 3 15 0 ff41 |
|
1346 0xde20, //w 2 15 0 de20 |
|
1347 0x0140, //w 1 15 0 0140 |
|
1348 0x00bb } },{ //w 0 15 0 00bb |
|
1349 { 0xf000, //w 4 15 12 f |
|
1350 0xdf01, //w 3 15 0 df01 |
|
1351 0xdf20, //w 2 15 0 df20 |
|
1352 0xff95, //w 1 15 0 ff95 |
|
1353 0xbf00 } //w 0 15 0 bf00 |
|
1354 } |
|
1355 }, *p = phy_magic; |
|
1356 unsigned int i; |
|
1357 |
|
1358 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1 |
|
1359 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000 |
|
1360 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7 |
|
1361 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
|
1362 |
|
1363 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) { |
|
1364 int val, pos = 4; |
|
1365 |
|
1366 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); |
|
1367 mdio_write(ioaddr, pos, val); |
|
1368 while (--pos >= 0) |
|
1369 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); |
|
1370 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 |
|
1371 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
|
1372 } |
|
1373 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0 |
|
1374 } |
|
1375 |
|
1376 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) |
|
1377 { |
|
1378 struct phy_reg phy_reg_init[] = { |
|
1379 { 0x1f, 0x0002 }, |
|
1380 { 0x01, 0x90d0 }, |
|
1381 { 0x1f, 0x0000 } |
|
1382 }; |
|
1383 |
|
1384 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1385 } |
|
1386 |
|
1387 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr) |
|
1388 { |
|
1389 struct phy_reg phy_reg_init[] = { |
|
1390 { 0x1f, 0x0000 }, |
|
1391 { 0x1d, 0x0f00 }, |
|
1392 { 0x1f, 0x0002 }, |
|
1393 { 0x0c, 0x1ec8 }, |
|
1394 { 0x1f, 0x0000 } |
|
1395 }; |
|
1396 |
|
1397 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1398 } |
|
1399 |
|
1400 static void rtl8168c_hw_phy_config(void __iomem *ioaddr) |
|
1401 { |
|
1402 struct phy_reg phy_reg_init[] = { |
|
1403 { 0x1f, 0x0001 }, |
|
1404 { 0x12, 0x2300 }, |
|
1405 { 0x1f, 0x0002 }, |
|
1406 { 0x00, 0x88d4 }, |
|
1407 { 0x01, 0x82b1 }, |
|
1408 { 0x03, 0x7002 }, |
|
1409 { 0x08, 0x9e30 }, |
|
1410 { 0x09, 0x01f0 }, |
|
1411 { 0x0a, 0x5500 }, |
|
1412 { 0x0c, 0x00c8 }, |
|
1413 { 0x1f, 0x0003 }, |
|
1414 { 0x12, 0xc096 }, |
|
1415 { 0x16, 0x000a }, |
|
1416 { 0x1f, 0x0000 } |
|
1417 }; |
|
1418 |
|
1419 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1420 } |
|
1421 |
|
1422 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr) |
|
1423 { |
|
1424 struct phy_reg phy_reg_init[] = { |
|
1425 { 0x1f, 0x0000 }, |
|
1426 { 0x12, 0x2300 }, |
|
1427 { 0x1f, 0x0003 }, |
|
1428 { 0x16, 0x0f0a }, |
|
1429 { 0x1f, 0x0000 }, |
|
1430 { 0x1f, 0x0002 }, |
|
1431 { 0x0c, 0x7eb8 }, |
|
1432 { 0x1f, 0x0000 } |
|
1433 }; |
|
1434 |
|
1435 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1436 } |
|
1437 |
|
1438 static void rtl8102e_hw_phy_config(void __iomem *ioaddr) |
|
1439 { |
|
1440 struct phy_reg phy_reg_init[] = { |
|
1441 { 0x1f, 0x0003 }, |
|
1442 { 0x08, 0x441d }, |
|
1443 { 0x01, 0x9100 }, |
|
1444 { 0x1f, 0x0000 } |
|
1445 }; |
|
1446 |
|
1447 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1448 mdio_patch(ioaddr, 0x11, 1 << 12); |
|
1449 mdio_patch(ioaddr, 0x19, 1 << 13); |
|
1450 |
|
1451 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1452 } |
|
1453 |
|
1454 static void rtl_hw_phy_config(struct net_device *dev) |
|
1455 { |
|
1456 struct rtl8169_private *tp = netdev_priv(dev); |
|
1457 void __iomem *ioaddr = tp->mmio_addr; |
|
1458 |
|
1459 rtl8169_print_mac_version(tp); |
|
1460 |
|
1461 switch (tp->mac_version) { |
|
1462 case RTL_GIGA_MAC_VER_01: |
|
1463 break; |
|
1464 case RTL_GIGA_MAC_VER_02: |
|
1465 case RTL_GIGA_MAC_VER_03: |
|
1466 rtl8169s_hw_phy_config(ioaddr); |
|
1467 break; |
|
1468 case RTL_GIGA_MAC_VER_04: |
|
1469 rtl8169sb_hw_phy_config(ioaddr); |
|
1470 break; |
|
1471 case RTL_GIGA_MAC_VER_07: |
|
1472 case RTL_GIGA_MAC_VER_08: |
|
1473 case RTL_GIGA_MAC_VER_09: |
|
1474 rtl8102e_hw_phy_config(ioaddr); |
|
1475 break; |
|
1476 case RTL_GIGA_MAC_VER_18: |
|
1477 rtl8168cp_hw_phy_config(ioaddr); |
|
1478 break; |
|
1479 case RTL_GIGA_MAC_VER_19: |
|
1480 rtl8168c_hw_phy_config(ioaddr); |
|
1481 break; |
|
1482 case RTL_GIGA_MAC_VER_20: |
|
1483 rtl8168cx_hw_phy_config(ioaddr); |
|
1484 break; |
|
1485 default: |
|
1486 break; |
|
1487 } |
|
1488 } |
|
1489 |
|
1490 static void rtl8169_phy_timer(unsigned long __opaque) |
|
1491 { |
|
1492 struct net_device *dev = (struct net_device *)__opaque; |
|
1493 struct rtl8169_private *tp = netdev_priv(dev); |
|
1494 struct timer_list *timer = &tp->timer; |
|
1495 void __iomem *ioaddr = tp->mmio_addr; |
|
1496 unsigned long timeout = RTL8169_PHY_TIMEOUT; |
|
1497 |
|
1498 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
|
1499 |
|
1500 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
1501 return; |
|
1502 |
|
1503 if (!tp->ecdev) |
|
1504 spin_lock_irq(&tp->lock); |
|
1505 |
|
1506 if (tp->phy_reset_pending(ioaddr)) { |
|
1507 /* |
|
1508 * A busy loop could burn quite a few cycles on nowadays CPU. |
|
1509 * Let's delay the execution of the timer for a few ticks. |
|
1510 */ |
|
1511 timeout = HZ/10; |
|
1512 goto out_mod_timer; |
|
1513 } |
|
1514 |
|
1515 if (tp->link_ok(ioaddr)) |
|
1516 goto out_unlock; |
|
1517 |
|
1518 if (netif_msg_link(tp)) |
|
1519 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); |
|
1520 |
|
1521 tp->phy_reset_enable(ioaddr); |
|
1522 |
|
1523 out_mod_timer: |
|
1524 if (!tp->ecdev) |
|
1525 mod_timer(timer, jiffies + timeout); |
|
1526 out_unlock: |
|
1527 if (!tp->ecdev) |
|
1528 spin_unlock_irq(&tp->lock); |
|
1529 } |
|
1530 |
|
1531 static inline void rtl8169_delete_timer(struct net_device *dev) |
|
1532 { |
|
1533 struct rtl8169_private *tp = netdev_priv(dev); |
|
1534 struct timer_list *timer = &tp->timer; |
|
1535 |
|
1536 if (tp->ecdev || tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
1537 return; |
|
1538 |
|
1539 del_timer_sync(timer); |
|
1540 } |
|
1541 |
|
1542 static inline void rtl8169_request_timer(struct net_device *dev) |
|
1543 { |
|
1544 struct rtl8169_private *tp = netdev_priv(dev); |
|
1545 struct timer_list *timer = &tp->timer; |
|
1546 |
|
1547 if (tp->ecdev || tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
1548 return; |
|
1549 |
|
1550 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
1551 } |
|
1552 |
|
1553 static void ec_poll(struct net_device *dev) |
|
1554 { |
|
1555 struct rtl8169_private *tp = netdev_priv(dev); |
|
1556 struct pci_dev *pdev = tp->pci_dev; |
|
1557 |
|
1558 rtl8169_interrupt(pdev->irq, dev); |
|
1559 |
|
1560 if (jiffies - tp->ec_watchdog_jiffies >= 2 * HZ) { |
|
1561 rtl8169_phy_timer((unsigned long) dev); |
|
1562 tp->ec_watchdog_jiffies = jiffies; |
|
1563 } |
|
1564 } |
|
1565 |
|
1566 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
1567 /* |
|
1568 * Polling 'interrupt' - used by things like netconsole to send skbs |
|
1569 * without having to re-enable interrupts. It's not called while |
|
1570 * the interrupt routine is executing. |
|
1571 */ |
|
1572 static void rtl8169_netpoll(struct net_device *dev) |
|
1573 { |
|
1574 struct rtl8169_private *tp = netdev_priv(dev); |
|
1575 struct pci_dev *pdev = tp->pci_dev; |
|
1576 |
|
1577 disable_irq(pdev->irq); |
|
1578 rtl8169_interrupt(pdev->irq, dev); |
|
1579 enable_irq(pdev->irq); |
|
1580 } |
|
1581 #endif |
|
1582 |
|
1583 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
|
1584 void __iomem *ioaddr) |
|
1585 { |
|
1586 iounmap(ioaddr); |
|
1587 pci_release_regions(pdev); |
|
1588 pci_disable_device(pdev); |
|
1589 free_netdev(dev); |
|
1590 } |
|
1591 |
|
1592 static void rtl8169_phy_reset(struct net_device *dev, |
|
1593 struct rtl8169_private *tp) |
|
1594 { |
|
1595 void __iomem *ioaddr = tp->mmio_addr; |
|
1596 unsigned int i; |
|
1597 |
|
1598 tp->phy_reset_enable(ioaddr); |
|
1599 for (i = 0; i < 100; i++) { |
|
1600 if (!tp->phy_reset_pending(ioaddr)) |
|
1601 return; |
|
1602 msleep(1); |
|
1603 } |
|
1604 if (netif_msg_link(tp)) |
|
1605 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); |
|
1606 } |
|
1607 |
|
1608 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
|
1609 { |
|
1610 void __iomem *ioaddr = tp->mmio_addr; |
|
1611 |
|
1612 rtl_hw_phy_config(dev); |
|
1613 |
|
1614 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
|
1615 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
1616 RTL_W8(0x82, 0x01); |
|
1617 } |
|
1618 |
|
1619 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
|
1620 |
|
1621 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
1622 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
|
1623 |
|
1624 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
|
1625 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
1626 RTL_W8(0x82, 0x01); |
|
1627 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
|
1628 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 |
|
1629 } |
|
1630 |
|
1631 rtl8169_phy_reset(dev, tp); |
|
1632 |
|
1633 /* |
|
1634 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet |
|
1635 * only 8101. Don't panic. |
|
1636 */ |
|
1637 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); |
|
1638 |
|
1639 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) |
|
1640 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); |
|
1641 } |
|
1642 |
|
1643 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
|
1644 { |
|
1645 void __iomem *ioaddr = tp->mmio_addr; |
|
1646 u32 high; |
|
1647 u32 low; |
|
1648 |
|
1649 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); |
|
1650 high = addr[4] | (addr[5] << 8); |
|
1651 |
|
1652 spin_lock_irq(&tp->lock); |
|
1653 |
|
1654 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1655 RTL_W32(MAC0, low); |
|
1656 RTL_W32(MAC4, high); |
|
1657 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1658 |
|
1659 spin_unlock_irq(&tp->lock); |
|
1660 } |
|
1661 |
|
1662 static int rtl_set_mac_address(struct net_device *dev, void *p) |
|
1663 { |
|
1664 struct rtl8169_private *tp = netdev_priv(dev); |
|
1665 struct sockaddr *addr = p; |
|
1666 |
|
1667 if (!is_valid_ether_addr(addr->sa_data)) |
|
1668 return -EADDRNOTAVAIL; |
|
1669 |
|
1670 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
1671 |
|
1672 rtl_rar_set(tp, dev->dev_addr); |
|
1673 |
|
1674 return 0; |
|
1675 } |
|
1676 |
|
1677 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
|
1678 { |
|
1679 struct rtl8169_private *tp = netdev_priv(dev); |
|
1680 struct mii_ioctl_data *data = if_mii(ifr); |
|
1681 |
|
1682 if (!netif_running(dev)) |
|
1683 return -ENODEV; |
|
1684 |
|
1685 switch (cmd) { |
|
1686 case SIOCGMIIPHY: |
|
1687 data->phy_id = 32; /* Internal PHY */ |
|
1688 return 0; |
|
1689 |
|
1690 case SIOCGMIIREG: |
|
1691 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); |
|
1692 return 0; |
|
1693 |
|
1694 case SIOCSMIIREG: |
|
1695 if (!capable(CAP_NET_ADMIN)) |
|
1696 return -EPERM; |
|
1697 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); |
|
1698 return 0; |
|
1699 } |
|
1700 return -EOPNOTSUPP; |
|
1701 } |
|
1702 |
|
1703 static const struct rtl_cfg_info { |
|
1704 void (*hw_start)(struct net_device *); |
|
1705 unsigned int region; |
|
1706 unsigned int align; |
|
1707 u16 intr_event; |
|
1708 u16 napi_event; |
|
1709 unsigned features; |
|
1710 u8 default_ver; |
|
1711 } rtl_cfg_infos [] = { |
|
1712 [RTL_CFG_0] = { |
|
1713 .hw_start = rtl_hw_start_8169, |
|
1714 .region = 1, |
|
1715 .align = 0, |
|
1716 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
1717 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
1718 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
1719 .features = RTL_FEATURE_GMII, |
|
1720 .default_ver = RTL_GIGA_MAC_VER_01, |
|
1721 }, |
|
1722 [RTL_CFG_1] = { |
|
1723 .hw_start = rtl_hw_start_8168, |
|
1724 .region = 2, |
|
1725 .align = 8, |
|
1726 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
1727 TxErr | TxOK | RxOK | RxErr, |
|
1728 .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
|
1729 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
|
1730 .default_ver = RTL_GIGA_MAC_VER_11, |
|
1731 }, |
|
1732 [RTL_CFG_2] = { |
|
1733 .hw_start = rtl_hw_start_8101, |
|
1734 .region = 2, |
|
1735 .align = 8, |
|
1736 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | |
|
1737 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
1738 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
1739 .features = RTL_FEATURE_MSI, |
|
1740 .default_ver = RTL_GIGA_MAC_VER_13, |
|
1741 } |
|
1742 }; |
|
1743 |
|
1744 /* Cfg9346_Unlock assumed. */ |
|
1745 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, |
|
1746 const struct rtl_cfg_info *cfg) |
|
1747 { |
|
1748 unsigned msi = 0; |
|
1749 u8 cfg2; |
|
1750 |
|
1751 cfg2 = RTL_R8(Config2) & ~MSIEnable; |
|
1752 if (cfg->features & RTL_FEATURE_MSI) { |
|
1753 if (pci_enable_msi(pdev)) { |
|
1754 dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); |
|
1755 } else { |
|
1756 cfg2 |= MSIEnable; |
|
1757 msi = RTL_FEATURE_MSI; |
|
1758 } |
|
1759 } |
|
1760 RTL_W8(Config2, cfg2); |
|
1761 return msi; |
|
1762 } |
|
1763 |
|
1764 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
|
1765 { |
|
1766 if (tp->features & RTL_FEATURE_MSI) { |
|
1767 pci_disable_msi(pdev); |
|
1768 tp->features &= ~RTL_FEATURE_MSI; |
|
1769 } |
|
1770 } |
|
1771 |
|
1772 static int __devinit |
|
1773 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
1774 { |
|
1775 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
|
1776 const unsigned int region = cfg->region; |
|
1777 struct rtl8169_private *tp; |
|
1778 struct mii_if_info *mii; |
|
1779 struct net_device *dev; |
|
1780 void __iomem *ioaddr; |
|
1781 unsigned int i; |
|
1782 int rc; |
|
1783 |
|
1784 if (netif_msg_drv(&debug)) { |
|
1785 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", |
|
1786 MODULENAME, RTL8169_VERSION); |
|
1787 } |
|
1788 |
|
1789 dev = alloc_etherdev(sizeof (*tp)); |
|
1790 if (!dev) { |
|
1791 if (netif_msg_drv(&debug)) |
|
1792 dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
|
1793 rc = -ENOMEM; |
|
1794 goto out; |
|
1795 } |
|
1796 |
|
1797 SET_NETDEV_DEV(dev, &pdev->dev); |
|
1798 tp = netdev_priv(dev); |
|
1799 tp->dev = dev; |
|
1800 tp->pci_dev = pdev; |
|
1801 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
|
1802 |
|
1803 mii = &tp->mii; |
|
1804 mii->dev = dev; |
|
1805 mii->mdio_read = rtl_mdio_read; |
|
1806 mii->mdio_write = rtl_mdio_write; |
|
1807 mii->phy_id_mask = 0x1f; |
|
1808 mii->reg_num_mask = 0x1f; |
|
1809 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); |
|
1810 |
|
1811 /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
1812 rc = pci_enable_device(pdev); |
|
1813 if (rc < 0) { |
|
1814 if (netif_msg_probe(tp)) |
|
1815 dev_err(&pdev->dev, "enable failure\n"); |
|
1816 goto err_out_free_dev_1; |
|
1817 } |
|
1818 |
|
1819 rc = pci_set_mwi(pdev); |
|
1820 if (rc < 0) |
|
1821 goto err_out_disable_2; |
|
1822 |
|
1823 /* make sure PCI base addr 1 is MMIO */ |
|
1824 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
|
1825 if (netif_msg_probe(tp)) { |
|
1826 dev_err(&pdev->dev, |
|
1827 "region #%d not an MMIO resource, aborting\n", |
|
1828 region); |
|
1829 } |
|
1830 rc = -ENODEV; |
|
1831 goto err_out_mwi_3; |
|
1832 } |
|
1833 |
|
1834 /* check for weird/broken PCI region reporting */ |
|
1835 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
|
1836 if (netif_msg_probe(tp)) { |
|
1837 dev_err(&pdev->dev, |
|
1838 "Invalid PCI region size(s), aborting\n"); |
|
1839 } |
|
1840 rc = -ENODEV; |
|
1841 goto err_out_mwi_3; |
|
1842 } |
|
1843 |
|
1844 rc = pci_request_regions(pdev, MODULENAME); |
|
1845 if (rc < 0) { |
|
1846 if (netif_msg_probe(tp)) |
|
1847 dev_err(&pdev->dev, "could not request regions.\n"); |
|
1848 goto err_out_mwi_3; |
|
1849 } |
|
1850 |
|
1851 tp->cp_cmd = PCIMulRW | RxChkSum; |
|
1852 |
|
1853 if ((sizeof(dma_addr_t) > 4) && |
|
1854 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) { |
|
1855 tp->cp_cmd |= PCIDAC; |
|
1856 dev->features |= NETIF_F_HIGHDMA; |
|
1857 } else { |
|
1858 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
|
1859 if (rc < 0) { |
|
1860 if (netif_msg_probe(tp)) { |
|
1861 dev_err(&pdev->dev, |
|
1862 "DMA configuration failed.\n"); |
|
1863 } |
|
1864 goto err_out_free_res_4; |
|
1865 } |
|
1866 } |
|
1867 |
|
1868 pci_set_master(pdev); |
|
1869 |
|
1870 /* ioremap MMIO region */ |
|
1871 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
|
1872 if (!ioaddr) { |
|
1873 if (netif_msg_probe(tp)) |
|
1874 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
|
1875 rc = -EIO; |
|
1876 goto err_out_free_res_4; |
|
1877 } |
|
1878 |
|
1879 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
|
1880 if (!tp->pcie_cap && netif_msg_probe(tp)) |
|
1881 dev_info(&pdev->dev, "no PCI Express capability\n"); |
|
1882 |
|
1883 RTL_W16(IntrMask, 0x0000); |
|
1884 |
|
1885 /* Soft reset the chip. */ |
|
1886 RTL_W8(ChipCmd, CmdReset); |
|
1887 |
|
1888 /* Check that the chip has finished the reset. */ |
|
1889 for (i = 0; i < 100; i++) { |
|
1890 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
1891 break; |
|
1892 msleep_interruptible(1); |
|
1893 } |
|
1894 |
|
1895 RTL_W16(IntrStatus, 0xffff); |
|
1896 |
|
1897 /* Identify chip attached to board */ |
|
1898 rtl8169_get_mac_version(tp, ioaddr); |
|
1899 |
|
1900 /* Use appropriate default if unknown */ |
|
1901 if (tp->mac_version == RTL_GIGA_MAC_NONE) { |
|
1902 if (netif_msg_probe(tp)) { |
|
1903 dev_notice(&pdev->dev, |
|
1904 "unknown MAC, using family default\n"); |
|
1905 } |
|
1906 tp->mac_version = cfg->default_ver; |
|
1907 } |
|
1908 |
|
1909 rtl8169_print_mac_version(tp); |
|
1910 |
|
1911 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { |
|
1912 if (tp->mac_version == rtl_chip_info[i].mac_version) |
|
1913 break; |
|
1914 } |
|
1915 if (i == ARRAY_SIZE(rtl_chip_info)) { |
|
1916 dev_err(&pdev->dev, |
|
1917 "driver bug, MAC version not found in rtl_chip_info\n"); |
|
1918 goto err_out_msi_5; |
|
1919 } |
|
1920 tp->chipset = i; |
|
1921 |
|
1922 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1923 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); |
|
1924 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); |
|
1925 tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
|
1926 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1927 |
|
1928 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && |
|
1929 (RTL_R8(PHYstatus) & TBI_Enable)) { |
|
1930 tp->set_speed = rtl8169_set_speed_tbi; |
|
1931 tp->get_settings = rtl8169_gset_tbi; |
|
1932 tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
|
1933 tp->phy_reset_pending = rtl8169_tbi_reset_pending; |
|
1934 tp->link_ok = rtl8169_tbi_link_ok; |
|
1935 |
|
1936 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
|
1937 } else { |
|
1938 tp->set_speed = rtl8169_set_speed_xmii; |
|
1939 tp->get_settings = rtl8169_gset_xmii; |
|
1940 tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
|
1941 tp->phy_reset_pending = rtl8169_xmii_reset_pending; |
|
1942 tp->link_ok = rtl8169_xmii_link_ok; |
|
1943 |
|
1944 dev->do_ioctl = rtl8169_ioctl; |
|
1945 } |
|
1946 |
|
1947 /* Get MAC address. FIXME: read EEPROM */ |
|
1948 for (i = 0; i < MAC_ADDR_LEN; i++) |
|
1949 dev->dev_addr[i] = RTL_R8(MAC0 + i); |
|
1950 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
1951 |
|
1952 dev->open = rtl8169_open; |
|
1953 dev->hard_start_xmit = rtl8169_start_xmit; |
|
1954 dev->get_stats = rtl8169_get_stats; |
|
1955 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
|
1956 dev->stop = rtl8169_close; |
|
1957 dev->tx_timeout = rtl8169_tx_timeout; |
|
1958 dev->set_multicast_list = rtl_set_rx_mode; |
|
1959 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
|
1960 dev->irq = pdev->irq; |
|
1961 dev->base_addr = (unsigned long) ioaddr; |
|
1962 dev->change_mtu = rtl8169_change_mtu; |
|
1963 dev->set_mac_address = rtl_set_mac_address; |
|
1964 |
|
1965 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
|
1966 |
|
1967 #ifdef CONFIG_R8169_VLAN |
|
1968 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
1969 dev->vlan_rx_register = rtl8169_vlan_rx_register; |
|
1970 #endif |
|
1971 |
|
1972 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
1973 dev->poll_controller = rtl8169_netpoll; |
|
1974 #endif |
|
1975 |
|
1976 tp->intr_mask = 0xffff; |
|
1977 tp->mmio_addr = ioaddr; |
|
1978 tp->align = cfg->align; |
|
1979 tp->hw_start = cfg->hw_start; |
|
1980 tp->intr_event = cfg->intr_event; |
|
1981 tp->napi_event = cfg->napi_event; |
|
1982 |
|
1983 init_timer(&tp->timer); |
|
1984 tp->timer.data = (unsigned long) dev; |
|
1985 tp->timer.function = rtl8169_phy_timer; |
|
1986 |
|
1987 spin_lock_init(&tp->lock); |
|
1988 |
|
1989 // offer device to EtherCAT master module |
|
1990 tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE); |
|
1991 |
|
1992 if (!tp->ecdev) { |
|
1993 rc = register_netdev(dev); |
|
1994 if (rc < 0) |
|
1995 goto err_out_msi_5; |
|
1996 } |
|
1997 |
|
1998 pci_set_drvdata(pdev, dev); |
|
1999 |
|
2000 if (netif_msg_probe(tp)) { |
|
2001 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff; |
|
2002 |
|
2003 printk(KERN_INFO "%s: %s at 0x%lx, " |
|
2004 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " |
|
2005 "XID %08x IRQ %d\n", |
|
2006 dev->name, |
|
2007 rtl_chip_info[tp->chipset].name, |
|
2008 dev->base_addr, |
|
2009 dev->dev_addr[0], dev->dev_addr[1], |
|
2010 dev->dev_addr[2], dev->dev_addr[3], |
|
2011 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq); |
|
2012 } |
|
2013 |
|
2014 rtl8169_init_phy(dev, tp); |
|
2015 |
|
2016 if (tp->ecdev && ecdev_open(tp->ecdev)) { |
|
2017 ecdev_withdraw(tp->ecdev); |
|
2018 goto err_out_msi_5; |
|
2019 } |
|
2020 |
|
2021 out: |
|
2022 return rc; |
|
2023 |
|
2024 err_out_msi_5: |
|
2025 rtl_disable_msi(pdev, tp); |
|
2026 iounmap(ioaddr); |
|
2027 err_out_free_res_4: |
|
2028 pci_release_regions(pdev); |
|
2029 err_out_mwi_3: |
|
2030 pci_clear_mwi(pdev); |
|
2031 err_out_disable_2: |
|
2032 pci_disable_device(pdev); |
|
2033 err_out_free_dev_1: |
|
2034 free_netdev(dev); |
|
2035 goto out; |
|
2036 } |
|
2037 |
|
2038 static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
|
2039 { |
|
2040 struct net_device *dev = pci_get_drvdata(pdev); |
|
2041 struct rtl8169_private *tp = netdev_priv(dev); |
|
2042 |
|
2043 flush_scheduled_work(); |
|
2044 |
|
2045 if (tp->ecdev) { |
|
2046 ecdev_close(tp->ecdev); |
|
2047 ecdev_withdraw(tp->ecdev); |
|
2048 } else { |
|
2049 unregister_netdev(dev); |
|
2050 } |
|
2051 rtl_disable_msi(pdev, tp); |
|
2052 rtl8169_release_board(pdev, dev, tp->mmio_addr); |
|
2053 pci_set_drvdata(pdev, NULL); |
|
2054 } |
|
2055 |
|
2056 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, |
|
2057 struct net_device *dev) |
|
2058 { |
|
2059 unsigned int mtu = dev->mtu; |
|
2060 |
|
2061 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE; |
|
2062 } |
|
2063 |
|
2064 static int rtl8169_open(struct net_device *dev) |
|
2065 { |
|
2066 struct rtl8169_private *tp = netdev_priv(dev); |
|
2067 struct pci_dev *pdev = tp->pci_dev; |
|
2068 int retval = -ENOMEM; |
|
2069 |
|
2070 |
|
2071 rtl8169_set_rxbufsize(tp, dev); |
|
2072 |
|
2073 /* |
|
2074 * Rx and Tx desscriptors needs 256 bytes alignment. |
|
2075 * pci_alloc_consistent provides more. |
|
2076 */ |
|
2077 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, |
|
2078 &tp->TxPhyAddr); |
|
2079 if (!tp->TxDescArray) |
|
2080 goto out; |
|
2081 |
|
2082 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, |
|
2083 &tp->RxPhyAddr); |
|
2084 if (!tp->RxDescArray) |
|
2085 goto err_free_tx_0; |
|
2086 |
|
2087 retval = rtl8169_init_ring(dev); |
|
2088 if (retval < 0) |
|
2089 goto err_free_rx_1; |
|
2090 |
|
2091 INIT_DELAYED_WORK(&tp->task, NULL); |
|
2092 |
|
2093 smp_mb(); |
|
2094 |
|
2095 if (!tp->ecdev) { |
|
2096 retval = request_irq(dev->irq, rtl8169_interrupt, |
|
2097 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
|
2098 dev->name, dev); |
|
2099 if (retval < 0) |
|
2100 goto err_release_ring_2; |
|
2101 |
|
2102 napi_enable(&tp->napi); |
|
2103 } |
|
2104 |
|
2105 rtl_hw_start(dev); |
|
2106 |
|
2107 rtl8169_request_timer(dev); |
|
2108 |
|
2109 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
2110 out: |
|
2111 return retval; |
|
2112 |
|
2113 err_release_ring_2: |
|
2114 rtl8169_rx_clear(tp); |
|
2115 err_free_rx_1: |
|
2116 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
2117 tp->RxPhyAddr); |
|
2118 err_free_tx_0: |
|
2119 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
2120 tp->TxPhyAddr); |
|
2121 goto out; |
|
2122 } |
|
2123 |
|
2124 static void rtl8169_hw_reset(void __iomem *ioaddr) |
|
2125 { |
|
2126 /* Disable interrupts */ |
|
2127 rtl8169_irq_mask_and_ack(ioaddr); |
|
2128 |
|
2129 /* Reset the chipset */ |
|
2130 RTL_W8(ChipCmd, CmdReset); |
|
2131 |
|
2132 /* PCI commit */ |
|
2133 RTL_R8(ChipCmd); |
|
2134 } |
|
2135 |
|
2136 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
|
2137 { |
|
2138 void __iomem *ioaddr = tp->mmio_addr; |
|
2139 u32 cfg = rtl8169_rx_config; |
|
2140 |
|
2141 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
2142 RTL_W32(RxConfig, cfg); |
|
2143 |
|
2144 /* Set DMA burst size and Interframe Gap Time */ |
|
2145 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
2146 (InterFrameGap << TxInterFrameGapShift)); |
|
2147 } |
|
2148 |
|
2149 static void rtl_hw_start(struct net_device *dev) |
|
2150 { |
|
2151 struct rtl8169_private *tp = netdev_priv(dev); |
|
2152 void __iomem *ioaddr = tp->mmio_addr; |
|
2153 unsigned int i; |
|
2154 |
|
2155 /* Soft reset the chip. */ |
|
2156 RTL_W8(ChipCmd, CmdReset); |
|
2157 |
|
2158 /* Check that the chip has finished the reset. */ |
|
2159 for (i = 0; i < 100; i++) { |
|
2160 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
2161 break; |
|
2162 msleep_interruptible(1); |
|
2163 } |
|
2164 |
|
2165 tp->hw_start(dev); |
|
2166 |
|
2167 if (!tp->ecdev) |
|
2168 netif_start_queue(dev); |
|
2169 } |
|
2170 |
|
2171 |
|
2172 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
|
2173 void __iomem *ioaddr) |
|
2174 { |
|
2175 /* |
|
2176 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh |
|
2177 * register to be written before TxDescAddrLow to work. |
|
2178 * Switching from MMIO to I/O access fixes the issue as well. |
|
2179 */ |
|
2180 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
|
2181 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK); |
|
2182 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
|
2183 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK); |
|
2184 } |
|
2185 |
|
2186 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) |
|
2187 { |
|
2188 u16 cmd; |
|
2189 |
|
2190 cmd = RTL_R16(CPlusCmd); |
|
2191 RTL_W16(CPlusCmd, cmd); |
|
2192 return cmd; |
|
2193 } |
|
2194 |
|
2195 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
|
2196 { |
|
2197 /* Low hurts. Let's disable the filtering. */ |
|
2198 RTL_W16(RxMaxSize, rx_buf_sz); |
|
2199 } |
|
2200 |
|
2201 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
|
2202 { |
|
2203 struct { |
|
2204 u32 mac_version; |
|
2205 u32 clk; |
|
2206 u32 val; |
|
2207 } cfg2_info [] = { |
|
2208 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd |
|
2209 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, |
|
2210 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe |
|
2211 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } |
|
2212 }, *p = cfg2_info; |
|
2213 unsigned int i; |
|
2214 u32 clk; |
|
2215 |
|
2216 clk = RTL_R8(Config2) & PCI_Clock_66MHz; |
|
2217 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
|
2218 if ((p->mac_version == mac_version) && (p->clk == clk)) { |
|
2219 RTL_W32(0x7c, p->val); |
|
2220 break; |
|
2221 } |
|
2222 } |
|
2223 } |
|
2224 |
|
2225 static void rtl_hw_start_8169(struct net_device *dev) |
|
2226 { |
|
2227 struct rtl8169_private *tp = netdev_priv(dev); |
|
2228 void __iomem *ioaddr = tp->mmio_addr; |
|
2229 struct pci_dev *pdev = tp->pci_dev; |
|
2230 |
|
2231 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
|
2232 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); |
|
2233 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); |
|
2234 } |
|
2235 |
|
2236 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2237 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
2238 (tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
2239 (tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
2240 (tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
2241 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2242 |
|
2243 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2244 |
|
2245 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); |
|
2246 |
|
2247 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
2248 (tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
2249 (tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
2250 (tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
2251 rtl_set_rx_tx_config_registers(tp); |
|
2252 |
|
2253 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
2254 |
|
2255 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
2256 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { |
|
2257 dprintk("Set MAC Reg C+CR Offset 0xE0. " |
|
2258 "Bit-3 and bit-14 MUST be 1\n"); |
|
2259 tp->cp_cmd |= (1 << 14); |
|
2260 } |
|
2261 |
|
2262 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2263 |
|
2264 rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
|
2265 |
|
2266 /* |
|
2267 * Undocumented corner. Supposedly: |
|
2268 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
2269 */ |
|
2270 RTL_W16(IntrMitigate, 0x0000); |
|
2271 |
|
2272 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2273 |
|
2274 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
|
2275 (tp->mac_version != RTL_GIGA_MAC_VER_02) && |
|
2276 (tp->mac_version != RTL_GIGA_MAC_VER_03) && |
|
2277 (tp->mac_version != RTL_GIGA_MAC_VER_04)) { |
|
2278 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2279 rtl_set_rx_tx_config_registers(tp); |
|
2280 } |
|
2281 |
|
2282 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2283 |
|
2284 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
|
2285 RTL_R8(IntrMask); |
|
2286 |
|
2287 RTL_W32(RxMissed, 0); |
|
2288 |
|
2289 rtl_set_rx_mode(dev); |
|
2290 |
|
2291 /* no early-rx interrupts */ |
|
2292 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
2293 |
|
2294 /* Enable all known interrupts by setting the interrupt mask. */ |
|
2295 if (!tp->ecdev) |
|
2296 RTL_W16(IntrMask, tp->intr_event); |
|
2297 } |
|
2298 |
|
2299 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
|
2300 { |
|
2301 struct net_device *dev = pci_get_drvdata(pdev); |
|
2302 struct rtl8169_private *tp = netdev_priv(dev); |
|
2303 int cap = tp->pcie_cap; |
|
2304 |
|
2305 if (cap) { |
|
2306 u16 ctl; |
|
2307 |
|
2308 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
|
2309 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; |
|
2310 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); |
|
2311 } |
|
2312 } |
|
2313 |
|
2314 static void rtl_csi_access_enable(void __iomem *ioaddr) |
|
2315 { |
|
2316 u32 csi; |
|
2317 |
|
2318 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; |
|
2319 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); |
|
2320 } |
|
2321 |
|
2322 struct ephy_info { |
|
2323 unsigned int offset; |
|
2324 u16 mask; |
|
2325 u16 bits; |
|
2326 }; |
|
2327 |
|
2328 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len) |
|
2329 { |
|
2330 u16 w; |
|
2331 |
|
2332 while (len-- > 0) { |
|
2333 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; |
|
2334 rtl_ephy_write(ioaddr, e->offset, w); |
|
2335 e++; |
|
2336 } |
|
2337 } |
|
2338 |
|
2339 static void rtl_hw_start_8168(struct net_device *dev) |
|
2340 { |
|
2341 struct rtl8169_private *tp = netdev_priv(dev); |
|
2342 void __iomem *ioaddr = tp->mmio_addr; |
|
2343 struct pci_dev *pdev = tp->pci_dev; |
|
2344 |
|
2345 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2346 |
|
2347 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2348 |
|
2349 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); |
|
2350 |
|
2351 rtl_set_rx_tx_config_registers(tp); |
|
2352 |
|
2353 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
|
2354 |
|
2355 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2356 |
|
2357 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
2358 |
|
2359 RTL_W16(IntrMitigate, 0x5151); |
|
2360 |
|
2361 /* Work around for RxFIFO overflow. */ |
|
2362 if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
|
2363 tp->intr_event |= RxFIFOOver | PCSTimeout; |
|
2364 tp->intr_event &= ~RxOverflow; |
|
2365 } |
|
2366 |
|
2367 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2368 |
|
2369 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2370 |
|
2371 RTL_R8(IntrMask); |
|
2372 |
|
2373 rtl_set_rx_mode(dev); |
|
2374 |
|
2375 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2376 |
|
2377 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
2378 |
|
2379 if (!tp->ecdev) |
|
2380 RTL_W16(IntrMask, tp->intr_event); |
|
2381 } |
|
2382 |
|
2383 #define R810X_CPCMD_QUIRK_MASK (\ |
|
2384 EnableBist | \ |
|
2385 Mac_dbgo_oe | \ |
|
2386 Force_half_dup | \ |
|
2387 Force_half_dup | \ |
|
2388 Force_txflow_en | \ |
|
2389 Cxpl_dbg_sel | \ |
|
2390 ASF | \ |
|
2391 PktCntrDisable | \ |
|
2392 PCIDAC | \ |
|
2393 PCIMulRW) |
|
2394 |
|
2395 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2396 { |
|
2397 static struct ephy_info e_info_8102e_1[] = { |
|
2398 { 0x01, 0, 0x6e65 }, |
|
2399 { 0x02, 0, 0x091f }, |
|
2400 { 0x03, 0, 0xc2f9 }, |
|
2401 { 0x06, 0, 0xafb5 }, |
|
2402 { 0x07, 0, 0x0e00 }, |
|
2403 { 0x19, 0, 0xec80 }, |
|
2404 { 0x01, 0, 0x2e65 }, |
|
2405 { 0x01, 0, 0x6e65 } |
|
2406 }; |
|
2407 u8 cfg1; |
|
2408 |
|
2409 rtl_csi_access_enable(ioaddr); |
|
2410 |
|
2411 RTL_W8(DBG_REG, FIX_NAK_1); |
|
2412 |
|
2413 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
2414 |
|
2415 RTL_W8(Config1, |
|
2416 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); |
|
2417 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
2418 |
|
2419 cfg1 = RTL_R8(Config1); |
|
2420 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) |
|
2421 RTL_W8(Config1, cfg1 & ~LEDS0); |
|
2422 |
|
2423 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); |
|
2424 |
|
2425 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
|
2426 } |
|
2427 |
|
2428 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2429 { |
|
2430 rtl_csi_access_enable(ioaddr); |
|
2431 |
|
2432 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
2433 |
|
2434 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); |
|
2435 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
2436 |
|
2437 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); |
|
2438 } |
|
2439 |
|
2440 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2441 { |
|
2442 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
2443 |
|
2444 rtl_ephy_write(ioaddr, 0x03, 0xc2f9); |
|
2445 } |
|
2446 |
|
2447 static void rtl_hw_start_8101(struct net_device *dev) |
|
2448 { |
|
2449 struct rtl8169_private *tp = netdev_priv(dev); |
|
2450 void __iomem *ioaddr = tp->mmio_addr; |
|
2451 struct pci_dev *pdev = tp->pci_dev; |
|
2452 |
|
2453 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
2454 (tp->mac_version == RTL_GIGA_MAC_VER_16)) { |
|
2455 int cap = tp->pcie_cap; |
|
2456 |
|
2457 if (cap) { |
|
2458 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, |
|
2459 PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
2460 } |
|
2461 } |
|
2462 |
|
2463 switch (tp->mac_version) { |
|
2464 case RTL_GIGA_MAC_VER_07: |
|
2465 rtl_hw_start_8102e_1(ioaddr, pdev); |
|
2466 break; |
|
2467 |
|
2468 case RTL_GIGA_MAC_VER_08: |
|
2469 rtl_hw_start_8102e_3(ioaddr, pdev); |
|
2470 break; |
|
2471 |
|
2472 case RTL_GIGA_MAC_VER_09: |
|
2473 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
2474 break; |
|
2475 } |
|
2476 |
|
2477 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2478 |
|
2479 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2480 |
|
2481 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); |
|
2482 |
|
2483 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
2484 |
|
2485 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2486 |
|
2487 RTL_W16(IntrMitigate, 0x0000); |
|
2488 |
|
2489 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2490 |
|
2491 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2492 rtl_set_rx_tx_config_registers(tp); |
|
2493 |
|
2494 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2495 |
|
2496 RTL_R8(IntrMask); |
|
2497 |
|
2498 rtl_set_rx_mode(dev); |
|
2499 |
|
2500 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2501 |
|
2502 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
|
2503 |
|
2504 if (!tp->ecdev) |
|
2505 RTL_W16(IntrMask, tp->intr_event); |
|
2506 } |
|
2507 |
|
2508 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
|
2509 { |
|
2510 struct rtl8169_private *tp = netdev_priv(dev); |
|
2511 int ret = 0; |
|
2512 |
|
2513 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) |
|
2514 return -EINVAL; |
|
2515 |
|
2516 dev->mtu = new_mtu; |
|
2517 |
|
2518 if (!netif_running(dev)) |
|
2519 goto out; |
|
2520 |
|
2521 rtl8169_down(dev); |
|
2522 |
|
2523 rtl8169_set_rxbufsize(tp, dev); |
|
2524 |
|
2525 ret = rtl8169_init_ring(dev); |
|
2526 if (ret < 0) |
|
2527 goto out; |
|
2528 |
|
2529 napi_enable(&tp->napi); |
|
2530 |
|
2531 rtl_hw_start(dev); |
|
2532 |
|
2533 rtl8169_request_timer(dev); |
|
2534 |
|
2535 out: |
|
2536 return ret; |
|
2537 } |
|
2538 |
|
2539 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) |
|
2540 { |
|
2541 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
|
2542 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
|
2543 } |
|
2544 |
|
2545 static void rtl8169_free_rx_skb(struct rtl8169_private *tp, |
|
2546 struct sk_buff **sk_buff, struct RxDesc *desc) |
|
2547 { |
|
2548 struct pci_dev *pdev = tp->pci_dev; |
|
2549 |
|
2550 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, |
|
2551 PCI_DMA_FROMDEVICE); |
|
2552 dev_kfree_skb(*sk_buff); |
|
2553 *sk_buff = NULL; |
|
2554 rtl8169_make_unusable_by_asic(desc); |
|
2555 } |
|
2556 |
|
2557 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) |
|
2558 { |
|
2559 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; |
|
2560 |
|
2561 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
|
2562 } |
|
2563 |
|
2564 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, |
|
2565 u32 rx_buf_sz) |
|
2566 { |
|
2567 desc->addr = cpu_to_le64(mapping); |
|
2568 wmb(); |
|
2569 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
2570 } |
|
2571 |
|
2572 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, |
|
2573 struct net_device *dev, |
|
2574 struct RxDesc *desc, int rx_buf_sz, |
|
2575 unsigned int align) |
|
2576 { |
|
2577 struct sk_buff *skb; |
|
2578 dma_addr_t mapping; |
|
2579 unsigned int pad; |
|
2580 |
|
2581 pad = align ? align : NET_IP_ALIGN; |
|
2582 |
|
2583 skb = netdev_alloc_skb(dev, rx_buf_sz + pad); |
|
2584 if (!skb) |
|
2585 goto err_out; |
|
2586 |
|
2587 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); |
|
2588 |
|
2589 mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
|
2590 PCI_DMA_FROMDEVICE); |
|
2591 |
|
2592 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); |
|
2593 out: |
|
2594 return skb; |
|
2595 |
|
2596 err_out: |
|
2597 rtl8169_make_unusable_by_asic(desc); |
|
2598 goto out; |
|
2599 } |
|
2600 |
|
2601 static void rtl8169_rx_clear(struct rtl8169_private *tp) |
|
2602 { |
|
2603 unsigned int i; |
|
2604 |
|
2605 for (i = 0; i < NUM_RX_DESC; i++) { |
|
2606 if (tp->Rx_skbuff[i]) { |
|
2607 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, |
|
2608 tp->RxDescArray + i); |
|
2609 } |
|
2610 } |
|
2611 } |
|
2612 |
|
2613 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, |
|
2614 u32 start, u32 end) |
|
2615 { |
|
2616 u32 cur; |
|
2617 |
|
2618 for (cur = start; end - cur != 0; cur++) { |
|
2619 struct sk_buff *skb; |
|
2620 unsigned int i = cur % NUM_RX_DESC; |
|
2621 |
|
2622 WARN_ON((s32)(end - cur) < 0); |
|
2623 |
|
2624 if (tp->Rx_skbuff[i]) |
|
2625 continue; |
|
2626 |
|
2627 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, |
|
2628 tp->RxDescArray + i, |
|
2629 tp->rx_buf_sz, tp->align); |
|
2630 if (!skb) |
|
2631 break; |
|
2632 |
|
2633 tp->Rx_skbuff[i] = skb; |
|
2634 } |
|
2635 return cur - start; |
|
2636 } |
|
2637 |
|
2638 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
|
2639 { |
|
2640 desc->opts1 |= cpu_to_le32(RingEnd); |
|
2641 } |
|
2642 |
|
2643 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
|
2644 { |
|
2645 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; |
|
2646 } |
|
2647 |
|
2648 static int rtl8169_init_ring(struct net_device *dev) |
|
2649 { |
|
2650 struct rtl8169_private *tp = netdev_priv(dev); |
|
2651 |
|
2652 rtl8169_init_ring_indexes(tp); |
|
2653 |
|
2654 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); |
|
2655 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); |
|
2656 |
|
2657 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) |
|
2658 goto err_out; |
|
2659 |
|
2660 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
|
2661 |
|
2662 return 0; |
|
2663 |
|
2664 err_out: |
|
2665 rtl8169_rx_clear(tp); |
|
2666 return -ENOMEM; |
|
2667 } |
|
2668 |
|
2669 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, |
|
2670 struct TxDesc *desc) |
|
2671 { |
|
2672 unsigned int len = tx_skb->len; |
|
2673 |
|
2674 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); |
|
2675 desc->opts1 = 0x00; |
|
2676 desc->opts2 = 0x00; |
|
2677 desc->addr = 0x00; |
|
2678 tx_skb->len = 0; |
|
2679 } |
|
2680 |
|
2681 static void rtl8169_tx_clear(struct rtl8169_private *tp) |
|
2682 { |
|
2683 unsigned int i; |
|
2684 |
|
2685 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { |
|
2686 unsigned int entry = i % NUM_TX_DESC; |
|
2687 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
2688 unsigned int len = tx_skb->len; |
|
2689 |
|
2690 if (len) { |
|
2691 struct sk_buff *skb = tx_skb->skb; |
|
2692 |
|
2693 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, |
|
2694 tp->TxDescArray + entry); |
|
2695 if (skb) { |
|
2696 if (!tp->ecdev) |
|
2697 dev_kfree_skb(skb); |
|
2698 tx_skb->skb = NULL; |
|
2699 } |
|
2700 tp->dev->stats.tx_dropped++; |
|
2701 } |
|
2702 } |
|
2703 tp->cur_tx = tp->dirty_tx = 0; |
|
2704 } |
|
2705 |
|
2706 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
|
2707 { |
|
2708 struct rtl8169_private *tp = netdev_priv(dev); |
|
2709 |
|
2710 PREPARE_DELAYED_WORK(&tp->task, task); |
|
2711 schedule_delayed_work(&tp->task, 4); |
|
2712 } |
|
2713 |
|
2714 static void rtl8169_wait_for_quiescence(struct net_device *dev) |
|
2715 { |
|
2716 struct rtl8169_private *tp = netdev_priv(dev); |
|
2717 void __iomem *ioaddr = tp->mmio_addr; |
|
2718 |
|
2719 synchronize_irq(dev->irq); |
|
2720 |
|
2721 /* Wait for any pending NAPI task to complete */ |
|
2722 napi_disable(&tp->napi); |
|
2723 |
|
2724 rtl8169_irq_mask_and_ack(ioaddr); |
|
2725 |
|
2726 tp->intr_mask = 0xffff; |
|
2727 RTL_W16(IntrMask, tp->intr_event); |
|
2728 napi_enable(&tp->napi); |
|
2729 } |
|
2730 |
|
2731 static void rtl8169_reinit_task(struct work_struct *work) |
|
2732 { |
|
2733 struct rtl8169_private *tp = |
|
2734 container_of(work, struct rtl8169_private, task.work); |
|
2735 struct net_device *dev = tp->dev; |
|
2736 int ret; |
|
2737 |
|
2738 rtnl_lock(); |
|
2739 |
|
2740 if (!netif_running(dev)) |
|
2741 goto out_unlock; |
|
2742 |
|
2743 rtl8169_wait_for_quiescence(dev); |
|
2744 rtl8169_close(dev); |
|
2745 |
|
2746 ret = rtl8169_open(dev); |
|
2747 if (unlikely(ret < 0)) { |
|
2748 if (net_ratelimit() && netif_msg_drv(tp)) { |
|
2749 printk(KERN_ERR PFX "%s: reinit failure (status = %d)." |
|
2750 " Rescheduling.\n", dev->name, ret); |
|
2751 } |
|
2752 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
2753 } |
|
2754 |
|
2755 out_unlock: |
|
2756 rtnl_unlock(); |
|
2757 } |
|
2758 |
|
2759 static void rtl8169_reset_task(struct work_struct *work) |
|
2760 { |
|
2761 struct rtl8169_private *tp = |
|
2762 container_of(work, struct rtl8169_private, task.work); |
|
2763 struct net_device *dev = tp->dev; |
|
2764 |
|
2765 rtnl_lock(); |
|
2766 |
|
2767 if (!netif_running(dev)) |
|
2768 goto out_unlock; |
|
2769 |
|
2770 rtl8169_wait_for_quiescence(dev); |
|
2771 |
|
2772 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
|
2773 rtl8169_tx_clear(tp); |
|
2774 |
|
2775 if (tp->dirty_rx == tp->cur_rx) { |
|
2776 rtl8169_init_ring_indexes(tp); |
|
2777 rtl_hw_start(dev); |
|
2778 netif_wake_queue(dev); |
|
2779 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
2780 } else { |
|
2781 if (net_ratelimit() && netif_msg_intr(tp)) { |
|
2782 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n", |
|
2783 dev->name); |
|
2784 } |
|
2785 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
2786 } |
|
2787 |
|
2788 out_unlock: |
|
2789 rtnl_unlock(); |
|
2790 } |
|
2791 |
|
2792 static void rtl8169_tx_timeout(struct net_device *dev) |
|
2793 { |
|
2794 struct rtl8169_private *tp = netdev_priv(dev); |
|
2795 |
|
2796 if (tp->ecdev) |
|
2797 return; |
|
2798 |
|
2799 rtl8169_hw_reset(tp->mmio_addr); |
|
2800 |
|
2801 /* Let's wait a bit while any (async) irq lands on */ |
|
2802 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
2803 } |
|
2804 |
|
2805 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
|
2806 u32 opts1) |
|
2807 { |
|
2808 struct skb_shared_info *info = skb_shinfo(skb); |
|
2809 unsigned int cur_frag, entry; |
|
2810 struct TxDesc * uninitialized_var(txd); |
|
2811 |
|
2812 entry = tp->cur_tx; |
|
2813 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { |
|
2814 skb_frag_t *frag = info->frags + cur_frag; |
|
2815 dma_addr_t mapping; |
|
2816 u32 status, len; |
|
2817 void *addr; |
|
2818 |
|
2819 entry = (entry + 1) % NUM_TX_DESC; |
|
2820 |
|
2821 txd = tp->TxDescArray + entry; |
|
2822 len = frag->size; |
|
2823 addr = ((void *) page_address(frag->page)) + frag->page_offset; |
|
2824 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); |
|
2825 |
|
2826 /* anti gcc 2.95.3 bugware (sic) */ |
|
2827 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
2828 |
|
2829 txd->opts1 = cpu_to_le32(status); |
|
2830 txd->addr = cpu_to_le64(mapping); |
|
2831 |
|
2832 tp->tx_skb[entry].len = len; |
|
2833 } |
|
2834 |
|
2835 if (cur_frag) { |
|
2836 tp->tx_skb[entry].skb = skb; |
|
2837 txd->opts1 |= cpu_to_le32(LastFrag); |
|
2838 } |
|
2839 |
|
2840 return cur_frag; |
|
2841 } |
|
2842 |
|
2843 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) |
|
2844 { |
|
2845 if (dev->features & NETIF_F_TSO) { |
|
2846 u32 mss = skb_shinfo(skb)->gso_size; |
|
2847 |
|
2848 if (mss) |
|
2849 return LargeSend | ((mss & MSSMask) << MSSShift); |
|
2850 } |
|
2851 if (skb->ip_summed == CHECKSUM_PARTIAL) { |
|
2852 const struct iphdr *ip = ip_hdr(skb); |
|
2853 |
|
2854 if (ip->protocol == IPPROTO_TCP) |
|
2855 return IPCS | TCPCS; |
|
2856 else if (ip->protocol == IPPROTO_UDP) |
|
2857 return IPCS | UDPCS; |
|
2858 WARN_ON(1); /* we need a WARN() */ |
|
2859 } |
|
2860 return 0; |
|
2861 } |
|
2862 |
|
2863 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) |
|
2864 { |
|
2865 struct rtl8169_private *tp = netdev_priv(dev); |
|
2866 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; |
|
2867 struct TxDesc *txd = tp->TxDescArray + entry; |
|
2868 void __iomem *ioaddr = tp->mmio_addr; |
|
2869 dma_addr_t mapping; |
|
2870 u32 status, len; |
|
2871 u32 opts1; |
|
2872 int ret = NETDEV_TX_OK; |
|
2873 |
|
2874 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
|
2875 if (netif_msg_drv(tp)) { |
|
2876 printk(KERN_ERR |
|
2877 "%s: BUG! Tx Ring full when queue awake!\n", |
|
2878 dev->name); |
|
2879 } |
|
2880 goto err_stop; |
|
2881 } |
|
2882 |
|
2883 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) |
|
2884 goto err_stop; |
|
2885 |
|
2886 opts1 = DescOwn | rtl8169_tso_csum(skb, dev); |
|
2887 |
|
2888 frags = rtl8169_xmit_frags(tp, skb, opts1); |
|
2889 if (frags) { |
|
2890 len = skb_headlen(skb); |
|
2891 opts1 |= FirstFrag; |
|
2892 } else { |
|
2893 len = skb->len; |
|
2894 opts1 |= FirstFrag | LastFrag; |
|
2895 tp->tx_skb[entry].skb = skb; |
|
2896 } |
|
2897 |
|
2898 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); |
|
2899 |
|
2900 tp->tx_skb[entry].len = len; |
|
2901 txd->addr = cpu_to_le64(mapping); |
|
2902 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
|
2903 |
|
2904 wmb(); |
|
2905 |
|
2906 /* anti gcc 2.95.3 bugware (sic) */ |
|
2907 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
2908 txd->opts1 = cpu_to_le32(status); |
|
2909 |
|
2910 dev->trans_start = jiffies; |
|
2911 |
|
2912 tp->cur_tx += frags + 1; |
|
2913 |
|
2914 smp_wmb(); |
|
2915 |
|
2916 RTL_W8(TxPoll, NPQ); /* set polling bit */ |
|
2917 |
|
2918 if (!tp->ecdev) { |
|
2919 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { |
|
2920 netif_stop_queue(dev); |
|
2921 smp_rmb(); |
|
2922 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) |
|
2923 netif_wake_queue(dev); |
|
2924 } |
|
2925 } |
|
2926 |
|
2927 out: |
|
2928 return ret; |
|
2929 |
|
2930 err_stop: |
|
2931 if (!tp->ecdev) |
|
2932 netif_stop_queue(dev); |
|
2933 ret = NETDEV_TX_BUSY; |
|
2934 dev->stats.tx_dropped++; |
|
2935 goto out; |
|
2936 } |
|
2937 |
|
2938 static void rtl8169_pcierr_interrupt(struct net_device *dev) |
|
2939 { |
|
2940 struct rtl8169_private *tp = netdev_priv(dev); |
|
2941 struct pci_dev *pdev = tp->pci_dev; |
|
2942 void __iomem *ioaddr = tp->mmio_addr; |
|
2943 u16 pci_status, pci_cmd; |
|
2944 |
|
2945 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
|
2946 pci_read_config_word(pdev, PCI_STATUS, &pci_status); |
|
2947 |
|
2948 if (netif_msg_intr(tp)) { |
|
2949 printk(KERN_ERR |
|
2950 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", |
|
2951 dev->name, pci_cmd, pci_status); |
|
2952 } |
|
2953 |
|
2954 /* |
|
2955 * The recovery sequence below admits a very elaborated explanation: |
|
2956 * - it seems to work; |
|
2957 * - I did not see what else could be done; |
|
2958 * - it makes iop3xx happy. |
|
2959 * |
|
2960 * Feel free to adjust to your needs. |
|
2961 */ |
|
2962 if (pdev->broken_parity_status) |
|
2963 pci_cmd &= ~PCI_COMMAND_PARITY; |
|
2964 else |
|
2965 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
|
2966 |
|
2967 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
|
2968 |
|
2969 pci_write_config_word(pdev, PCI_STATUS, |
|
2970 pci_status & (PCI_STATUS_DETECTED_PARITY | |
|
2971 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | |
|
2972 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); |
|
2973 |
|
2974 /* The infamous DAC f*ckup only happens at boot time */ |
|
2975 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { |
|
2976 if (netif_msg_intr(tp)) |
|
2977 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); |
|
2978 tp->cp_cmd &= ~PCIDAC; |
|
2979 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2980 dev->features &= ~NETIF_F_HIGHDMA; |
|
2981 } |
|
2982 |
|
2983 rtl8169_hw_reset(ioaddr); |
|
2984 |
|
2985 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
2986 } |
|
2987 |
|
2988 static void rtl8169_tx_interrupt(struct net_device *dev, |
|
2989 struct rtl8169_private *tp, |
|
2990 void __iomem *ioaddr) |
|
2991 { |
|
2992 unsigned int dirty_tx, tx_left; |
|
2993 |
|
2994 dirty_tx = tp->dirty_tx; |
|
2995 smp_rmb(); |
|
2996 tx_left = tp->cur_tx - dirty_tx; |
|
2997 |
|
2998 while (tx_left > 0) { |
|
2999 unsigned int entry = dirty_tx % NUM_TX_DESC; |
|
3000 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
3001 u32 len = tx_skb->len; |
|
3002 u32 status; |
|
3003 |
|
3004 rmb(); |
|
3005 status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
|
3006 if (status & DescOwn) |
|
3007 break; |
|
3008 |
|
3009 dev->stats.tx_bytes += len; |
|
3010 dev->stats.tx_packets++; |
|
3011 |
|
3012 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); |
|
3013 |
|
3014 if (status & LastFrag) { |
|
3015 if (!tp->ecdev) |
|
3016 dev_kfree_skb_irq(tx_skb->skb); |
|
3017 tx_skb->skb = NULL; |
|
3018 } |
|
3019 dirty_tx++; |
|
3020 tx_left--; |
|
3021 } |
|
3022 |
|
3023 if (tp->dirty_tx != dirty_tx) { |
|
3024 tp->dirty_tx = dirty_tx; |
|
3025 smp_wmb(); |
|
3026 if (!tp->ecdev && netif_queue_stopped(dev) && |
|
3027 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { |
|
3028 netif_wake_queue(dev); |
|
3029 } |
|
3030 /* |
|
3031 * 8168 hack: TxPoll requests are lost when the Tx packets are |
|
3032 * too close. Let's kick an extra TxPoll request when a burst |
|
3033 * of start_xmit activity is detected (if it is not detected, |
|
3034 * it is slow enough). -- FR |
|
3035 */ |
|
3036 smp_rmb(); |
|
3037 if (tp->cur_tx != dirty_tx) |
|
3038 RTL_W8(TxPoll, NPQ); |
|
3039 } |
|
3040 } |
|
3041 |
|
3042 static inline int rtl8169_fragmented_frame(u32 status) |
|
3043 { |
|
3044 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); |
|
3045 } |
|
3046 |
|
3047 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) |
|
3048 { |
|
3049 u32 opts1 = le32_to_cpu(desc->opts1); |
|
3050 u32 status = opts1 & RxProtoMask; |
|
3051 |
|
3052 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || |
|
3053 ((status == RxProtoUDP) && !(opts1 & UDPFail)) || |
|
3054 ((status == RxProtoIP) && !(opts1 & IPFail))) |
|
3055 skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
3056 else |
|
3057 skb->ip_summed = CHECKSUM_NONE; |
|
3058 } |
|
3059 |
|
3060 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, |
|
3061 struct rtl8169_private *tp, int pkt_size, |
|
3062 dma_addr_t addr) |
|
3063 { |
|
3064 struct sk_buff *skb; |
|
3065 bool done = false; |
|
3066 |
|
3067 if (pkt_size >= rx_copybreak) |
|
3068 goto out; |
|
3069 |
|
3070 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN); |
|
3071 if (!skb) |
|
3072 goto out; |
|
3073 |
|
3074 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size, |
|
3075 PCI_DMA_FROMDEVICE); |
|
3076 skb_reserve(skb, NET_IP_ALIGN); |
|
3077 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size); |
|
3078 *sk_buff = skb; |
|
3079 done = true; |
|
3080 out: |
|
3081 return done; |
|
3082 } |
|
3083 |
|
3084 static int rtl8169_rx_interrupt(struct net_device *dev, |
|
3085 struct rtl8169_private *tp, |
|
3086 void __iomem *ioaddr, u32 budget) |
|
3087 { |
|
3088 unsigned int cur_rx, rx_left; |
|
3089 unsigned int delta, count; |
|
3090 |
|
3091 cur_rx = tp->cur_rx; |
|
3092 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; |
|
3093 rx_left = min(rx_left, budget); |
|
3094 |
|
3095 for (; rx_left > 0; rx_left--, cur_rx++) { |
|
3096 unsigned int entry = cur_rx % NUM_RX_DESC; |
|
3097 struct RxDesc *desc = tp->RxDescArray + entry; |
|
3098 u32 status; |
|
3099 |
|
3100 rmb(); |
|
3101 status = le32_to_cpu(desc->opts1); |
|
3102 |
|
3103 if (status & DescOwn) |
|
3104 break; |
|
3105 if (unlikely(status & RxRES)) { |
|
3106 if (netif_msg_rx_err(tp)) { |
|
3107 printk(KERN_INFO |
|
3108 "%s: Rx ERROR. status = %08x\n", |
|
3109 dev->name, status); |
|
3110 } |
|
3111 dev->stats.rx_errors++; |
|
3112 if (status & (RxRWT | RxRUNT)) |
|
3113 dev->stats.rx_length_errors++; |
|
3114 if (status & RxCRC) |
|
3115 dev->stats.rx_crc_errors++; |
|
3116 if (status & RxFOVF) { |
|
3117 if (!tp->ecdev) |
|
3118 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
3119 dev->stats.rx_fifo_errors++; |
|
3120 } |
|
3121 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
3122 } else { |
|
3123 struct sk_buff *skb = tp->Rx_skbuff[entry]; |
|
3124 dma_addr_t addr = le64_to_cpu(desc->addr); |
|
3125 int pkt_size = (status & 0x00001FFF) - 4; |
|
3126 struct pci_dev *pdev = tp->pci_dev; |
|
3127 |
|
3128 /* |
|
3129 * The driver does not support incoming fragmented |
|
3130 * frames. They are seen as a symptom of over-mtu |
|
3131 * sized frames. |
|
3132 */ |
|
3133 if (unlikely(rtl8169_fragmented_frame(status))) { |
|
3134 dev->stats.rx_dropped++; |
|
3135 dev->stats.rx_length_errors++; |
|
3136 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
3137 continue; |
|
3138 } |
|
3139 |
|
3140 rtl8169_rx_csum(skb, desc); |
|
3141 |
|
3142 if (tp->ecdev) { |
|
3143 pci_dma_sync_single_for_cpu(pdev, addr, pkt_size, |
|
3144 PCI_DMA_FROMDEVICE); |
|
3145 |
|
3146 ecdev_receive(tp->ecdev, skb->data, pkt_size); |
|
3147 |
|
3148 pci_dma_sync_single_for_device(pdev, addr, |
|
3149 pkt_size, PCI_DMA_FROMDEVICE); |
|
3150 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
3151 |
|
3152 // No need to detect link status as |
|
3153 // long as frames are received: Reset watchdog. |
|
3154 tp->ec_watchdog_jiffies = jiffies; |
|
3155 } else { |
|
3156 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) { |
|
3157 pci_dma_sync_single_for_device(pdev, addr, |
|
3158 pkt_size, PCI_DMA_FROMDEVICE); |
|
3159 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
3160 } else { |
|
3161 pci_unmap_single(pdev, addr, tp->rx_buf_sz, |
|
3162 PCI_DMA_FROMDEVICE); |
|
3163 tp->Rx_skbuff[entry] = NULL; |
|
3164 } |
|
3165 |
|
3166 skb_put(skb, pkt_size); |
|
3167 skb->protocol = eth_type_trans(skb, dev); |
|
3168 |
|
3169 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) |
|
3170 netif_receive_skb(skb); |
|
3171 } |
|
3172 |
|
3173 dev->last_rx = jiffies; |
|
3174 dev->stats.rx_bytes += pkt_size; |
|
3175 dev->stats.rx_packets++; |
|
3176 } |
|
3177 |
|
3178 /* Work around for AMD plateform. */ |
|
3179 if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
|
3180 (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
|
3181 desc->opts2 = 0; |
|
3182 cur_rx++; |
|
3183 } |
|
3184 } |
|
3185 |
|
3186 count = cur_rx - tp->cur_rx; |
|
3187 tp->cur_rx = cur_rx; |
|
3188 |
|
3189 if (tp->ecdev) { |
|
3190 /* descriptors are cleaned up immediately. */ |
|
3191 tp->dirty_rx = tp->cur_rx; |
|
3192 } else { |
|
3193 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); |
|
3194 if (!delta && count && netif_msg_intr(tp)) |
|
3195 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); |
|
3196 tp->dirty_rx += delta; |
|
3197 |
|
3198 /* |
|
3199 * FIXME: until there is periodic timer to try and refill the ring, |
|
3200 * a temporary shortage may definitely kill the Rx process. |
|
3201 * - disable the asic to try and avoid an overflow and kick it again |
|
3202 * after refill ? |
|
3203 * - how do others driver handle this condition (Uh oh...). |
|
3204 */ |
|
3205 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) |
|
3206 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); |
|
3207 } |
|
3208 |
|
3209 return count; |
|
3210 } |
|
3211 |
|
3212 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
|
3213 { |
|
3214 struct net_device *dev = dev_instance; |
|
3215 struct rtl8169_private *tp = netdev_priv(dev); |
|
3216 void __iomem *ioaddr = tp->mmio_addr; |
|
3217 int handled = 0; |
|
3218 int status; |
|
3219 |
|
3220 /* loop handling interrupts until we have no new ones or |
|
3221 * we hit a invalid/hotplug case. |
|
3222 */ |
|
3223 status = RTL_R16(IntrStatus); |
|
3224 while (status && status != 0xffff) { |
|
3225 handled = 1; |
|
3226 |
|
3227 /* Handle all of the error cases first. These will reset |
|
3228 * the chip, so just exit the loop. |
|
3229 */ |
|
3230 if (unlikely(!tp->ecdev && !netif_running(dev))) { |
|
3231 rtl8169_asic_down(ioaddr); |
|
3232 break; |
|
3233 } |
|
3234 |
|
3235 /* Work around for rx fifo overflow */ |
|
3236 if (unlikely(status & RxFIFOOver) && |
|
3237 (tp->mac_version == RTL_GIGA_MAC_VER_11)) { |
|
3238 netif_stop_queue(dev); |
|
3239 rtl8169_tx_timeout(dev); |
|
3240 break; |
|
3241 } |
|
3242 |
|
3243 if (unlikely(!tp->ecdev && (status & SYSErr))) { |
|
3244 rtl8169_pcierr_interrupt(dev); |
|
3245 break; |
|
3246 } |
|
3247 |
|
3248 if (status & LinkChg) |
|
3249 rtl8169_check_link_status(dev, tp, ioaddr); |
|
3250 |
|
3251 /* We need to see the lastest version of tp->intr_mask to |
|
3252 * avoid ignoring an MSI interrupt and having to wait for |
|
3253 * another event which may never come. |
|
3254 */ |
|
3255 smp_rmb(); |
|
3256 if (status & tp->intr_mask & tp->napi_event) { |
|
3257 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); |
|
3258 tp->intr_mask = ~tp->napi_event; |
|
3259 |
|
3260 if (likely(napi_schedule_prep(&tp->napi))) |
|
3261 __napi_schedule(&tp->napi); |
|
3262 else if (netif_msg_intr(tp)) { |
|
3263 printk(KERN_INFO "%s: interrupt %04x in poll\n", |
|
3264 dev->name, status); |
|
3265 } |
|
3266 } |
|
3267 |
|
3268 /* We only get a new MSI interrupt when all active irq |
|
3269 * sources on the chip have been acknowledged. So, ack |
|
3270 * everything we've seen and check if new sources have become |
|
3271 * active to avoid blocking all interrupts from the chip. |
|
3272 */ |
|
3273 RTL_W16(IntrStatus, |
|
3274 (status & RxFIFOOver) ? (status | RxOverflow) : status); |
|
3275 status = RTL_R16(IntrStatus); |
|
3276 } |
|
3277 |
|
3278 return IRQ_RETVAL(handled); |
|
3279 } |
|
3280 |
|
3281 static int rtl8169_poll(struct napi_struct *napi, int budget) |
|
3282 { |
|
3283 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
|
3284 struct net_device *dev = tp->dev; |
|
3285 void __iomem *ioaddr = tp->mmio_addr; |
|
3286 int work_done; |
|
3287 |
|
3288 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
|
3289 rtl8169_tx_interrupt(dev, tp, ioaddr); |
|
3290 |
|
3291 if (work_done < budget) { |
|
3292 netif_rx_complete(dev, napi); |
|
3293 |
|
3294 /* We need for force the visibility of tp->intr_mask |
|
3295 * for other CPUs, as we can loose an MSI interrupt |
|
3296 * and potentially wait for a retransmit timeout if we don't. |
|
3297 * The posted write to IntrMask is safe, as it will |
|
3298 * eventually make it to the chip and we won't loose anything |
|
3299 * until it does. |
|
3300 */ |
|
3301 tp->intr_mask = 0xffff; |
|
3302 smp_wmb(); |
|
3303 RTL_W16(IntrMask, tp->intr_event); |
|
3304 } |
|
3305 |
|
3306 return work_done; |
|
3307 } |
|
3308 |
|
3309 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
|
3310 { |
|
3311 struct rtl8169_private *tp = netdev_priv(dev); |
|
3312 |
|
3313 if (tp->mac_version > RTL_GIGA_MAC_VER_06) |
|
3314 return; |
|
3315 |
|
3316 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); |
|
3317 RTL_W32(RxMissed, 0); |
|
3318 } |
|
3319 |
|
3320 static void rtl8169_down(struct net_device *dev) |
|
3321 { |
|
3322 struct rtl8169_private *tp = netdev_priv(dev); |
|
3323 void __iomem *ioaddr = tp->mmio_addr; |
|
3324 unsigned int intrmask; |
|
3325 |
|
3326 rtl8169_delete_timer(dev); |
|
3327 |
|
3328 if (!tp->ecdev) { |
|
3329 netif_stop_queue(dev); |
|
3330 |
|
3331 napi_disable(&tp->napi); |
|
3332 } |
|
3333 |
|
3334 core_down: |
|
3335 if (!tp->ecdev) |
|
3336 spin_lock_irq(&tp->lock); |
|
3337 |
|
3338 rtl8169_asic_down(ioaddr); |
|
3339 |
|
3340 rtl8169_rx_missed(dev, ioaddr); |
|
3341 |
|
3342 if (!tp->ecdev) |
|
3343 spin_unlock_irq(&tp->lock); |
|
3344 |
|
3345 if (!tp->ecdev) |
|
3346 synchronize_irq(dev->irq); |
|
3347 |
|
3348 /* Give a racing hard_start_xmit a few cycles to complete. */ |
|
3349 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
|
3350 |
|
3351 /* |
|
3352 * And now for the 50k$ question: are IRQ disabled or not ? |
|
3353 * |
|
3354 * Two paths lead here: |
|
3355 * 1) dev->close |
|
3356 * -> netif_running() is available to sync the current code and the |
|
3357 * IRQ handler. See rtl8169_interrupt for details. |
|
3358 * 2) dev->change_mtu |
|
3359 * -> rtl8169_poll can not be issued again and re-enable the |
|
3360 * interruptions. Let's simply issue the IRQ down sequence again. |
|
3361 * |
|
3362 * No loop if hotpluged or major error (0xffff). |
|
3363 */ |
|
3364 intrmask = RTL_R16(IntrMask); |
|
3365 if (intrmask && (intrmask != 0xffff)) |
|
3366 goto core_down; |
|
3367 |
|
3368 rtl8169_tx_clear(tp); |
|
3369 |
|
3370 rtl8169_rx_clear(tp); |
|
3371 } |
|
3372 |
|
3373 static int rtl8169_close(struct net_device *dev) |
|
3374 { |
|
3375 struct rtl8169_private *tp = netdev_priv(dev); |
|
3376 struct pci_dev *pdev = tp->pci_dev; |
|
3377 |
|
3378 /* update counters before going down */ |
|
3379 rtl8169_update_counters(dev); |
|
3380 |
|
3381 rtl8169_down(dev); |
|
3382 |
|
3383 if (!tp->ecdev) |
|
3384 free_irq(dev->irq, dev); |
|
3385 |
|
3386 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
3387 tp->RxPhyAddr); |
|
3388 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
3389 tp->TxPhyAddr); |
|
3390 tp->TxDescArray = NULL; |
|
3391 tp->RxDescArray = NULL; |
|
3392 |
|
3393 return 0; |
|
3394 } |
|
3395 |
|
3396 static void rtl_set_rx_mode(struct net_device *dev) |
|
3397 { |
|
3398 struct rtl8169_private *tp = netdev_priv(dev); |
|
3399 void __iomem *ioaddr = tp->mmio_addr; |
|
3400 unsigned long flags; |
|
3401 u32 mc_filter[2]; /* Multicast hash filter */ |
|
3402 int rx_mode; |
|
3403 u32 tmp = 0; |
|
3404 |
|
3405 if (dev->flags & IFF_PROMISC) { |
|
3406 /* Unconditionally log net taps. */ |
|
3407 if (netif_msg_link(tp)) { |
|
3408 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", |
|
3409 dev->name); |
|
3410 } |
|
3411 rx_mode = |
|
3412 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
3413 AcceptAllPhys; |
|
3414 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
3415 } else if ((dev->mc_count > multicast_filter_limit) |
|
3416 || (dev->flags & IFF_ALLMULTI)) { |
|
3417 /* Too many to filter perfectly -- accept all multicasts. */ |
|
3418 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
3419 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
3420 } else { |
|
3421 struct dev_mc_list *mclist; |
|
3422 unsigned int i; |
|
3423 |
|
3424 rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
3425 mc_filter[1] = mc_filter[0] = 0; |
|
3426 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; |
|
3427 i++, mclist = mclist->next) { |
|
3428 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; |
|
3429 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
3430 rx_mode |= AcceptMulticast; |
|
3431 } |
|
3432 } |
|
3433 |
|
3434 spin_lock_irqsave(&tp->lock, flags); |
|
3435 |
|
3436 tmp = rtl8169_rx_config | rx_mode | |
|
3437 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
3438 |
|
3439 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
|
3440 u32 data = mc_filter[0]; |
|
3441 |
|
3442 mc_filter[0] = swab32(mc_filter[1]); |
|
3443 mc_filter[1] = swab32(data); |
|
3444 } |
|
3445 |
|
3446 RTL_W32(MAR0 + 0, mc_filter[0]); |
|
3447 RTL_W32(MAR0 + 4, mc_filter[1]); |
|
3448 |
|
3449 RTL_W32(RxConfig, tmp); |
|
3450 |
|
3451 spin_unlock_irqrestore(&tp->lock, flags); |
|
3452 } |
|
3453 |
|
3454 /** |
|
3455 * rtl8169_get_stats - Get rtl8169 read/write statistics |
|
3456 * @dev: The Ethernet Device to get statistics for |
|
3457 * |
|
3458 * Get TX/RX statistics for rtl8169 |
|
3459 */ |
|
3460 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) |
|
3461 { |
|
3462 struct rtl8169_private *tp = netdev_priv(dev); |
|
3463 void __iomem *ioaddr = tp->mmio_addr; |
|
3464 unsigned long flags; |
|
3465 |
|
3466 if (netif_running(dev)) { |
|
3467 spin_lock_irqsave(&tp->lock, flags); |
|
3468 rtl8169_rx_missed(dev, ioaddr); |
|
3469 spin_unlock_irqrestore(&tp->lock, flags); |
|
3470 } |
|
3471 |
|
3472 return &dev->stats; |
|
3473 } |
|
3474 |
|
3475 #ifdef CONFIG_PM |
|
3476 |
|
3477 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state) |
|
3478 { |
|
3479 struct net_device *dev = pci_get_drvdata(pdev); |
|
3480 struct rtl8169_private *tp = netdev_priv(dev); |
|
3481 void __iomem *ioaddr = tp->mmio_addr; |
|
3482 |
|
3483 if (tp->ecdev) |
|
3484 return; |
|
3485 |
|
3486 if (!netif_running(dev)) |
|
3487 goto out_pci_suspend; |
|
3488 |
|
3489 netif_device_detach(dev); |
|
3490 netif_stop_queue(dev); |
|
3491 |
|
3492 spin_lock_irq(&tp->lock); |
|
3493 |
|
3494 rtl8169_asic_down(ioaddr); |
|
3495 |
|
3496 rtl8169_rx_missed(dev, ioaddr); |
|
3497 |
|
3498 spin_unlock_irq(&tp->lock); |
|
3499 |
|
3500 out_pci_suspend: |
|
3501 pci_save_state(pdev); |
|
3502 pci_enable_wake(pdev, pci_choose_state(pdev, state), |
|
3503 (tp->features & RTL_FEATURE_WOL) ? 1 : 0); |
|
3504 pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
|
3505 |
|
3506 return 0; |
|
3507 } |
|
3508 |
|
3509 static int rtl8169_resume(struct pci_dev *pdev) |
|
3510 { |
|
3511 struct net_device *dev = pci_get_drvdata(pdev); |
|
3512 struct rtl8169_private *tp = netdev_priv(dev); |
|
3513 |
|
3514 if (tp->ecdev) |
|
3515 return; |
|
3516 |
|
3517 pci_set_power_state(pdev, PCI_D0); |
|
3518 pci_restore_state(pdev); |
|
3519 pci_enable_wake(pdev, PCI_D0, 0); |
|
3520 |
|
3521 if (!netif_running(dev)) |
|
3522 goto out; |
|
3523 |
|
3524 netif_device_attach(dev); |
|
3525 |
|
3526 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
3527 out: |
|
3528 return 0; |
|
3529 } |
|
3530 |
|
3531 #endif /* CONFIG_PM */ |
|
3532 |
|
3533 static struct pci_driver rtl8169_pci_driver = { |
|
3534 .name = MODULENAME, |
|
3535 .id_table = rtl8169_pci_tbl, |
|
3536 .probe = rtl8169_init_one, |
|
3537 .remove = __devexit_p(rtl8169_remove_one), |
|
3538 #ifdef CONFIG_PM |
|
3539 .suspend = rtl8169_suspend, |
|
3540 .resume = rtl8169_resume, |
|
3541 #endif |
|
3542 }; |
|
3543 |
|
3544 static int __init rtl8169_init_module(void) |
|
3545 { |
|
3546 return pci_register_driver(&rtl8169_pci_driver); |
|
3547 } |
|
3548 |
|
3549 static void __exit rtl8169_cleanup_module(void) |
|
3550 { |
|
3551 pci_unregister_driver(&rtl8169_pci_driver); |
|
3552 } |
|
3553 |
|
3554 module_init(rtl8169_init_module); |
|
3555 module_exit(rtl8169_cleanup_module); |