1 /******************************************************************************

     2  *

     3  *  drv_8139too.c

     4  *

     5  *  EtherCAT-Treiber für RTL8139-kompatible Netzwerkkarten.

     6  *

     7  *  Autoren: Wilhelm Hagemeister, Florian Pose

     8  *

     9  *  $Date$

    10  *  $Author$

    11  *

    12  *  (C) Copyright IgH 2005

    13  *  Ingenieurgemeinschaft IgH

    14  *  Heinz-Bäcker Str. 34

    15  *  D-45356 Essen

    16  *  Tel.: +49 201/61 99 31

    17  *  Fax.: +49 201/61 98 36

    18  *  E-mail: sp@igh-essen.com

    19  *

    20  ******************************************************************************/

    21 

    22 /*

    23 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    24 

    25 	Maintained by Jeff Garzik <jgarzik@mandrakesoft.com>

    26 	Copyright 2000-2002 Jeff Garzik

    27 

    28 	Much code comes from Donald Becker's rtl8139.c driver,

    29 	versions 1.13 and older.  This driver was originally based

    30 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    31 

    32 	-----<snip>-----

    33 

    34         	Written 1997-2001 by Donald Becker.

    35 		This software may be used and distributed according to the

    36 		terms of the GNU General Public License (GPL), incorporated

    37 		herein by reference.  Drivers based on or derived from this

    38 		code fall under the GPL and must retain the authorship,

    39 		copyright and license notice.  This file is not a complete

    40 		program and may only be used when the entire operating

    41 		system is licensed under the GPL.

    42 

    43 		This driver is for boards based on the RTL8129 and RTL8139

    44 		PCI ethernet chips.

    45 

    46 		The author may be reached as becker@scyld.com, or C/O Scyld

    47 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    48 		MD 21403

    49 

    50 		Support and updates available at

    51 		http://www.scyld.com/network/rtl8139.html

    52 

    53 		Twister-tuning table provided by Kinston

    54 		<shangh@realtek.com.tw>.

    55 

    56 	-----<snip>-----

    57 

    58 	This software may be used and distributed according to the terms

    59 	of the GNU General Public License, incorporated herein by reference.

    60 

    61 	Contributors:

    62 

    63 		Donald Becker - he wrote the original driver, kudos to him!

    64 		(but please don't e-mail him for support, this isn't his driver)

    65 

    66 		Tigran Aivazian - bug fixes, skbuff free cleanup

    67 

    68 		Martin Mares - suggestions for PCI cleanup

    69 

    70 		David S. Miller - PCI DMA and softnet updates

    71 

    72 		Ernst Gill - fixes ported from BSD driver

    73 

    74 		Daniel Kobras - identified specific locations of

    75 			posted MMIO write bugginess

    76 

    77 		Gerard Sharp - bug fix, testing and feedback

    78 

    79 		David Ford - Rx ring wrap fix

    80 

    81 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    82 		to find and fix a crucial bug on older chipsets.

    83 

    84 		Donald Becker/Chris Butterworth/Marcus Westergren -

    85 		Noticed various Rx packet size-related buglets.

    86 

    87 		Santiago Garcia Mantinan - testing and feedback

    88 

    89 		Jens David - 2.2.x kernel backports

    90 

    91 		Martin Dennett - incredibly helpful insight on undocumented

    92 		features of the 8139 chips

    93 

    94 		Jean-Jacques Michel - bug fix

    95 

    96 		Tobias Ringström - Rx interrupt status checking suggestion

    97 

    98 		Andrew Morton - Clear blocked signals, avoid

    99 		buffer overrun setting current->comm.

   100 

   101 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   102 

   103 		Robert Kuebel - Save kernel thread from dying on any signal.

   104 

   105 	Submitting bug reports:

   106 

   107 		"rtl8139-diag -mmmaaavvveefN" output

   108 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   109 

   110 		See 8139too.txt for more details.

   111 

   112 */

   113 

   114 #define DRV_NAME	"8139too_ecat"

   115 #define DRV_VERSION	"0.9.26"

   116 

   117 

   118 #include <linux/config.h>

   119 #include <linux/module.h>

   120 #include <linux/kernel.h>

   121 #include <linux/compiler.h>

   122 #include <linux/pci.h>

   123 #include <linux/init.h>

   124 #include <linux/ioport.h>

   125 #include <linux/netdevice.h>

   126 #include <linux/etherdevice.h>

   127 #include <linux/rtnetlink.h>

   128 #include <linux/delay.h>

   129 #include <linux/ethtool.h>

   130 #include <linux/mii.h>

   131 #include <linux/completion.h>

   132 #include <linux/crc32.h>

   133 #include <asm/io.h>

   134 #include <asm/uaccess.h>

   135 

   136 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   137 

   138 #include "ec_device.h"

   139 #include "ec_dbg.h"

   140 

   141 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   142 

   143 #define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   144 #define PFX DRV_NAME ": "

   145 

   146 

   147 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   148 #ifdef CONFIG_8139TOO_PIO

   149 #define USE_IO_OPS 1

   150 #endif

   151 

   152 /* define to 1 to enable copious debugging info */

   153 //#define RTL8139_DEBUG 1

   154 #undef RTL8139_DEBUG

   155 

   156 /* define to 1 to disable lightweight runtime debugging checks */

   157 #undef RTL8139_NDEBUG

   158 

   159 

   160 #ifdef RTL8139_DEBUG

   161 /* note: prints function name for you */

   162 #  define DPRINTK(fmt, args...) EC_DBG(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   163 #else

   164 #  define DPRINTK(fmt, args...)

   165 #endif

   166 

   167 #ifdef RTL8139_NDEBUG

   168 #  define assert(expr) do {} while (0)

   169 #else

   170 #  define assert(expr) \

   171         if(!(expr)) {					\

   172         printk( "Assertion failed! %s,%s,%s,line=%d\n",	\

   173         #expr,__FILE__,__FUNCTION__,__LINE__);		\

   174         }

   175 #endif

   176 

   177 

   178 /* A few user-configurable values. */

   179 /* media options */

   180 #define MAX_UNITS 8

   181 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   182 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   183 

   184 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */

   185 static int max_interrupt_work = 20;

   186 

   187 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   188    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   189 static int multicast_filter_limit = 32;

   190 

   191 /* bitmapped message enable number */

   192 static int debug = -1;

   193 

   194 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   195 

   196 // Device index for EtherCAT device selection

   197 static int ec_device_index = -1;

   198 

   199 //#define ECAT_DEBUG

   200 

   201 EtherCAT_device_t rtl_ecat_dev;

   202 

   203 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   204 

   205 /* Size of the in-memory receive ring. */

   206 #define RX_BUF_LEN_IDX	2	/* 0==8K, 1==16K, 2==32K, 3==64K */

   207 #define RX_BUF_LEN	(8192 << RX_BUF_LEN_IDX)

   208 #define RX_BUF_PAD	16

   209 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   210 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   211 

   212 /* Number of Tx descriptor registers. */

   213 #define NUM_TX_DESC	4

   214 

   215 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   216 #define MAX_ETH_FRAME_SIZE	1536

   217 

   218 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   219 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   220 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   221 

   222 /* PCI Tuning Parameters

   223    Threshold is bytes transferred to chip before transmission starts. */

   224 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   225 

   226 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   227 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   228 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   229 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   230 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   231 

   232 /* Operational parameters that usually are not changed. */

   233 /* Time in jiffies before concluding the transmitter is hung. */

   234 #define TX_TIMEOUT  (6*HZ)

   235 

   236 

   237 enum {

   238 	HAS_MII_XCVR = 0x010000,

   239 	HAS_CHIP_XCVR = 0x020000,

   240 	HAS_LNK_CHNG = 0x040000,

   241 };

   242 

   243 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   244 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   245 #define RTL_MIN_IO_SIZE 0x80

   246 #define RTL8139B_IO_SIZE 256

   247 

   248 #define RTL8129_CAPS	HAS_MII_XCVR

   249 #define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   250 

   251 typedef enum {

   252 	RTL8139 = 0,

   253 	RTL8139_CB,

   254 	SMC1211TX,

   255 	/*MPX5030,*/

   256 	DELTA8139,

   257 	ADDTRON8139,

   258 	DFE538TX,

   259 	DFE690TXD,

   260 	FE2000VX,

   261 	ALLIED8139,

   262 	RTL8129,

   263 	FNW3603TX,

   264 	FNW3800TX,

   265 } board_t;

   266 

   267 

   268 /* indexed by board_t, above */

   269 static struct {

   270 	const char *name;

   271 	u32 hw_flags;

   272 } board_info[] __devinitdata = {

   273 	{ "RealTek RTL8139 Fast Ethernet", RTL8139_CAPS },

   274 	{ "RealTek RTL8139B PCI/CardBus", RTL8139_CAPS },

   275 	{ "SMC1211TX EZCard 10/100 (RealTek RTL8139)", RTL8139_CAPS },

   276 /*	{ MPX5030, "Accton MPX5030 (RealTek RTL8139)", RTL8139_CAPS },*/

   277 	{ "Delta Electronics 8139 10/100BaseTX", RTL8139_CAPS },

   278 	{ "Addtron Technolgy 8139 10/100BaseTX", RTL8139_CAPS },

   279 	{ "D-Link DFE-538TX (RealTek RTL8139)", RTL8139_CAPS },

   280 	{ "D-Link DFE-690TXD (RealTek RTL8139)", RTL8139_CAPS },

   281 	{ "AboCom FE2000VX (RealTek RTL8139)", RTL8139_CAPS },

   282 	{ "Allied Telesyn 8139 CardBus", RTL8139_CAPS },

   283 	{ "RealTek RTL8129", RTL8129_CAPS },

   284 	{ "Planex FNW-3603-TX 10/100 CardBus", RTL8139_CAPS },

   285 	{ "Planex FNW-3800-TX 10/100 CardBus", RTL8139_CAPS },

   286 };

   287 

   288 

   289 static struct pci_device_id rtl8139_pci_tbl[] __devinitdata = {

   290 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139_CB },

   292 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },

   293 /*	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/

   294 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },

   295 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },

   296 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE538TX },

   297 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE690TXD },

   298 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FE2000VX },

   299 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ALLIED8139 },

   300 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FNW3603TX },

   301 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FNW3800TX },

   302 

   303 #ifdef CONFIG_8139TOO_8129

   304 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   305 #endif

   306 

   307 	/* some crazy cards report invalid vendor ids like

   308 	 * 0x0001 here.  The other ids are valid and constant,

   309 	 * so we simply don't match on the main vendor id.

   310 	 */

   311 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   312 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, DFE538TX },

   313 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, FE2000VX },

   314 

   315 	{0,}

   316 };

   317 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   318 

   319 static struct {

   320 	const char str[ETH_GSTRING_LEN];

   321 } ethtool_stats_keys[] = {

   322 	{ "early_rx" },

   323 	{ "tx_buf_mapped" },

   324 	{ "tx_timeouts" },

   325 	{ "rx_lost_in_ring" },

   326 };

   327 

   328 /* The rest of these values should never change. */

   329 

   330 /* Symbolic offsets to registers. */

   331 enum RTL8139_registers {

   332 	MAC0 = 0,		/* Ethernet hardware address. */

   333 	MAR0 = 8,		/* Multicast filter. */

   334 	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   335 	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   336 	RxBuf = 0x30,

   337 	ChipCmd = 0x37,

   338 	RxBufPtr = 0x38,

   339 	RxBufAddr = 0x3A,

   340 	IntrMask = 0x3C,

   341 	IntrStatus = 0x3E,

   342 	TxConfig = 0x40,

   343 	ChipVersion = 0x43,

   344 	RxConfig = 0x44,

   345 	Timer = 0x48,		/* A general-purpose counter. */

   346 	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   347 	Cfg9346 = 0x50,

   348 	Config0 = 0x51,

   349 	Config1 = 0x52,

   350 	FlashReg = 0x54,

   351 	MediaStatus = 0x58,

   352 	Config3 = 0x59,

   353 	Config4 = 0x5A,		/* absent on RTL-8139A */

   354 	HltClk = 0x5B,

   355 	MultiIntr = 0x5C,

   356 	TxSummary = 0x60,

   357 	BasicModeCtrl = 0x62,

   358 	BasicModeStatus = 0x64,

   359 	NWayAdvert = 0x66,

   360 	NWayLPAR = 0x68,

   361 	NWayExpansion = 0x6A,

   362 	/* Undocumented registers, but required for proper operation. */

   363 	FIFOTMS = 0x70,		/* FIFO Control and test. */

   364 	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   365 	PARA78 = 0x78,

   366 	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   367 	Config5 = 0xD8,		/* absent on RTL-8139A */

   368 };

   369 

   370 enum ClearBitMasks {

   371 	MultiIntrClear = 0xF000,

   372 	ChipCmdClear = 0xE2,

   373 	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   374 };

   375 

   376 enum ChipCmdBits {

   377 	CmdReset = 0x10,

   378 	CmdRxEnb = 0x08,

   379 	CmdTxEnb = 0x04,

   380 	RxBufEmpty = 0x01,

   381 };

   382 

   383 /* Interrupt register bits, using my own meaningful names. */

   384 enum IntrStatusBits {

   385 	PCIErr = 0x8000,

   386 	PCSTimeout = 0x4000,

   387 	RxFIFOOver = 0x40,

   388 	RxUnderrun = 0x20,

   389 	RxOverflow = 0x10,

   390 	TxErr = 0x08,

   391 	TxOK = 0x04,

   392 	RxErr = 0x02,

   393 	RxOK = 0x01,

   394 

   395 	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   396 };

   397 

   398 enum TxStatusBits {

   399 	TxHostOwns = 0x2000,

   400 	TxUnderrun = 0x4000,

   401 	TxStatOK = 0x8000,

   402 	TxOutOfWindow = 0x20000000,

   403 	TxAborted = 0x40000000,

   404 	TxCarrierLost = 0x80000000,

   405 };

   406 enum RxStatusBits {

   407 	RxMulticast = 0x8000,

   408 	RxPhysical = 0x4000,

   409 	RxBroadcast = 0x2000,

   410 	RxBadSymbol = 0x0020,

   411 	RxRunt = 0x0010,

   412 	RxTooLong = 0x0008,

   413 	RxCRCErr = 0x0004,

   414 	RxBadAlign = 0x0002,

   415 	RxStatusOK = 0x0001,

   416 };

   417 

   418 /* Bits in RxConfig. */

   419 enum rx_mode_bits {

   420 	AcceptErr = 0x20,

   421 	AcceptRunt = 0x10,

   422 	AcceptBroadcast = 0x08,

   423 	AcceptMulticast = 0x04,

   424 	AcceptMyPhys = 0x02,

   425 	AcceptAllPhys = 0x01,

   426 };

   427 

   428 /* Bits in TxConfig. */

   429 enum tx_config_bits {

   430 	TxIFG1 = (1 << 25),	/* Interframe Gap Time */

   431 	TxIFG0 = (1 << 24),	/* Enabling these bits violates IEEE 802.3 */

   432 	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   433 	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   434 	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   435 	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   436 	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   437 

   438 	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   439 };

   440 

   441 /* Bits in Config1 */

   442 enum Config1Bits {

   443 	Cfg1_PM_Enable = 0x01,

   444 	Cfg1_VPD_Enable = 0x02,

   445 	Cfg1_PIO = 0x04,

   446 	Cfg1_MMIO = 0x08,

   447 	LWAKE = 0x10,		/* not on 8139, 8139A */

   448 	Cfg1_Driver_Load = 0x20,

   449 	Cfg1_LED0 = 0x40,

   450 	Cfg1_LED1 = 0x80,

   451 	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   452 	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   453 };

   454 

   455 /* Bits in Config3 */

   456 enum Config3Bits {

   457 	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   458 	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   459 	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   460 	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   461 	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   462 	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   463 	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   464 	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   465 };

   466 

   467 /* Bits in Config4 */

   468 enum Config4Bits {

   469 	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   470 };

   471 

   472 /* Bits in Config5 */

   473 enum Config5Bits {

   474 	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   475 	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   476 	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   477 	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   478 	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   479 	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   480 	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   481 };

   482 

   483 enum RxConfigBits {

   484 	/* rx fifo threshold */

   485 	RxCfgFIFOShift = 13,

   486 	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   487 

   488 	/* Max DMA burst */

   489 	RxCfgDMAShift = 8,

   490 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   491 

   492 	/* rx ring buffer length */

   493 	RxCfgRcv8K = 0,

   494 	RxCfgRcv16K = (1 << 11),

   495 	RxCfgRcv32K = (1 << 12),

   496 	RxCfgRcv64K = (1 << 11) | (1 << 12),

   497 

   498 	/* Disable packet wrap at end of Rx buffer */

   499 	RxNoWrap = (1 << 7),

   500 };

   501 

   502 

   503 /* Twister tuning parameters from RealTek.

   504    Completely undocumented, but required to tune bad links on some boards. */

   505 enum CSCRBits {

   506 	CSCR_LinkOKBit = 0x0400,

   507 	CSCR_LinkChangeBit = 0x0800,

   508 	CSCR_LinkStatusBits = 0x0f000,

   509 	CSCR_LinkDownOffCmd = 0x003c0,

   510 	CSCR_LinkDownCmd = 0x0f3c0,

   511 };

   512 

   513 

   514 enum Cfg9346Bits {

   515 	Cfg9346_Lock = 0x00,

   516 	Cfg9346_Unlock = 0xC0,

   517 };

   518 

   519 #ifdef CONFIG_8139TOO_TUNE_TWISTER

   520 

   521 enum TwisterParamVals {

   522 	PARA78_default	= 0x78fa8388,

   523 	PARA7c_default	= 0xcb38de43,	/* param[0][3] */

   524 	PARA7c_xxx	= 0xcb38de43,

   525 };

   526 

   527 static const unsigned long param[4][4] = {

   528 	{0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},

   529 	{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},

   530 	{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},

   531 	{0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}

   532 };

   533 

   534 #endif /* CONFIG_8139TOO_TUNE_TWISTER */

   535 

   536 typedef enum {

   537 	CH_8139 = 0,

   538 	CH_8139_K,

   539 	CH_8139A,

   540 	CH_8139B,

   541 	CH_8130,

   542 	CH_8139C,

   543 } chip_t;

   544 

   545 enum chip_flags {

   546 	HasHltClk = (1 << 0),

   547 	HasLWake = (1 << 1),

   548 };

   549 

   550 

   551 /* directly indexed by chip_t, above */

   552 const static struct {

   553 	const char *name;

   554 	u8 version; /* from RTL8139C docs */

   555 	u32 RxConfigMask; /* should clear the bits supported by this chip */

   556 	u32 flags;

   557 } rtl_chip_info[] = {

   558 	{ "RTL-8139",

   559 	  0x40,

   560 	  0xf0fe0040, /* XXX copied from RTL8139A, verify */

   561 	  HasHltClk,

   562 	},

   563 

   564 	{ "RTL-8139 rev K",

   565 	  0x60,

   566 	  0xf0fe0040,

   567 	  HasHltClk,

   568 	},

   569 

   570 	{ "RTL-8139A",

   571 	  0x70,

   572 	  0xf0fe0040,

   573 	  HasHltClk, /* XXX undocumented? */

   574 	},

   575 

   576 	{ "RTL-8139B",

   577 	  0x78,

   578 	  0xf0fc0040,

   579 	  HasLWake,

   580 	},

   581 

   582 	{ "RTL-8130",

   583 	  0x7C,

   584 	  0xf0fe0040, /* XXX copied from RTL8139A, verify */

   585 	  HasLWake,

   586 	},

   587 

   588 	{ "RTL-8139C",

   589 	  0x74,

   590 	  0xf0fc0040, /* XXX copied from RTL8139B, verify */

   591 	  HasLWake,

   592 	},

   593 

   594 };

   595 

   596 struct rtl_extra_stats {

   597 	unsigned long early_rx;

   598 	unsigned long tx_buf_mapped;

   599 	unsigned long tx_timeouts;

   600 	unsigned long rx_lost_in_ring;

   601 };

   602 

   603 struct rtl8139_private {

   604 	void *mmio_addr;

   605 	int drv_flags;

   606 	struct pci_dev *pci_dev;

   607 	struct net_device_stats stats;

   608 	unsigned char *rx_ring;

   609 	unsigned int cur_rx;	/* Index into the Rx buffer of next Rx pkt. */

   610 	unsigned int tx_flag;

   611 	unsigned long cur_tx;

   612 	unsigned long dirty_tx;

   613 	unsigned char *tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   614 	unsigned char *tx_bufs;	/* Tx bounce buffer region. */

   615 	dma_addr_t rx_ring_dma;

   616 	dma_addr_t tx_bufs_dma;

   617 	signed char phys[4];		/* MII device addresses. */

   618 	char twistie, twist_row, twist_col;	/* Twister tune state. */

   619 	unsigned int default_port:4;	/* Last dev->if_port value. */

   620 	spinlock_t lock;

   621 	chip_t chipset;

   622 	pid_t thr_pid;

   623 	wait_queue_head_t thr_wait;

   624 	struct completion thr_exited;

   625 	u32 rx_config;

   626 	struct rtl_extra_stats xstats;

   627 	int time_to_die;

   628 	struct mii_if_info mii;

   629 	unsigned int regs_len;

   630 };

   631 

   632 MODULE_AUTHOR ("Jeff Garzik <jgarzik@mandrakesoft.com>");

   633 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");

   634 MODULE_LICENSE("GPL");

   635 

   636 MODULE_PARM (multicast_filter_limit, "i");

   637 MODULE_PARM (max_interrupt_work, "i");

   638 MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");

   639 MODULE_PARM (full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");

   640 MODULE_PARM (debug, "i");

   641 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   642 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   643 MODULE_PARM_DESC (max_interrupt_work, "8139too maximum events handled per interrupt");

   644 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   645 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   646 

   647 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   648 

   649 MODULE_PARM(ec_device_index, "i");

   650 MODULE_PARM_DESC(ec_device_index, "Index of the device reserved for EtherCAT.");

   651 

   652 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   653 

   654 static int read_eeprom (void *ioaddr, int location, int addr_len);

   655 static int rtl8139_open (struct net_device *dev);

   656 static int mdio_read (struct net_device *dev, int phy_id, int location);

   657 static void mdio_write (struct net_device *dev, int phy_id, int location,

   658 			int val);

   659 static int rtl8139_thread (void *data);

   660 static void rtl8139_tx_timeout (struct net_device *dev);

   661 static void rtl8139_init_ring (struct net_device *dev);

   662 static int rtl8139_start_xmit (struct sk_buff *skb,

   663 			       struct net_device *dev);

   664 static void rtl8139_interrupt (int irq, void *dev_instance,

   665 			       struct pt_regs *regs);

   666 static int rtl8139_close (struct net_device *dev);

   667 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   668 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   669 static void rtl8139_set_rx_mode (struct net_device *dev);

   670 static void __set_rx_mode (struct net_device *dev);

   671 static void rtl8139_hw_start (struct net_device *dev);

   672 

   673 #ifdef USE_IO_OPS

   674 

   675 #define RTL_R8(reg)		inb (((unsigned long)ioaddr) + (reg))

   676 #define RTL_R16(reg)		inw (((unsigned long)ioaddr) + (reg))

   677 #define RTL_R32(reg)		((unsigned long) inl (((unsigned long)ioaddr) + (reg)))

   678 #define RTL_W8(reg, val8)	outb ((val8), ((unsigned long)ioaddr) + (reg))

   679 #define RTL_W16(reg, val16)	outw ((val16), ((unsigned long)ioaddr) + (reg))

   680 #define RTL_W32(reg, val32)	outl ((val32), ((unsigned long)ioaddr) + (reg))

   681 #define RTL_W8_F		RTL_W8

   682 #define RTL_W16_F		RTL_W16

   683 #define RTL_W32_F		RTL_W32

   684 #undef readb

   685 #undef readw

   686 #undef readl

   687 #undef writeb

   688 #undef writew

   689 #undef writel

   690 #define readb(addr) inb((unsigned long)(addr))

   691 #define readw(addr) inw((unsigned long)(addr))

   692 #define readl(addr) inl((unsigned long)(addr))

   693 #define writeb(val,addr) outb((val),(unsigned long)(addr))

   694 #define writew(val,addr) outw((val),(unsigned long)(addr))

   695 #define writel(val,addr) outl((val),(unsigned long)(addr))

   696 

   697 #else

   698 

   699 /* write MMIO register, with flush */

   700 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   701 #define RTL_W8_F(reg, val8)	do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)

   702 #define RTL_W16_F(reg, val16)	do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)

   703 #define RTL_W32_F(reg, val32)	do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)

   704 

   705 

   706 #define MMIO_FLUSH_AUDIT_COMPLETE 1

   707 #if MMIO_FLUSH_AUDIT_COMPLETE

   708 

   709 /* write MMIO register */

   710 #define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))

   711 #define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))

   712 #define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

   713 

   714 #else

   715 

   716 /* write MMIO register, then flush */

   717 #define RTL_W8		RTL_W8_F

   718 #define RTL_W16		RTL_W16_F

   719 #define RTL_W32		RTL_W32_F

   720 

   721 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */

   722 

   723 /* read MMIO register */

   724 #define RTL_R8(reg)		readb (ioaddr + (reg))

   725 #define RTL_R16(reg)		readw (ioaddr + (reg))

   726 #define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

   727 

   728 #endif /* USE_IO_OPS */

   729 

   730 static const u16 rtl8139_intr_mask =

   731 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   732 	TxErr | TxOK | RxErr | RxOK;

   733 

   734 static const unsigned int rtl8139_rx_config =

   735 	RxCfgRcv32K | RxNoWrap |

   736 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   737 	(RX_DMA_BURST << RxCfgDMAShift);

   738 

   739 static const unsigned int rtl8139_tx_config =

   740 	(TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   741 

   742 static void __rtl8139_cleanup_dev (struct net_device *dev)

   743 {

   744 	struct rtl8139_private *tp;

   745 	struct pci_dev *pdev;

   746 

   747 	assert (dev != NULL);

   748 	assert (dev->priv != NULL);

   749 

   750 	tp = dev->priv;

   751 	assert (tp->pci_dev != NULL);

   752 	pdev = tp->pci_dev;

   753 

   754 #ifndef USE_IO_OPS

   755 	if (tp->mmio_addr)

   756 		iounmap (tp->mmio_addr);

   757 #endif /* !USE_IO_OPS */

   758 

   759 	/* it's ok to call this even if we have no regions to free */

   760 	pci_release_regions (pdev);

   761 

   762 #ifndef RTL8139_NDEBUG

   763 	/* poison memory before freeing */

   764 	memset (dev, 0xBC,

   765 		sizeof (struct net_device) +

   766 		sizeof (struct rtl8139_private));

   767 #endif /* RTL8139_NDEBUG */

   768 

   769 	kfree (dev);

   770 

   771 	pci_set_drvdata (pdev, NULL);

   772 }

   773 

   774 

   775 static void rtl8139_chip_reset (void *ioaddr)

   776 {

   777 	int i;

   778 #ifdef ECAT_DEBUG

   779 	int succ = 0;

   780 #endif

   781 	/* Soft reset the chip. */

   782 	RTL_W8 (ChipCmd, CmdReset);

   783 

   784 	/* Check that the chip has finished the reset. */

   785 	for (i = 1000; i > 0; i--) {

   786 		barrier();

   787 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0) {

   788 #ifdef ECAT_DEBUG

   789 		    succ = 1;

   790 #endif

   791 		    break;

   792 		}

   793 		udelay (10);

   794 	}

   795 #ifdef ECAT_DEBUG

   796 	EC_DBG("rtl8139 chipreset");

   797 	if(succ == 0)

   798 	    EC_DBG("failed");

   799 	else

   800 	    EC_DBG("success at count %d",i);

   801 #endif

   802 }

   803 

   804 

   805 static int __devinit rtl8139_init_board (struct pci_dev *pdev,

   806 					 struct net_device **dev_out)

   807 {

   808 	void *ioaddr;

   809 	struct net_device *dev;

   810 	struct rtl8139_private *tp;

   811 	u8 tmp8;

   812 	int rc;

   813 	unsigned int i;

   814 	u32 pio_start, pio_end, pio_flags, pio_len;

   815 	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;

   816 	u32 tmp;

   817 

   818 	assert (pdev != NULL);

   819 

   820 	*dev_out = NULL;

   821 

   822 	/* dev and dev->priv zeroed in alloc_etherdev */

   823 	dev = alloc_etherdev (sizeof (*tp));

   824 	if (dev == NULL) {

   825 		EC_DBG (KERN_ERR PFX "%s: Unable to alloc new net device\n", pdev->slot_name);

   826 		return -ENOMEM;

   827 	}

   828 	SET_MODULE_OWNER(dev);

   829 	tp = dev->priv;

   830 	tp->pci_dev = pdev;

   831 

   832 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   833 	rc = pci_enable_device (pdev);

   834 	if (rc)

   835 		goto err_out;

   836 

   837 	pio_start = pci_resource_start (pdev, 0);

   838 	pio_end = pci_resource_end (pdev, 0);

   839 	pio_flags = pci_resource_flags (pdev, 0);

   840 	pio_len = pci_resource_len (pdev, 0);

   841 

   842 	mmio_start = pci_resource_start (pdev, 1);

   843 	mmio_end = pci_resource_end (pdev, 1);

   844 	mmio_flags = pci_resource_flags (pdev, 1);

   845 	mmio_len = pci_resource_len (pdev, 1);

   846 

   847 	/* set this immediately, we need to know before

   848 	 * we talk to the chip directly */

   849 	DPRINTK("PIO region size == 0x%02X\n", pio_len);

   850 	DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);

   851 

   852 #ifdef USE_IO_OPS

   853 	/* make sure PCI base addr 0 is PIO */

   854 	if (!(pio_flags & IORESOURCE_IO)) {

   855 		EC_DBG (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pdev->slot_name);

   856 		rc = -ENODEV;

   857 		goto err_out;

   858 	}

   859 	/* check for weird/broken PCI region reporting */

   860 	if (pio_len < RTL_MIN_IO_SIZE) {

   861 		EC_DBG (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pdev->slot_name);

   862 		rc = -ENODEV;

   863 		goto err_out;

   864 	}

   865 #else

   866 	/* make sure PCI base addr 1 is MMIO */

   867 	if (!(mmio_flags & IORESOURCE_MEM)) {

   868 		EC_DBG (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pdev->slot_name);

   869 		rc = -ENODEV;

   870 		goto err_out;

   871 	}

   872 	if (mmio_len < RTL_MIN_IO_SIZE) {

   873 		EC_DBG (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pdev->slot_name);

   874 		rc = -ENODEV;

   875 		goto err_out;

   876 	}

   877 #endif

   878 

   879 	rc = pci_request_regions (pdev, "8139too");

   880 	if (rc)

   881 		goto err_out;

   882 

   883 	/* enable PCI bus-mastering */

   884 	pci_set_master (pdev);

   885 

   886 #ifdef USE_IO_OPS

   887 	ioaddr = (void *) pio_start;

   888 	dev->base_addr = pio_start;

   889 	tp->mmio_addr = ioaddr;

   890 	tp->regs_len = pio_len;

   891 #else

   892 	/* ioremap MMIO region */

   893 	ioaddr = ioremap (mmio_start, mmio_len);

   894 	if (ioaddr == NULL) {

   895 		EC_DBG (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pdev->slot_name);

   896 		rc = -EIO;

   897 		goto err_out;

   898 	}

   899 	dev->base_addr = (long) ioaddr;

   900 	tp->mmio_addr = ioaddr;

   901 	tp->regs_len = mmio_len;

   902 #endif /* USE_IO_OPS */

   903 

   904 	/* Bring old chips out of low-power mode. */

   905 	RTL_W8 (HltClk, 'R');

   906 

   907 	/* check for missing/broken hardware */

   908 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   909 		EC_DBG (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",

   910 			pdev->slot_name);

   911 		rc = -EIO;

   912 		goto err_out;

   913 	}

   914 

   915 	/* identify chip attached to board */

   916 	tmp = RTL_R8 (ChipVersion);

   917 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   918 		if (tmp == rtl_chip_info[i].version) {

   919 			tp->chipset = i;

   920 			goto match;

   921 		}

   922 

   923 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   924 	EC_DBG (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",

   925 		pdev->slot_name);

   926 	EC_DBG (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pdev->slot_name, RTL_R32 (TxConfig));

   927 	tp->chipset = 0;

   928 

   929 match:

   930 	DPRINTK ("chipset id (%d) == index %d, '%s'\n",

   931 		tmp,

   932 		tp->chipset,

   933 		rtl_chip_info[tp->chipset].name);

   934 

   935 	if (tp->chipset >= CH_8139B) {

   936 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   937 		DPRINTK("PCI PM wakeup\n");

   938 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   939 		    (tmp8 & LWAKE))

   940 			new_tmp8 &= ~LWAKE;

   941 		new_tmp8 |= Cfg1_PM_Enable;

   942 		if (new_tmp8 != tmp8) {

   943 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   944 			RTL_W8 (Config1, tmp8);

   945 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   946 		}

   947 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   948 			tmp8 = RTL_R8 (Config4);

   949 			if (tmp8 & LWPTN)

   950 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   951 		}

   952 	} else {

   953 		DPRINTK("Old chip wakeup\n");

   954 		tmp8 = RTL_R8 (Config1);

   955 		tmp8 &= ~(SLEEP | PWRDN);

   956 		RTL_W8 (Config1, tmp8);

   957 	}

   958 

   959 	rtl8139_chip_reset (ioaddr);

   960 

   961 	*dev_out = dev;

   962 	return 0;

   963 

   964 err_out:

   965 	__rtl8139_cleanup_dev (dev);

   966 	return rc;

   967 }

   968 

   969 

   970 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

   971 				       const struct pci_device_id *ent)

   972 {

   973 	struct net_device *dev = NULL;

   974 	struct rtl8139_private *tp;

   975 	int i, addr_len, option;

   976 	void *ioaddr;

   977 	static int board_idx = -1;

   978 	u8 pci_rev;

   979 

   980 	assert (pdev != NULL);

   981 	assert (ent != NULL);

   982 

   983 	board_idx++;

   984 

   985 

   986 	/* when we're built into the kernel, the driver version message

   987 	 * is only printed if at least one 8139 board has been found

   988 	 */

   989 #ifndef MODULE

   990 	{

   991 		static int printed_version;

   992 		if (!printed_version++)

   993 			EC_DBG (KERN_INFO RTL8139_DRIVER_NAME "\n");

   994 	}

   995 #endif

   996 

   997 	pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);

   998 

   999 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1000 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {

  1001 		EC_DBG(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",

  1002 		       pdev->slot_name, pdev->vendor, pdev->device, pci_rev);

  1003 		EC_DBG(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");

  1004 	}

  1005 

  1006 	i = rtl8139_init_board (pdev, &dev);

  1007 	if (i < 0)

  1008 		return i;

  1009 

  1010 	/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

  1011 

  1012 	if (board_idx == ec_device_index)

  1013         {

  1014           EC_DBG("EtherCAT registering board %d.\n", board_idx);

  1015 

  1016           if (EtherCAT_device_assign(&rtl_ecat_dev, dev) < 0)

  1017             goto err_out;

  1018 

  1019 	  strcpy(dev->name,"ECAT");  //device name überschreiben

  1020 	}

  1021 

  1022 	/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

  1023 

  1024 	tp = dev->priv;

  1025 	ioaddr = tp->mmio_addr;

  1026 

  1027 	assert (ioaddr != NULL);

  1028 	assert (dev != NULL);

  1029 	assert (tp != NULL);

  1030 

  1031 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1032 	for (i = 0; i < 3; i++)

  1033 		((u16 *) (dev->dev_addr))[i] =

  1034 		    le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));

  1035 

  1036 	/* The Rtl8139-specific entries in the device structure. */

  1037 	dev->open = rtl8139_open;

  1038 	dev->hard_start_xmit = rtl8139_start_xmit;

  1039 	dev->stop = rtl8139_close;

  1040 	dev->get_stats = rtl8139_get_stats;

  1041 	dev->set_multicast_list = rtl8139_set_rx_mode;

  1042 	dev->do_ioctl = netdev_ioctl;

  1043 	dev->tx_timeout = rtl8139_tx_timeout;

  1044 	dev->watchdog_timeo = TX_TIMEOUT;

  1045 	dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;

  1046 

  1047 	dev->irq = pdev->irq;

  1048 

  1049 	/* dev->priv/tp zeroed and aligned in init_etherdev */

  1050 	tp = dev->priv;

  1051 

  1052 	/* note: tp->chipset set in rtl8139_init_board */

  1053 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1054 	tp->mmio_addr = ioaddr;

  1055 	spin_lock_init (&tp->lock);

  1056 

  1057 	/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

  1058 

  1059 	if (board_idx == ec_device_index)

  1060         {

  1061           rtl_ecat_dev.lock = &tp->lock;

  1062 	}

  1063 

  1064 	/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

  1065 

  1066 	init_waitqueue_head (&tp->thr_wait);

  1067 	init_completion (&tp->thr_exited);

  1068 	tp->mii.dev = dev;

  1069 	tp->mii.mdio_read = mdio_read;

  1070 	tp->mii.mdio_write = mdio_write;

  1071 	tp->mii.phy_id_mask = 0x3f;

  1072 	tp->mii.reg_num_mask = 0x1f;

  1073 

  1074 	/* dev is fully set up and ready to use now */

  1075 

  1076 	/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

  1077 

  1078 	/* EtherCAT-Karten nicht beim Stack anmelden. */

  1079         if (dev != rtl_ecat_dev.dev)

  1080 	{

  1081           DPRINTK("About to register device named %s (%p)...\n", dev->name, dev);

  1082           i = register_netdev (dev);

  1083           if (i) goto err_out;

  1084 	}

  1085 

  1086 	/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

  1087 

  1088 	pci_set_drvdata (pdev, dev);

  1089 

  1090 	EC_DBG (KERN_INFO "%s: %s at 0x%lx, "

  1091 		"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "

  1092 		"IRQ %d\n",

  1093 		dev->name,

  1094 		board_info[ent->driver_data].name,

  1095 		dev->base_addr,

  1096 		dev->dev_addr[0], dev->dev_addr[1],

  1097 		dev->dev_addr[2], dev->dev_addr[3],

  1098 		dev->dev_addr[4], dev->dev_addr[5],

  1099 		dev->irq);

  1100 

  1101 	EC_DBG (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",

  1102 		dev->name, rtl_chip_info[tp->chipset].name);

  1103 

  1104 	/* Find the connected MII xcvrs.

  1105 	   Doing this in open() would allow detecting external xcvrs later, but

  1106 	   takes too much time. */

  1107 #ifdef CONFIG_8139TOO_8129

  1108 	if (tp->drv_flags & HAS_MII_XCVR) {

  1109 		int phy, phy_idx = 0;

  1110 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1111 			int mii_status = mdio_read(dev, phy, 1);

  1112 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1113 				u16 advertising = mdio_read(dev, phy, 4);

  1114 				tp->phys[phy_idx++] = phy;

  1115 				EC_DBG(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "

  1116 					   "advertising %4.4x.\n",

  1117 					   dev->name, phy, mii_status, advertising);

  1118 			}

  1119 		}

  1120 		if (phy_idx == 0) {

  1121 			EC_DBG(KERN_INFO "%s: No MII transceivers found!  Assuming SYM "

  1122 				   "transceiver.\n",

  1123 				   dev->name);

  1124 			tp->phys[0] = 32;

  1125 		}

  1126 	} else

  1127 #endif

  1128 		tp->phys[0] = 32;

  1129 	tp->mii.phy_id = tp->phys[0];

  1130 

  1131 	/* The lower four bits are the media type. */

  1132 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];

  1133 	if (option > 0) {

  1134 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;

  1135 		tp->default_port = option & 0xFF;