1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2006 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27  */

    28 

    29 /* e1000_hw.c

    30  * Shared functions for accessing and configuring the MAC

    31  */

    32 

    33 #include "e1000.h"

    34 

    35 static s32 e1000_check_downshift(struct e1000_hw *hw);

    36 static s32 e1000_check_polarity(struct e1000_hw *hw,

    37 				e1000_rev_polarity *polarity);

    38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39 static void e1000_clear_vfta(struct e1000_hw *hw);

    40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41 					      bool link_up);

    42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46 				  u16 *max_length);

    47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48 static s32 e1000_id_led_init(struct e1000_hw *hw);

    49 static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51 				  struct e1000_phy_info *phy_info);

    52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53 				  struct e1000_phy_info *phy_info);

    54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55 static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57 static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58 static void e1000_phy_init_script(struct e1000_hw *hw);

    59 static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70 				  u16 words, u16 *data);

    71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72 					u16 words, u16 *data);

    73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78 				  u16 phy_data);

    79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    80 				 u16 *phy_data);

    81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83 static void e1000_release_eeprom(struct e1000_hw *hw);

    84 static void e1000_standby_eeprom(struct e1000_hw *hw);

    85 static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87 static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89 				u16 *data);

    90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91 				 u16 *data);

    92 

    93 /* IGP cable length table */

    94 static const

    95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96 	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    97 	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98 	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99 	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100 	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101 	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102 	    100,

   103 	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104 	    110, 110,

   105 	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106 	    120, 120

   107 };

   108 

   109 static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110 

   111 /**

   112  * e1000_set_phy_type - Set the phy type member in the hw struct.

   113  * @hw: Struct containing variables accessed by shared code

   114  */

   115 static s32 e1000_set_phy_type(struct e1000_hw *hw)

   116 {

   117 	e_dbg("e1000_set_phy_type");

   118 

   119 	if (hw->mac_type == e1000_undefined)

   120 		return -E1000_ERR_PHY_TYPE;

   121 

   122 	switch (hw->phy_id) {

   123 	case M88E1000_E_PHY_ID:

   124 	case M88E1000_I_PHY_ID:

   125 	case M88E1011_I_PHY_ID:

   126 	case M88E1111_I_PHY_ID:

   127 	case M88E1118_E_PHY_ID:

   128 		hw->phy_type = e1000_phy_m88;

   129 		break;

   130 	case IGP01E1000_I_PHY_ID:

   131 		if (hw->mac_type == e1000_82541 ||

   132 		    hw->mac_type == e1000_82541_rev_2 ||

   133 		    hw->mac_type == e1000_82547 ||

   134 		    hw->mac_type == e1000_82547_rev_2)

   135 			hw->phy_type = e1000_phy_igp;

   136 		break;

   137 	case RTL8211B_PHY_ID:

   138 		hw->phy_type = e1000_phy_8211;

   139 		break;

   140 	case RTL8201N_PHY_ID:

   141 		hw->phy_type = e1000_phy_8201;

   142 		break;

   143 	default:

   144 		/* Should never have loaded on this device */

   145 		hw->phy_type = e1000_phy_undefined;

   146 		return -E1000_ERR_PHY_TYPE;

   147 	}

   148 

   149 	return E1000_SUCCESS;

   150 }

   151 

   152 /**

   153  * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   154  * @hw: Struct containing variables accessed by shared code

   155  */

   156 static void e1000_phy_init_script(struct e1000_hw *hw)

   157 {

   158 	u32 ret_val;

   159 	u16 phy_saved_data;

   160 

   161 	e_dbg("e1000_phy_init_script");

   162 

   163 	if (hw->phy_init_script) {

   164 		msleep(20);

   165 

   166 		/* Save off the current value of register 0x2F5B to be restored at

   167 		 * the end of this routine. */

   168 		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   169 

   170 		/* Disabled the PHY transmitter */

   171 		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   172 		msleep(20);

   173 

   174 		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   175 		msleep(5);

   176 

   177 		switch (hw->mac_type) {

   178 		case e1000_82541:

   179 		case e1000_82547:

   180 			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   181 			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   182 			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   183 			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   184 			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   185 			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   186 			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   187 			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   188 			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   189 			break;

   190 

   191 		case e1000_82541_rev_2:

   192 		case e1000_82547_rev_2:

   193 			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   194 			break;

   195 		default:

   196 			break;

   197 		}

   198 

   199 		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   200 		msleep(20);

   201 

   202 		/* Now enable the transmitter */

   203 		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   204 

   205 		if (hw->mac_type == e1000_82547) {

   206 			u16 fused, fine, coarse;

   207 

   208 			/* Move to analog registers page */

   209 			e1000_read_phy_reg(hw,

   210 					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   211 					   &fused);

   212 

   213 			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   214 				e1000_read_phy_reg(hw,

   215 						   IGP01E1000_ANALOG_FUSE_STATUS,

   216 						   &fused);

   217 

   218 				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   219 				coarse =

   220 				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   221 

   222 				if (coarse >

   223 				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   224 					coarse -=

   225 					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   226 					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   227 				} else if (coarse ==

   228 					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   229 					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   230 

   231 				fused =

   232 				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   233 				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   234 				    (coarse &

   235 				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   236 

   237 				e1000_write_phy_reg(hw,

   238 						    IGP01E1000_ANALOG_FUSE_CONTROL,

   239 						    fused);

   240 				e1000_write_phy_reg(hw,

   241 						    IGP01E1000_ANALOG_FUSE_BYPASS,

   242 						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   243 			}

   244 		}

   245 	}

   246 }

   247 

   248 /**

   249  * e1000_set_mac_type - Set the mac type member in the hw struct.

   250  * @hw: Struct containing variables accessed by shared code

   251  */

   252 s32 e1000_set_mac_type(struct e1000_hw *hw)

   253 {

   254 	e_dbg("e1000_set_mac_type");

   255 

   256 	switch (hw->device_id) {

   257 	case E1000_DEV_ID_82542:

   258 		switch (hw->revision_id) {

   259 		case E1000_82542_2_0_REV_ID:

   260 			hw->mac_type = e1000_82542_rev2_0;

   261 			break;

   262 		case E1000_82542_2_1_REV_ID:

   263 			hw->mac_type = e1000_82542_rev2_1;

   264 			break;

   265 		default:

   266 			/* Invalid 82542 revision ID */

   267 			return -E1000_ERR_MAC_TYPE;

   268 		}

   269 		break;

   270 	case E1000_DEV_ID_82543GC_FIBER:

   271 	case E1000_DEV_ID_82543GC_COPPER:

   272 		hw->mac_type = e1000_82543;

   273 		break;

   274 	case E1000_DEV_ID_82544EI_COPPER:

   275 	case E1000_DEV_ID_82544EI_FIBER:

   276 	case E1000_DEV_ID_82544GC_COPPER:

   277 	case E1000_DEV_ID_82544GC_LOM:

   278 		hw->mac_type = e1000_82544;

   279 		break;

   280 	case E1000_DEV_ID_82540EM:

   281 	case E1000_DEV_ID_82540EM_LOM:

   282 	case E1000_DEV_ID_82540EP:

   283 	case E1000_DEV_ID_82540EP_LOM:

   284 	case E1000_DEV_ID_82540EP_LP:

   285 		hw->mac_type = e1000_82540;

   286 		break;

   287 	case E1000_DEV_ID_82545EM_COPPER:

   288 	case E1000_DEV_ID_82545EM_FIBER:

   289 		hw->mac_type = e1000_82545;

   290 		break;

   291 	case E1000_DEV_ID_82545GM_COPPER:

   292 	case E1000_DEV_ID_82545GM_FIBER:

   293 	case E1000_DEV_ID_82545GM_SERDES:

   294 		hw->mac_type = e1000_82545_rev_3;

   295 		break;

   296 	case E1000_DEV_ID_82546EB_COPPER:

   297 	case E1000_DEV_ID_82546EB_FIBER:

   298 	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   299 		hw->mac_type = e1000_82546;

   300 		break;

   301 	case E1000_DEV_ID_82546GB_COPPER:

   302 	case E1000_DEV_ID_82546GB_FIBER:

   303 	case E1000_DEV_ID_82546GB_SERDES:

   304 	case E1000_DEV_ID_82546GB_PCIE:

   305 	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   306 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   307 		hw->mac_type = e1000_82546_rev_3;

   308 		break;

   309 	case E1000_DEV_ID_82541EI:

   310 	case E1000_DEV_ID_82541EI_MOBILE:

   311 	case E1000_DEV_ID_82541ER_LOM:

   312 		hw->mac_type = e1000_82541;

   313 		break;

   314 	case E1000_DEV_ID_82541ER:

   315 	case E1000_DEV_ID_82541GI:

   316 	case E1000_DEV_ID_82541GI_LF:

   317 	case E1000_DEV_ID_82541GI_MOBILE:

   318 		hw->mac_type = e1000_82541_rev_2;

   319 		break;

   320 	case E1000_DEV_ID_82547EI:

   321 	case E1000_DEV_ID_82547EI_MOBILE:

   322 		hw->mac_type = e1000_82547;

   323 		break;

   324 	case E1000_DEV_ID_82547GI:

   325 		hw->mac_type = e1000_82547_rev_2;

   326 		break;

   327 	case E1000_DEV_ID_INTEL_CE4100_GBE:

   328 		hw->mac_type = e1000_ce4100;

   329 		break;

   330 	default:

   331 		/* Should never have loaded on this device */

   332 		return -E1000_ERR_MAC_TYPE;

   333 	}

   334 

   335 	switch (hw->mac_type) {

   336 	case e1000_82541:

   337 	case e1000_82547:

   338 	case e1000_82541_rev_2:

   339 	case e1000_82547_rev_2:

   340 		hw->asf_firmware_present = true;

   341 		break;

   342 	default:

   343 		break;

   344 	}

   345 

   346 	/* The 82543 chip does not count tx_carrier_errors properly in

   347 	 * FD mode

   348 	 */

   349 	if (hw->mac_type == e1000_82543)

   350 		hw->bad_tx_carr_stats_fd = true;

   351 

   352 	if (hw->mac_type > e1000_82544)

   353 		hw->has_smbus = true;

   354 

   355 	return E1000_SUCCESS;

   356 }

   357 

   358 /**

   359  * e1000_set_media_type - Set media type and TBI compatibility.

   360  * @hw: Struct containing variables accessed by shared code

   361  */

   362 void e1000_set_media_type(struct e1000_hw *hw)

   363 {

   364 	u32 status;

   365 

   366 	e_dbg("e1000_set_media_type");

   367 

   368 	if (hw->mac_type != e1000_82543) {

   369 		/* tbi_compatibility is only valid on 82543 */

   370 		hw->tbi_compatibility_en = false;

   371 	}

   372 

   373 	switch (hw->device_id) {

   374 	case E1000_DEV_ID_82545GM_SERDES:

   375 	case E1000_DEV_ID_82546GB_SERDES:

   376 		hw->media_type = e1000_media_type_internal_serdes;

   377 		break;

   378 	default:

   379 		switch (hw->mac_type) {

   380 		case e1000_82542_rev2_0:

   381 		case e1000_82542_rev2_1:

   382 			hw->media_type = e1000_media_type_fiber;

   383 			break;

   384 		case e1000_ce4100:

   385 			hw->media_type = e1000_media_type_copper;

   386 			break;

   387 		default:

   388 			status = er32(STATUS);

   389 			if (status & E1000_STATUS_TBIMODE) {

   390 				hw->media_type = e1000_media_type_fiber;

   391 				/* tbi_compatibility not valid on fiber */

   392 				hw->tbi_compatibility_en = false;

   393 			} else {

   394 				hw->media_type = e1000_media_type_copper;

   395 			}

   396 			break;

   397 		}

   398 	}

   399 }

   400 

   401 /**

   402  * e1000_reset_hw - reset the hardware completely

   403  * @hw: Struct containing variables accessed by shared code

   404  *

   405  * Reset the transmit and receive units; mask and clear all interrupts.

   406  */

   407 s32 e1000_reset_hw(struct e1000_hw *hw)

   408 {

   409 	u32 ctrl;

   410 	u32 ctrl_ext;

   411 	u32 icr;

   412 	u32 manc;

   413 	u32 led_ctrl;

   414 	s32 ret_val;

   415 

   416 	e_dbg("e1000_reset_hw");

   417 

   418 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   419 	if (hw->mac_type == e1000_82542_rev2_0) {

   420 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   421 		e1000_pci_clear_mwi(hw);

   422 	}

   423 

   424 	/* Clear interrupt mask to stop board from generating interrupts */

   425 	e_dbg("Masking off all interrupts\n");

   426 	ew32(IMC, 0xffffffff);

   427 

   428 	/* Disable the Transmit and Receive units.  Then delay to allow

   429 	 * any pending transactions to complete before we hit the MAC with

   430 	 * the global reset.

   431 	 */

   432 	ew32(RCTL, 0);

   433 	ew32(TCTL, E1000_TCTL_PSP);

   434 	E1000_WRITE_FLUSH();

   435 

   436 	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   437 	hw->tbi_compatibility_on = false;

   438 

   439 	/* Delay to allow any outstanding PCI transactions to complete before

   440 	 * resetting the device

   441 	 */

   442 	msleep(10);

   443 

   444 	ctrl = er32(CTRL);

   445 

   446 	/* Must reset the PHY before resetting the MAC */

   447 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   448 		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   449 		E1000_WRITE_FLUSH();

   450 		msleep(5);

   451 	}

   452 

   453 	/* Issue a global reset to the MAC.  This will reset the chip's

   454 	 * transmit, receive, DMA, and link units.  It will not effect

   455 	 * the current PCI configuration.  The global reset bit is self-

   456 	 * clearing, and should clear within a microsecond.

   457 	 */

   458 	e_dbg("Issuing a global reset to MAC\n");

   459 

   460 	switch (hw->mac_type) {

   461 	case e1000_82544:

   462 	case e1000_82540:

   463 	case e1000_82545:

   464 	case e1000_82546:

   465 	case e1000_82541:

   466 	case e1000_82541_rev_2:

   467 		/* These controllers can't ack the 64-bit write when issuing the

   468 		 * reset, so use IO-mapping as a workaround to issue the reset */

   469 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   470 		break;

   471 	case e1000_82545_rev_3:

   472 	case e1000_82546_rev_3:

   473 		/* Reset is performed on a shadow of the control register */

   474 		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   475 		break;

   476 	case e1000_ce4100:

   477 	default:

   478 		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   479 		break;

   480 	}

   481 

   482 	/* After MAC reset, force reload of EEPROM to restore power-on settings to

   483 	 * device.  Later controllers reload the EEPROM automatically, so just wait

   484 	 * for reload to complete.

   485 	 */

   486 	switch (hw->mac_type) {

   487 	case e1000_82542_rev2_0:

   488 	case e1000_82542_rev2_1:

   489 	case e1000_82543:

   490 	case e1000_82544:

   491 		/* Wait for reset to complete */

   492 		udelay(10);

   493 		ctrl_ext = er32(CTRL_EXT);

   494 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   495 		ew32(CTRL_EXT, ctrl_ext);

   496 		E1000_WRITE_FLUSH();

   497 		/* Wait for EEPROM reload */

   498 		msleep(2);

   499 		break;

   500 	case e1000_82541:

   501 	case e1000_82541_rev_2:

   502 	case e1000_82547:

   503 	case e1000_82547_rev_2:

   504 		/* Wait for EEPROM reload */

   505 		msleep(20);

   506 		break;

   507 	default:

   508 		/* Auto read done will delay 5ms or poll based on mac type */

   509 		ret_val = e1000_get_auto_rd_done(hw);

   510 		if (ret_val)

   511 			return ret_val;

   512 		break;

   513 	}

   514 

   515 	/* Disable HW ARPs on ASF enabled adapters */

   516 	if (hw->mac_type >= e1000_82540) {

   517 		manc = er32(MANC);

   518 		manc &= ~(E1000_MANC_ARP_EN);

   519 		ew32(MANC, manc);

   520 	}

   521 

   522 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   523 		e1000_phy_init_script(hw);

   524 

   525 		/* Configure activity LED after PHY reset */

   526 		led_ctrl = er32(LEDCTL);

   527 		led_ctrl &= IGP_ACTIVITY_LED_MASK;

   528 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   529 		ew32(LEDCTL, led_ctrl);

   530 	}

   531 

   532 	/* Clear interrupt mask to stop board from generating interrupts */

   533 	e_dbg("Masking off all interrupts\n");

   534 	ew32(IMC, 0xffffffff);

   535 

   536 	/* Clear any pending interrupt events. */

   537 	icr = er32(ICR);

   538 

   539 	/* If MWI was previously enabled, reenable it. */

   540 	if (hw->mac_type == e1000_82542_rev2_0) {

   541 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   542 			e1000_pci_set_mwi(hw);

   543 	}

   544 

   545 	return E1000_SUCCESS;

   546 }

   547 

   548 /**

   549  * e1000_init_hw - Performs basic configuration of the adapter.

   550  * @hw: Struct containing variables accessed by shared code

   551  *

   552  * Assumes that the controller has previously been reset and is in a

   553  * post-reset uninitialized state. Initializes the receive address registers,

   554  * multicast table, and VLAN filter table. Calls routines to setup link

   555  * configuration and flow control settings. Clears all on-chip counters. Leaves

   556  * the transmit and receive units disabled and uninitialized.

   557  */

   558 s32 e1000_init_hw(struct e1000_hw *hw)

   559 {

   560 	u32 ctrl;

   561 	u32 i;

   562 	s32 ret_val;

   563 	u32 mta_size;

   564 	u32 ctrl_ext;

   565 

   566 	e_dbg("e1000_init_hw");

   567 

   568 	/* Initialize Identification LED */

   569 	ret_val = e1000_id_led_init(hw);

   570 	if (ret_val) {

   571 		e_dbg("Error Initializing Identification LED\n");

   572 		return ret_val;

   573 	}

   574 

   575 	/* Set the media type and TBI compatibility */

   576 	e1000_set_media_type(hw);

   577 

   578 	/* Disabling VLAN filtering. */

   579 	e_dbg("Initializing the IEEE VLAN\n");

   580 	if (hw->mac_type < e1000_82545_rev_3)

   581 		ew32(VET, 0);

   582 	e1000_clear_vfta(hw);

   583 

   584 	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */

   585 	if (hw->mac_type == e1000_82542_rev2_0) {

   586 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   587 		e1000_pci_clear_mwi(hw);

   588 		ew32(RCTL, E1000_RCTL_RST);

   589 		E1000_WRITE_FLUSH();

   590 		msleep(5);

   591 	}

   592 

   593 	/* Setup the receive address. This involves initializing all of the Receive

   594 	 * Address Registers (RARs 0 - 15).

   595 	 */

   596 	e1000_init_rx_addrs(hw);

   597 

   598 	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */

   599 	if (hw->mac_type == e1000_82542_rev2_0) {

   600 		ew32(RCTL, 0);

   601 		E1000_WRITE_FLUSH();

   602 		msleep(1);

   603 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   604 			e1000_pci_set_mwi(hw);

   605 	}

   606 

   607 	/* Zero out the Multicast HASH table */

   608 	e_dbg("Zeroing the MTA\n");

   609 	mta_size = E1000_MC_TBL_SIZE;

   610 	for (i = 0; i < mta_size; i++) {

   611 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);

   612 		/* use write flush to prevent Memory Write Block (MWB) from

   613 		 * occurring when accessing our register space */

   614 		E1000_WRITE_FLUSH();

   615 	}

   616 

   617 	/* Set the PCI priority bit correctly in the CTRL register.  This

   618 	 * determines if the adapter gives priority to receives, or if it

   619 	 * gives equal priority to transmits and receives.  Valid only on

   620 	 * 82542 and 82543 silicon.

   621 	 */

   622 	if (hw->dma_fairness && hw->mac_type <= e1000_82543) {

   623 		ctrl = er32(CTRL);

   624 		ew32(CTRL, ctrl | E1000_CTRL_PRIOR);

   625 	}

   626 

   627 	switch (hw->mac_type) {

   628 	case e1000_82545_rev_3:

   629 	case e1000_82546_rev_3:

   630 		break;

   631 	default:

   632 		/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */

   633 		if (hw->bus_type == e1000_bus_type_pcix

   634 		    && e1000_pcix_get_mmrbc(hw) > 2048)

   635 			e1000_pcix_set_mmrbc(hw, 2048);

   636 		break;

   637 	}

   638 

   639 	/* Call a subroutine to configure the link and setup flow control. */

   640 	ret_val = e1000_setup_link(hw);

   641 

   642 	/* Set the transmit descriptor write-back policy */

   643 	if (hw->mac_type > e1000_82544) {

   644 		ctrl = er32(TXDCTL);

   645 		ctrl =

   646 		    (ctrl & ~E1000_TXDCTL_WTHRESH) |

   647 		    E1000_TXDCTL_FULL_TX_DESC_WB;

   648 		ew32(TXDCTL, ctrl);

   649 	}

   650 

   651 	/* Clear all of the statistics registers (clear on read).  It is

   652 	 * important that we do this after we have tried to establish link

   653 	 * because the symbol error count will increment wildly if there

   654 	 * is no link.

   655 	 */

   656 	e1000_clear_hw_cntrs(hw);

   657 

   658 	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||

   659 	    hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {

   660 		ctrl_ext = er32(CTRL_EXT);

   661 		/* Relaxed ordering must be disabled to avoid a parity

   662 		 * error crash in a PCI slot. */

   663 		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;

   664 		ew32(CTRL_EXT, ctrl_ext);

   665 	}

   666 

   667 	return ret_val;

   668 }

   669 

   670 /**

   671  * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.

   672  * @hw: Struct containing variables accessed by shared code.

   673  */

   674 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)

   675 {

   676 	u16 eeprom_data;

   677 	s32 ret_val;

   678 

   679 	e_dbg("e1000_adjust_serdes_amplitude");

   680 

   681 	if (hw->media_type != e1000_media_type_internal_serdes)

   682 		return E1000_SUCCESS;

   683 

   684 	switch (hw->mac_type) {

   685 	case e1000_82545_rev_3:

   686 	case e1000_82546_rev_3:

   687 		break;

   688 	default:

   689 		return E1000_SUCCESS;

   690 	}

   691 

   692 	ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,

   693 	                            &eeprom_data);

   694 	if (ret_val) {

   695 		return ret_val;

   696 	}

   697 

   698 	if (eeprom_data != EEPROM_RESERVED_WORD) {

   699 		/* Adjust SERDES output amplitude only. */

   700 		eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;

   701 		ret_val =

   702 		    e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);

   703 		if (ret_val)

   704 			return ret_val;

   705 	}

   706 

   707 	return E1000_SUCCESS;

   708 }

   709 

   710 /**

   711  * e1000_setup_link - Configures flow control and link settings.

   712  * @hw: Struct containing variables accessed by shared code

   713  *

   714  * Determines which flow control settings to use. Calls the appropriate media-

   715  * specific link configuration function. Configures the flow control settings.

   716  * Assuming the adapter has a valid link partner, a valid link should be

   717  * established. Assumes the hardware has previously been reset and the

   718  * transmitter and receiver are not enabled.

   719  */

   720 s32 e1000_setup_link(struct e1000_hw *hw)

   721 {

   722 	u32 ctrl_ext;

   723 	s32 ret_val;

   724 	u16 eeprom_data;

   725 

   726 	e_dbg("e1000_setup_link");

   727 

   728 	/* Read and store word 0x0F of the EEPROM. This word contains bits

   729 	 * that determine the hardware's default PAUSE (flow control) mode,

   730 	 * a bit that determines whether the HW defaults to enabling or

   731 	 * disabling auto-negotiation, and the direction of the

   732 	 * SW defined pins. If there is no SW over-ride of the flow

   733 	 * control setting, then the variable hw->fc will

   734 	 * be initialized based on a value in the EEPROM.

   735 	 */

   736 	if (hw->fc == E1000_FC_DEFAULT) {

   737 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   738 					    1, &eeprom_data);

   739 		if (ret_val) {

   740 			e_dbg("EEPROM Read Error\n");

   741 			return -E1000_ERR_EEPROM;

   742 		}

   743 		if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)

   744 			hw->fc = E1000_FC_NONE;

   745 		else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==

   746 			 EEPROM_WORD0F_ASM_DIR)

   747 			hw->fc = E1000_FC_TX_PAUSE;

   748 		else

   749 			hw->fc = E1000_FC_FULL;

   750 	}

   751 

   752 	/* We want to save off the original Flow Control configuration just

   753 	 * in case we get disconnected and then reconnected into a different

   754 	 * hub or switch with different Flow Control capabilities.

   755 	 */

   756 	if (hw->mac_type == e1000_82542_rev2_0)

   757 		hw->fc &= (~E1000_FC_TX_PAUSE);

   758 

   759 	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))

   760 		hw->fc &= (~E1000_FC_RX_PAUSE);

   761 

   762 	hw->original_fc = hw->fc;

   763 

   764 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);

   765 

   766 	/* Take the 4 bits from EEPROM word 0x0F that determine the initial

   767 	 * polarity value for the SW controlled pins, and setup the

   768 	 * Extended Device Control reg with that info.

   769 	 * This is needed because one of the SW controlled pins is used for

   770 	 * signal detection.  So this should be done before e1000_setup_pcs_link()

   771 	 * or e1000_phy_setup() is called.

   772 	 */

   773 	if (hw->mac_type == e1000_82543) {

   774 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   775 					    1, &eeprom_data);

   776 		if (ret_val) {

   777 			e_dbg("EEPROM Read Error\n");

   778 			return -E1000_ERR_EEPROM;

   779 		}

   780 		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<

   781 			    SWDPIO__EXT_SHIFT);

   782 		ew32(CTRL_EXT, ctrl_ext);

   783 	}

   784 

   785 	/* Call the necessary subroutine to configure the link. */

   786 	ret_val = (hw->media_type == e1000_media_type_copper) ?

   787 	    e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);

   788 

   789 	/* Initialize the flow control address, type, and PAUSE timer

   790 	 * registers to their default values.  This is done even if flow

   791 	 * control is disabled, because it does not hurt anything to

   792 	 * initialize these registers.

   793 	 */

   794 	e_dbg("Initializing the Flow Control address, type and timer regs\n");

   795 

   796 	ew32(FCT, FLOW_CONTROL_TYPE);

   797 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);

   798 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);

   799 

   800 	ew32(FCTTV, hw->fc_pause_time);

   801 

   802 	/* Set the flow control receive threshold registers.  Normally,

   803 	 * these registers will be set to a default threshold that may be

   804 	 * adjusted later by the driver's runtime code.  However, if the

   805 	 * ability to transmit pause frames in not enabled, then these

   806 	 * registers will be set to 0.

   807 	 */

   808 	if (!(hw->fc & E1000_FC_TX_PAUSE)) {

   809 		ew32(FCRTL, 0);

   810 		ew32(FCRTH, 0);

   811 	} else {

   812 		/* We need to set up the Receive Threshold high and low water marks

   813 		 * as well as (optionally) enabling the transmission of XON frames.

   814 		 */

   815 		if (hw->fc_send_xon) {

   816 			ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));

   817 			ew32(FCRTH, hw->fc_high_water);

   818 		} else {

   819 			ew32(FCRTL, hw->fc_low_water);

   820 			ew32(FCRTH, hw->fc_high_water);

   821 		}

   822 	}

   823 	return ret_val;

   824 }

   825 

   826 /**

   827  * e1000_setup_fiber_serdes_link - prepare fiber or serdes link

   828  * @hw: Struct containing variables accessed by shared code

   829  *

   830  * Manipulates Physical Coding Sublayer functions in order to configure

   831  * link. Assumes the hardware has been previously reset and the transmitter

   832  * and receiver are not enabled.

   833  */

   834 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)

   835 {

   836 	u32 ctrl;

   837 	u32 status;

   838 	u32 txcw = 0;

   839 	u32 i;

   840 	u32 signal = 0;

   841 	s32 ret_val;

   842 

   843 	e_dbg("e1000_setup_fiber_serdes_link");

   844 

   845 	/* On adapters with a MAC newer than 82544, SWDP 1 will be

   846 	 * set when the optics detect a signal. On older adapters, it will be

   847 	 * cleared when there is a signal.  This applies to fiber media only.

   848 	 * If we're on serdes media, adjust the output amplitude to value

   849 	 * set in the EEPROM.

   850 	 */

   851 	ctrl = er32(CTRL);

   852 	if (hw->media_type == e1000_media_type_fiber)

   853 		signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;

   854 

   855 	ret_val = e1000_adjust_serdes_amplitude(hw);

   856 	if (ret_val)

   857 		return ret_val;

   858 

   859 	/* Take the link out of reset */

   860 	ctrl &= ~(E1000_CTRL_LRST);

   861 

   862 	/* Adjust VCO speed to improve BER performance */

   863 	ret_val = e1000_set_vco_speed(hw);

   864 	if (ret_val)

   865 		return ret_val;

   866 

   867 	e1000_config_collision_dist(hw);

   868 

   869 	/* Check for a software override of the flow control settings, and setup

   870 	 * the device accordingly.  If auto-negotiation is enabled, then software

   871 	 * will have to set the "PAUSE" bits to the correct value in the Tranmsit

   872 	 * Config Word Register (TXCW) and re-start auto-negotiation.  However, if

   873 	 * auto-negotiation is disabled, then software will have to manually

   874 	 * configure the two flow control enable bits in the CTRL register.

   875 	 *

   876 	 * The possible values of the "fc" parameter are:

   877 	 *      0:  Flow control is completely disabled

   878 	 *      1:  Rx flow control is enabled (we can receive pause frames, but

   879 	 *          not send pause frames).

   880 	 *      2:  Tx flow control is enabled (we can send pause frames but we do

   881 	 *          not support receiving pause frames).

   882 	 *      3:  Both Rx and TX flow control (symmetric) are enabled.

   883 	 */

   884 	switch (hw->fc) {

   885 	case E1000_FC_NONE:

   886 		/* Flow control is completely disabled by a software over-ride. */

   887 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);

   888 		break;

   889 	case E1000_FC_RX_PAUSE:

   890 		/* RX Flow control is enabled and TX Flow control is disabled by a

   891 		 * software over-ride. Since there really isn't a way to advertise

   892 		 * that we are capable of RX Pause ONLY, we will advertise that we

   893 		 * support both symmetric and asymmetric RX PAUSE. Later, we will

   894 		 *  disable the adapter's ability to send PAUSE frames.

   895 		 */

   896 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   897 		break;

   898 	case E1000_FC_TX_PAUSE:

   899 		/* TX Flow control is enabled, and RX Flow control is disabled, by a

   900 		 * software over-ride.

   901 		 */

   902 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);

   903 		break;

   904 	case E1000_FC_FULL:

   905 		/* Flow control (both RX and TX) is enabled by a software over-ride. */

   906 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   907 		break;

   908 	default:

   909 		e_dbg("Flow control param set incorrectly\n");

   910 		return -E1000_ERR_CONFIG;

   911 		break;

   912 	}

   913 

   914 	/* Since auto-negotiation is enabled, take the link out of reset (the link

   915 	 * will be in reset, because we previously reset the chip). This will

   916 	 * restart auto-negotiation.  If auto-negotiation is successful then the

   917 	 * link-up status bit will be set and the flow control enable bits (RFCE

   918 	 * and TFCE) will be set according to their negotiated value.

   919 	 */

   920 	e_dbg("Auto-negotiation enabled\n");

   921 

   922 	ew32(TXCW, txcw);

   923 	ew32(CTRL, ctrl);

   924 	E1000_WRITE_FLUSH();

   925 

   926 	hw->txcw = txcw;

   927 	msleep(1);

   928 

   929 	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"

   930 	 * indication in the Device Status Register.  Time-out if a link isn't

   931 	 * seen in 500 milliseconds seconds (Auto-negotiation should complete in

   932 	 * less than 500 milliseconds even if the other end is doing it in SW).

   933 	 * For internal serdes, we just assume a signal is present, then poll.

   934 	 */

   935 	if (hw->media_type == e1000_media_type_internal_serdes ||

   936 	    (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {

   937 		e_dbg("Looking for Link\n");

   938 		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {

   939 			msleep(10);

   940 			status = er32(STATUS);

   941 			if (status & E1000_STATUS_LU)

   942 				break;

   943 		}

   944 		if (i == (LINK_UP_TIMEOUT / 10)) {

   945 			e_dbg("Never got a valid link from auto-neg!!!\n");

   946 			hw->autoneg_failed = 1;

   947 			/* AutoNeg failed to achieve a link, so we'll call

   948 			 * e1000_check_for_link. This routine will force the link up if

   949 			 * we detect a signal. This will allow us to communicate with

   950 			 * non-autonegotiating link partners.

   951 			 */

   952 			ret_val = e1000_check_for_link(hw);

   953 			if (ret_val) {

   954 				e_dbg("Error while checking for link\n");

   955 				return ret_val;

   956 			}

   957 			hw->autoneg_failed = 0;

   958 		} else {

   959 			hw->autoneg_failed = 0;

   960 			e_dbg("Valid Link Found\n");

   961 		}

   962 	} else {

   963 		e_dbg("No Signal Detected\n");

   964 	}

   965 	return E1000_SUCCESS;

   966 }

   967 

   968 /**

   969  * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.

   970  * @hw: Struct containing variables accessed by shared code

   971  *

   972  * Commits changes to PHY configuration by calling e1000_phy_reset().

   973  */

   974 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)

   975 {

   976 	s32 ret_val;

   977 

   978 	/* SW reset the PHY so all changes take effect */

   979 	ret_val = e1000_phy_reset(hw);

   980 	if (ret_val) {

   981 		e_dbg("Error Resetting the PHY\n");

   982 		return ret_val;

   983 	}

   984 

   985 	return E1000_SUCCESS;

   986 }

   987 

   988 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)

   989 {

   990 	s32 ret_val;

   991 	u32 ctrl_aux;

   992 

   993 	switch (hw->phy_type) {

   994 	case e1000_phy_8211:

   995 		ret_val = e1000_copper_link_rtl_setup(hw);

   996 		if (ret_val) {

   997 			e_dbg("e1000_copper_link_rtl_setup failed!\n");

   998 			return ret_val;

   999 		}

  1000 		break;

  1001 	case e1000_phy_8201:

  1002 		/* Set RMII mode */

  1003 		ctrl_aux = er32(CTL_AUX);

  1004 		ctrl_aux |= E1000_CTL_AUX_RMII;

  1005 		ew32(CTL_AUX, ctrl_aux);

  1006 		E1000_WRITE_FLUSH();

  1007 

  1008 		/* Disable the J/K bits required for receive */

  1009 		ctrl_aux = er32(CTL_AUX);

  1010 		ctrl_aux |= 0x4;

  1011 		ctrl_aux &= ~0x2;

  1012 		ew32(CTL_AUX, ctrl_aux);

  1013 		E1000_WRITE_FLUSH();

  1014 		ret_val = e1000_copper_link_rtl_setup(hw);

  1015 

  1016 		if (ret_val) {

  1017 			e_dbg("e1000_copper_link_rtl_setup failed!\n");

  1018 			return ret_val;

  1019 		}

  1020 		break;

  1021 	default:

  1022 		e_dbg("Error Resetting the PHY\n");

  1023 		return E1000_ERR_PHY_TYPE;

  1024 	}

  1025 

  1026 	return E1000_SUCCESS;

  1027 }

  1028 

  1029 /**

  1030  * e1000_copper_link_preconfig - early configuration for copper

  1031  * @hw: Struct containing variables accessed by shared code

  1032  *

  1033  * Make sure we have a valid PHY and change PHY mode before link setup.

  1034  */

  1035 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)

  1036 {

  1037 	u32 ctrl;

  1038 	s32 ret_val;

  1039 	u16 phy_data;

  1040 

  1041 	e_dbg("e1000_copper_link_preconfig");

  1042 

  1043 	ctrl = er32(CTRL);

  1044 	/* With 82543, we need to force speed and duplex on the MAC equal to what

  1045 	 * the PHY speed and duplex configuration is. In addition, we need to

  1046 	 * perform a hardware reset on the PHY to take it out of reset.

  1047 	 */

  1048 	if (hw->mac_type > e1000_82543) {

  1049 		ctrl |= E1000_CTRL_SLU;

  1050 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

  1051 		ew32(CTRL, ctrl);

  1052 	} else {

  1053 		ctrl |=

  1054 		    (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);

  1055 		ew32(CTRL, ctrl);

  1056 		ret_val = e1000_phy_hw_reset(hw);

  1057 		if (ret_val)

  1058 			return ret_val;

  1059 	}

  1060 

  1061 	/* Make sure we have a valid PHY */

  1062 	ret_val = e1000_detect_gig_phy(hw);

  1063 	if (ret_val) {

  1064 		e_dbg("Error, did not detect valid phy.\n");

  1065 		return ret_val;

  1066 	}

  1067 	e_dbg("Phy ID = %x\n", hw->phy_id);

  1068 

  1069 	/* Set PHY to class A mode (if necessary) */

  1070 	ret_val = e1000_set_phy_mode(hw);

  1071 	if (ret_val)

  1072 		return ret_val;

  1073 

  1074 	if ((hw->mac_type == e1000_82545_rev_3) ||

  1075 	    (hw->mac_type == e1000_82546_rev_3)) {

  1076 		ret_val =

  1077 		    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

  1078 		phy_data |= 0x00000008;

  1079 		ret_val =

  1080 		    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

  1081 	}

  1082 

  1083 	if (hw->mac_type <= e1000_82543 ||

  1084 	    hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||

  1085 	    hw->mac_type == e1000_82541_rev_2

  1086 	    || hw->mac_type == e1000_82547_rev_2)

  1087 		hw->phy_reset_disable = false;

  1088 

  1089 	return E1000_SUCCESS;

  1090 }

  1091 

  1092 /**

  1093  * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.

  1094  * @hw: Struct containing variables accessed by shared code

  1095  */

  1096 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)

  1097 {

  1098 	u32 led_ctrl;

  1099 	s32 ret_val;

  1100 	u16 phy_data;

  1101 

  1102 	e_dbg("e1000_copper_link_igp_setup");

  1103 

  1104 	if (hw->phy_reset_disable)

  1105 		return E1000_SUCCESS;

  1106 

  1107 	ret_val = e1000_phy_reset(hw);

  1108 	if (ret_val) {

  1109 		e_dbg("Error Resetting the PHY\n");

  1110 		return ret_val;

  1111 	}

  1112 

  1113 	/* Wait 15ms for MAC to configure PHY from eeprom settings */

  1114 	msleep(15);

  1115 	/* Configure activity LED after PHY reset */

  1116 	led_ctrl = er32(LEDCTL);

  1117 	led_ctrl &= IGP_ACTIVITY_LED_MASK;

  1118 	led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

  1119 	ew32(LEDCTL, led_ctrl);

  1120 

  1121 	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */

  1122 	if (hw->phy_type == e1000_phy_igp) {

  1123 		/* disable lplu d3 during driver init */

  1124 		ret_val = e1000_set_d3_lplu_state(hw, false);

  1125 		if (ret_val) {

  1126 			e_dbg("Error Disabling LPLU D3\n");

  1127 			return ret_val;

  1128 		}

  1129 	}

  1130 

  1131 	/* Configure mdi-mdix settings */

  1132 	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);

  1133 	if (ret_val)

  1134 		return ret_val;

  1135