1923 assert (ioaddr != NULL); |
1923 assert (ioaddr != NULL); |
1924 |
1924 |
1925 dirty_tx = tp->dirty_tx; |
1925 dirty_tx = tp->dirty_tx; |
1926 tx_left = tp->cur_tx - dirty_tx; |
1926 tx_left = tp->cur_tx - dirty_tx; |
1927 |
1927 |
1928 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ |
|
1929 |
|
1930 #if 0 |
|
1931 if (EtherCAT_dev_is_ec(rtl_ec_dev, dev)) |
|
1932 { |
|
1933 rtl_ec_dev.tx_intr_cnt++; |
|
1934 rdtscl(rtl_ec_dev.tx_time); // Get CPU cycles |
|
1935 } |
|
1936 #endif |
|
1937 |
|
1938 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/ |
|
1939 |
|
1940 while (tx_left > 0) { |
1928 while (tx_left > 0) { |
1941 int entry = dirty_tx % NUM_TX_DESC; |
1929 int entry = dirty_tx % NUM_TX_DESC; |
1942 int txstatus; |
1930 int txstatus; |
1943 |
1931 |
1944 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32))); |
1932 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32))); |
1965 tp->stats.tx_window_errors++; |
1953 tp->stats.tx_window_errors++; |
1966 |
1954 |
1967 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ |
1955 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ |
1968 |
1956 |
1969 if (EtherCAT_dev_is_ec(rtl_ec_dev, dev)) |
1957 if (EtherCAT_dev_is_ec(rtl_ec_dev, dev)) |
1970 { |
1958 EtherCAT_dev_state(rtl_ec_dev, EC_DEVICE_STATE_ERROR); |
1971 EtherCAT_dev_state(rtl_ec_dev, EC_DEVICE_STATE_ERROR); |
|
1972 } |
|
1973 |
1959 |
1974 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/ |
1960 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/ |
1975 |
1961 |
1976 } else { |
1962 } else { |
1977 if (txstatus & TxUnderrun) { |
1963 if (txstatus & TxUnderrun) { |
2153 |
2139 |
2154 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x," |
2140 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x," |
2155 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx, |
2141 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx, |
2156 RTL_R16 (RxBufAddr), |
2142 RTL_R16 (RxBufAddr), |
2157 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd)); |
2143 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd)); |
2158 |
|
2159 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ |
|
2160 #if 0 |
|
2161 if (EtherCAT_dev_is_ec(rtl_ec_dev, dev)) |
|
2162 { |
|
2163 rtl_ec_dev.rx_intr_cnt++; |
|
2164 rdtscl(rtl_ec_dev.rx_time); // Get CPU cycles |
|
2165 } |
|
2166 #endif |
|
2167 |
|
2168 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/ |
|
2169 |
2144 |
2170 while ((EtherCAT_dev_is_ec(rtl_ec_dev, dev) || netif_running(dev)) |
2145 while ((EtherCAT_dev_is_ec(rtl_ec_dev, dev) || netif_running(dev)) |
2171 && received < budget |
2146 && received < budget |
2172 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) { |
2147 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) { |
2173 u32 ring_offset = cur_rx % RX_BUF_LEN; |
2148 u32 ring_offset = cur_rx % RX_BUF_LEN; |