1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it

    10  *  and/or modify it under the terms of the GNU General Public License

    11  *  as published by the Free Software Foundation; either version 2 of the

    12  *  License, or (at your option) any later version.

    13  *

    14  *  The IgH EtherCAT Master is distributed in the hope that it will be

    15  *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  *  GNU General Public License for more details.

    18  *

    19  *  You should have received a copy of the GNU General Public License

    20  *  along with the IgH EtherCAT Master; if not, write to the Free Software

    21  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    22  *

    23  *  The right to use EtherCAT Technology is granted and comes free of

    24  *  charge under condition of compatibility of product made by

    25  *  Licensee. People intending to distribute/sell products based on the

    26  *  code, have to sign an agreement to guarantee that products using

    27  *  software based on IgH EtherCAT master stay compatible with the actual

    28  *  EtherCAT specification (which are released themselves as an open

    29  *  standard) as the (only) precondition to have the right to use EtherCAT

    30  *  Technology, IP and trade marks.

    31  *

    32  *****************************************************************************/

    33 

    34 /**

    35    \file

    36    EtherCAT driver for RTL8139-compatible NICs.

    37 */

    38 

    39 /*****************************************************************************/

    40 

    41 /*

    42   Former documentation:

    43 

    44 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    45 

    46 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    47 	Copyright 2000-2002 Jeff Garzik

    48 

    49 	Much code comes from Donald Becker's rtl8139.c driver,

    50 	versions 1.13 and older.  This driver was originally based

    51 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    52 

    53 	-----<snip>-----

    54 

    55         	Written 1997-2001 by Donald Becker.

    56 		This software may be used and distributed according to the

    57 		terms of the GNU General Public License (GPL), incorporated

    58 		herein by reference.  Drivers based on or derived from this

    59 		code fall under the GPL and must retain the authorship,

    60 		copyright and license notice.  This file is not a complete

    61 		program and may only be used when the entire operating

    62 		system is licensed under the GPL.

    63 

    64 		This driver is for boards based on the RTL8129 and RTL8139

    65 		PCI ethernet chips.

    66 

    67 		The author may be reached as becker@scyld.com, or C/O Scyld

    68 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    69 		MD 21403

    70 

    71 		Support and updates available at

    72 		http://www.scyld.com/network/rtl8139.html

    73 

    74 		Twister-tuning table provided by Kinston

    75 		<shangh@realtek.com.tw>.

    76 

    77 	-----<snip>-----

    78 

    79 	This software may be used and distributed according to the terms

    80 	of the GNU General Public License, incorporated herein by reference.

    81 

    82 	Contributors:

    83 

    84 		Donald Becker - he wrote the original driver, kudos to him!

    85 		(but please don't e-mail him for support, this isn't his driver)

    86 

    87 		Tigran Aivazian - bug fixes, skbuff free cleanup

    88 

    89 		Martin Mares - suggestions for PCI cleanup

    90 

    91 		David S. Miller - PCI DMA and softnet updates

    92 

    93 		Ernst Gill - fixes ported from BSD driver

    94 

    95 		Daniel Kobras - identified specific locations of

    96 			posted MMIO write bugginess

    97 

    98 		Gerard Sharp - bug fix, testing and feedback

    99 

   100 		David Ford - Rx ring wrap fix

   101 

   102 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

   103 		to find and fix a crucial bug on older chipsets.

   104 

   105 		Donald Becker/Chris Butterworth/Marcus Westergren -

   106 		Noticed various Rx packet size-related buglets.

   107 

   108 		Santiago Garcia Mantinan - testing and feedback

   109 

   110 		Jens David - 2.2.x kernel backports

   111 

   112 		Martin Dennett - incredibly helpful insight on undocumented

   113 		features of the 8139 chips

   114 

   115 		Jean-Jacques Michel - bug fix

   116 

   117 		Tobias Ringström - Rx interrupt status checking suggestion

   118 

   119 		Andrew Morton - Clear blocked signals, avoid

   120 		buffer overrun setting current->comm.

   121 

   122 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   123 

   124 		Robert Kuebel - Save kernel thread from dying on any signal.

   125 

   126 	Submitting bug reports:

   127 

   128 		"rtl8139-diag -mmmaaavvveefN" output

   129 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   130 

   131 */

   132 

   133 #define DRV_NAME	"ec_8139too"

   134 #define DRV_VERSION	"0.9.27"

   135 

   136 

   137 #include <linux/config.h>

   138 #include <linux/module.h>

   139 #include <linux/kernel.h>

   140 #include <linux/compiler.h>

   141 #include <linux/pci.h>

   142 #include <linux/init.h>

   143 #include <linux/ioport.h>

   144 #include <linux/netdevice.h>

   145 #include <linux/etherdevice.h>

   146 #include <linux/rtnetlink.h>

   147 #include <linux/delay.h>

   148 #include <linux/ethtool.h>

   149 #include <linux/mii.h>

   150 #include <linux/completion.h>

   151 #include <linux/crc32.h>

   152 #include <asm/io.h>

   153 #include <asm/uaccess.h>

   154 #include <asm/irq.h>

   155 

   156 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   157 

   158 #include "../globals.h"

   159 #include "ecdev.h"

   160 

   161 #define RTL8139_DRIVER_NAME DRV_NAME \

   162                             " EtherCAT-capable Fast Ethernet driver " \

   163                             DRV_VERSION ", master " EC_MASTER_VERSION

   164 

   165 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   166 

   167 #define PFX DRV_NAME ": "

   168 

   169 /* Default Message level */

   170 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   171                                  NETIF_MSG_PROBE  | \

   172                                  NETIF_MSG_LINK)

   173 

   174 

   175 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   176 #ifdef CONFIG_8139TOO_PIO

   177 #define USE_IO_OPS 1

   178 #endif

   179 

   180 /* define to 1, 2 or 3 to enable copious debugging info */

   181 #define RTL8139_DEBUG 0

   182 

   183 /* define to 1 to disable lightweight runtime debugging checks */

   184 #undef RTL8139_NDEBUG

   185 

   186 

   187 #if RTL8139_DEBUG

   188 /* note: prints function name for you */

   189 #  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   190 #else

   191 #  define DPRINTK(fmt, args...)

   192 #endif

   193 

   194 #ifdef RTL8139_NDEBUG

   195 #  define assert(expr) do {} while (0)

   196 #else

   197 #  define assert(expr) \

   198         if(unlikely(!(expr))) {				        \

   199         printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   200         #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   201         }

   202 #endif

   203 

   204 

   205 /* A few user-configurable values. */

   206 /* media options */

   207 #define MAX_UNITS 8

   208 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   209 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   210 

   211 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   212    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   213 static int multicast_filter_limit = 32;

   214 

   215 /* bitmapped message enable number */

   216 static int debug = -1;

   217 

   218 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   219 

   220 static int ec_device_index = -1;

   221 static int ec_device_master_index = 0;

   222 static ec_device_t *rtl_ec_dev;

   223 struct net_device *rtl_ec_net_dev = NULL;

   224 

   225 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   226 

   227 /*

   228  * Receive ring size 

   229  * Warning: 64K ring has hardware issues and may lock up.

   230  */

   231 #if defined(CONFIG_SH_DREAMCAST)

   232 #define RX_BUF_IDX	1	/* 16K ring */

   233 #else

   234 #define RX_BUF_IDX	2	/* 32K ring */

   235 #endif

   236 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   237 #define RX_BUF_PAD	16

   238 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   239 

   240 #if RX_BUF_LEN == 65536

   241 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   242 #else

   243 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   244 #endif

   245 

   246 /* Number of Tx descriptor registers. */

   247 #define NUM_TX_DESC	4

   248 

   249 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   250 #define MAX_ETH_FRAME_SIZE	1536

   251 

   252 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   253 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   254 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   255 

   256 /* PCI Tuning Parameters

   257    Threshold is bytes transferred to chip before transmission starts. */

   258 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   259 

   260 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   261 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   262 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   263 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   264 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   265 

   266 /* Operational parameters that usually are not changed. */

   267 /* Time in jiffies before concluding the transmitter is hung. */

   268 #define TX_TIMEOUT  (6*HZ)

   269 

   270 

   271 enum {

   272 	HAS_MII_XCVR = 0x010000,

   273 	HAS_CHIP_XCVR = 0x020000,

   274 	HAS_LNK_CHNG = 0x040000,

   275 };

   276 

   277 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   278 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   279 #define RTL_MIN_IO_SIZE 0x80

   280 #define RTL8139B_IO_SIZE 256

   281 

   282 #define RTL8129_CAPS	HAS_MII_XCVR

   283 #define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   284 

   285 typedef enum {

   286 	RTL8139 = 0,

   287 	RTL8129,

   288 } board_t;

   289 

   290 

   291 /* indexed by board_t, above */

   292 static struct {

   293 	const char *name;

   294 	u32 hw_flags;

   295 } board_info[] __devinitdata = {

   296 	{ "RealTek RTL8139", RTL8139_CAPS },

   297 	{ "RealTek RTL8129", RTL8129_CAPS },

   298 };

   299 

   300 

   301 static struct pci_device_id rtl8139_pci_tbl[] = {

   302 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   305 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   306 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   308 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   309 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   310 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   311 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   312 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   313 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   314 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   315 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   316 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   317 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   318 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   319 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   320 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 

   321 

   322 #ifdef CONFIG_SH_SECUREEDGE5410

   323 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   324 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   325 #endif

   326 #ifdef CONFIG_8139TOO_8129

   327 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   328 #endif

   329 

   330 	/* some crazy cards report invalid vendor ids like

   331 	 * 0x0001 here.  The other ids are valid and constant,

   332 	 * so we simply don't match on the main vendor id.

   333 	 */

   334 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   335 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   336 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   337 

   338 	{0,}

   339 };

   340 

   341 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   342 

   343 /* prevent driver from being loaded automatically */

   344 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   345 

   346 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   347 

   348 static struct {

   349 	const char str[ETH_GSTRING_LEN];

   350 } ethtool_stats_keys[] = {

   351 	{ "early_rx" },

   352 	{ "tx_buf_mapped" },

   353 	{ "tx_timeouts" },

   354 	{ "rx_lost_in_ring" },

   355 };

   356 

   357 /* The rest of these values should never change. */

   358 

   359 /* Symbolic offsets to registers. */

   360 enum RTL8139_registers {

   361 	MAC0 = 0,		/* Ethernet hardware address. */

   362 	MAR0 = 8,		/* Multicast filter. */

   363 	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   364 	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   365 	RxBuf = 0x30,

   366 	ChipCmd = 0x37,

   367 	RxBufPtr = 0x38,

   368 	RxBufAddr = 0x3A,

   369 	IntrMask = 0x3C,

   370 	IntrStatus = 0x3E,

   371 	TxConfig = 0x40,

   372 	RxConfig = 0x44,

   373 	Timer = 0x48,		/* A general-purpose counter. */

   374 	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   375 	Cfg9346 = 0x50,

   376 	Config0 = 0x51,

   377 	Config1 = 0x52,

   378 	FlashReg = 0x54,

   379 	MediaStatus = 0x58,

   380 	Config3 = 0x59,

   381 	Config4 = 0x5A,		/* absent on RTL-8139A */

   382 	HltClk = 0x5B,

   383 	MultiIntr = 0x5C,

   384 	TxSummary = 0x60,

   385 	BasicModeCtrl = 0x62,

   386 	BasicModeStatus = 0x64,

   387 	NWayAdvert = 0x66,

   388 	NWayLPAR = 0x68,

   389 	NWayExpansion = 0x6A,

   390 	/* Undocumented registers, but required for proper operation. */

   391 	FIFOTMS = 0x70,		/* FIFO Control and test. */

   392 	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   393 	PARA78 = 0x78,

   394 	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   395 	Config5 = 0xD8,		/* absent on RTL-8139A */

   396 };

   397 

   398 enum ClearBitMasks {

   399 	MultiIntrClear = 0xF000,

   400 	ChipCmdClear = 0xE2,

   401 	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   402 };

   403 

   404 enum ChipCmdBits {

   405 	CmdReset = 0x10,

   406 	CmdRxEnb = 0x08,

   407 	CmdTxEnb = 0x04,

   408 	RxBufEmpty = 0x01,

   409 };

   410 

   411 /* Interrupt register bits, using my own meaningful names. */

   412 enum IntrStatusBits {

   413 	PCIErr = 0x8000,

   414 	PCSTimeout = 0x4000,

   415 	RxFIFOOver = 0x40,

   416 	RxUnderrun = 0x20,

   417 	RxOverflow = 0x10,

   418 	TxErr = 0x08,

   419 	TxOK = 0x04,

   420 	RxErr = 0x02,

   421 	RxOK = 0x01,

   422 

   423 	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   424 };

   425 

   426 enum TxStatusBits {

   427 	TxHostOwns = 0x2000,

   428 	TxUnderrun = 0x4000,

   429 	TxStatOK = 0x8000,

   430 	TxOutOfWindow = 0x20000000,

   431 	TxAborted = 0x40000000,

   432 	TxCarrierLost = 0x80000000,

   433 };

   434 enum RxStatusBits {

   435 	RxMulticast = 0x8000,

   436 	RxPhysical = 0x4000,

   437 	RxBroadcast = 0x2000,

   438 	RxBadSymbol = 0x0020,

   439 	RxRunt = 0x0010,

   440 	RxTooLong = 0x0008,

   441 	RxCRCErr = 0x0004,

   442 	RxBadAlign = 0x0002,

   443 	RxStatusOK = 0x0001,

   444 };

   445 

   446 /* Bits in RxConfig. */

   447 enum rx_mode_bits {

   448 	AcceptErr = 0x20,

   449 	AcceptRunt = 0x10,

   450 	AcceptBroadcast = 0x08,

   451 	AcceptMulticast = 0x04,

   452 	AcceptMyPhys = 0x02,

   453 	AcceptAllPhys = 0x01,

   454 };

   455 

   456 /* Bits in TxConfig. */

   457 enum tx_config_bits {

   458 

   459         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   460         TxIFGShift = 24,

   461         TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   462         TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   463         TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   464         TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   465 

   466 	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   467 	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   468 	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   469 	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   470 	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   471 

   472 	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   473 };

   474 

   475 /* Bits in Config1 */

   476 enum Config1Bits {

   477 	Cfg1_PM_Enable = 0x01,

   478 	Cfg1_VPD_Enable = 0x02,

   479 	Cfg1_PIO = 0x04,

   480 	Cfg1_MMIO = 0x08,

   481 	LWAKE = 0x10,		/* not on 8139, 8139A */

   482 	Cfg1_Driver_Load = 0x20,

   483 	Cfg1_LED0 = 0x40,

   484 	Cfg1_LED1 = 0x80,

   485 	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   486 	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   487 };

   488 

   489 /* Bits in Config3 */

   490 enum Config3Bits {

   491 	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   492 	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   493 	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   494 	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   495 	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   496 	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   497 	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   498 	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   499 };

   500 

   501 /* Bits in Config4 */

   502 enum Config4Bits {

   503 	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   504 };

   505 

   506 /* Bits in Config5 */

   507 enum Config5Bits {

   508 	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   509 	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   510 	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   511 	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   512 	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   513 	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   514 	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   515 };

   516 

   517 enum RxConfigBits {

   518 	/* rx fifo threshold */

   519 	RxCfgFIFOShift = 13,

   520 	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   521 

   522 	/* Max DMA burst */

   523 	RxCfgDMAShift = 8,

   524 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   525 

   526 	/* rx ring buffer length */

   527 	RxCfgRcv8K = 0,

   528 	RxCfgRcv16K = (1 << 11),

   529 	RxCfgRcv32K = (1 << 12),

   530 	RxCfgRcv64K = (1 << 11) | (1 << 12),

   531 

   532 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   533 	RxNoWrap = (1 << 7),

   534 };

   535 

   536 /* Twister tuning parameters from RealTek.

   537    Completely undocumented, but required to tune bad links on some boards. */

   538 enum CSCRBits {

   539 	CSCR_LinkOKBit = 0x0400,

   540 	CSCR_LinkChangeBit = 0x0800,

   541 	CSCR_LinkStatusBits = 0x0f000,

   542 	CSCR_LinkDownOffCmd = 0x003c0,

   543 	CSCR_LinkDownCmd = 0x0f3c0,

   544 };

   545 

   546 enum Cfg9346Bits {

   547 	Cfg9346_Lock = 0x00,

   548 	Cfg9346_Unlock = 0xC0,

   549 };

   550 

   551 typedef enum {

   552 	CH_8139 = 0,

   553 	CH_8139_K,

   554 	CH_8139A,

   555 	CH_8139A_G,

   556 	CH_8139B,

   557 	CH_8130,

   558 	CH_8139C,

   559 	CH_8100,

   560 	CH_8100B_8139D,

   561 	CH_8101,

   562 } chip_t;

   563 

   564 enum chip_flags {

   565 	HasHltClk = (1 << 0),

   566 	HasLWake = (1 << 1),

   567 };

   568 

   569 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   570 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   571 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   572 

   573 /* directly indexed by chip_t, above */

   574 const static struct {

   575 	const char *name;

   576 	u32 version; /* from RTL8139C/RTL8139D docs */

   577 	u32 flags;

   578 } rtl_chip_info[] = {

   579 	{ "RTL-8139",

   580 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   581 	  HasHltClk,

   582 	},

   583 

   584 	{ "RTL-8139 rev K",

   585 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   586 	  HasHltClk,

   587 	},

   588 

   589 	{ "RTL-8139A",

   590 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   591 	  HasHltClk, /* XXX undocumented? */

   592 	},

   593 

   594 	{ "RTL-8139A rev G",

   595 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   596 	  HasHltClk, /* XXX undocumented? */

   597 	},

   598 

   599 	{ "RTL-8139B",

   600 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   601 	  HasLWake,

   602 	},

   603 

   604 	{ "RTL-8130",

   605 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   606 	  HasLWake,

   607 	},

   608 

   609 	{ "RTL-8139C",

   610 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   611 	  HasLWake,

   612 	},

   613 

   614 	{ "RTL-8100",

   615 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   616  	  HasLWake,

   617  	},

   618 

   619 	{ "RTL-8100B/8139D",

   620 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   621 	  HasLWake,

   622 	},

   623 

   624 	{ "RTL-8101",

   625 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   626 	  HasLWake,

   627 	},

   628 };

   629 

   630 struct rtl_extra_stats {

   631 	unsigned long early_rx;

   632 	unsigned long tx_buf_mapped;

   633 	unsigned long tx_timeouts;

   634 	unsigned long rx_lost_in_ring;

   635 };

   636 

   637 struct rtl8139_private {

   638 	void __iomem *mmio_addr;

   639 	int drv_flags;

   640 	struct pci_dev *pci_dev;

   641 	u32 msg_enable;

   642 	struct net_device_stats stats;

   643 	unsigned char *rx_ring;

   644 	unsigned int cur_rx;	/* Index into the Rx buffer of next Rx pkt. */

   645 	unsigned int tx_flag;

   646 	unsigned long cur_tx;

   647 	unsigned long dirty_tx;

   648 	unsigned char *tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   649 	unsigned char *tx_bufs;	/* Tx bounce buffer region. */

   650 	dma_addr_t rx_ring_dma;

   651 	dma_addr_t tx_bufs_dma;

   652 	signed char phys[4];		/* MII device addresses. */

   653 	char twistie, twist_row, twist_col;	/* Twister tune state. */

   654 	unsigned int default_port:4;	/* Last dev->if_port value. */

   655 	spinlock_t lock;

   656 	spinlock_t rx_lock;

   657 	chip_t chipset;

   658 	pid_t thr_pid;

   659 	wait_queue_head_t thr_wait;

   660 	struct completion thr_exited;

   661 	u32 rx_config;

   662 	struct rtl_extra_stats xstats;

   663 	int time_to_die;

   664 	struct mii_if_info mii;

   665 	unsigned int regs_len;

   666 	unsigned long fifo_copy_timeout;

   667 };

   668 

   669 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   670 

   671 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   672 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   673 MODULE_LICENSE("GPL");

   674 MODULE_VERSION(EC_MASTER_VERSION);

   675 

   676 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   677 

   678 module_param(multicast_filter_limit, int, 0);

   679 module_param_array(media, int, NULL, 0);

   680 module_param_array(full_duplex, int, NULL, 0);

   681 module_param(debug, int, 0);

   682 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   683 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   684 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   685 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   686 

   687 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   688 

   689 module_param(ec_device_index, int, -1);

   690 module_param(ec_device_master_index, int, 0);

   691 MODULE_PARM_DESC(ec_device_index,

   692                  "Index of the device reserved for EtherCAT.");

   693 MODULE_PARM_DESC(ec_device_master_index,

   694                  "Index of the EtherCAT master to register the device.");

   695 

   696 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   697 

   698 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   699 static int rtl8139_open (struct net_device *dev);

   700 static int mdio_read (struct net_device *dev, int phy_id, int location);

   701 static void mdio_write (struct net_device *dev, int phy_id, int location,

   702 			int val);

   703 static void rtl8139_start_thread(struct net_device *dev);

   704 static void rtl8139_tx_timeout (struct net_device *dev);

   705 static void rtl8139_init_ring (struct net_device *dev);

   706 static int rtl8139_start_xmit (struct sk_buff *skb,

   707 			       struct net_device *dev);

   708 int rtl8139_poll(struct net_device *dev, int *budget);

   709 #ifdef CONFIG_NET_POLL_CONTROLLER

   710 static void rtl8139_poll_controller(struct net_device *dev);

   711 #endif

   712 irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,

   713                                struct pt_regs *regs);

   714 static int rtl8139_close (struct net_device *dev);

   715 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   716 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   717 static void rtl8139_set_rx_mode (struct net_device *dev);

   718 static void __set_rx_mode (struct net_device *dev);

   719 static void rtl8139_hw_start (struct net_device *dev);

   720 static struct ethtool_ops rtl8139_ethtool_ops;

   721 

   722 /* write MMIO register, with flush */

   723 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   724 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   725 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   726 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   727 

   728 

   729 #define MMIO_FLUSH_AUDIT_COMPLETE 1

   730 #if MMIO_FLUSH_AUDIT_COMPLETE

   731 

   732 /* write MMIO register */

   733 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   734 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   735 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   736 

   737 #else

   738 

   739 /* write MMIO register, then flush */

   740 #define RTL_W8		RTL_W8_F

   741 #define RTL_W16		RTL_W16_F

   742 #define RTL_W32		RTL_W32_F

   743 

   744 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */

   745 

   746 /* read MMIO register */

   747 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   748 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   749 #define RTL_R32(reg)		((unsigned long) ioread32 (ioaddr + (reg)))

   750 

   751 

   752 static const u16 rtl8139_intr_mask =

   753 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   754 	TxErr | TxOK | RxErr | RxOK;

   755 

   756 static const u16 rtl8139_norx_intr_mask =

   757 	PCIErr | PCSTimeout | RxUnderrun |

   758 	TxErr | TxOK | RxErr ;

   759 

   760 #if RX_BUF_IDX == 0

   761 static const unsigned int rtl8139_rx_config =

   762 	RxCfgRcv8K | RxNoWrap |

   763 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   764 	(RX_DMA_BURST << RxCfgDMAShift);

   765 #elif RX_BUF_IDX == 1

   766 static const unsigned int rtl8139_rx_config =

   767 	RxCfgRcv16K | RxNoWrap |

   768 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   769 	(RX_DMA_BURST << RxCfgDMAShift);

   770 #elif RX_BUF_IDX == 2

   771 static const unsigned int rtl8139_rx_config =

   772 	RxCfgRcv32K | RxNoWrap |

   773 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   774 	(RX_DMA_BURST << RxCfgDMAShift);

   775 #elif RX_BUF_IDX == 3

   776 static const unsigned int rtl8139_rx_config =

   777 	RxCfgRcv64K |

   778 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   779 	(RX_DMA_BURST << RxCfgDMAShift);

   780 #else

   781 #error "Invalid configuration for 8139_RXBUF_IDX"

   782 #endif

   783 

   784 static const unsigned int rtl8139_tx_config =

   785 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   786 

   787 static void __rtl8139_cleanup_dev (struct net_device *dev)

   788 {

   789 	struct rtl8139_private *tp = netdev_priv(dev);

   790 	struct pci_dev *pdev;

   791 

   792 	assert (dev != NULL);

   793 	assert (tp->pci_dev != NULL);

   794 	pdev = tp->pci_dev;

   795 

   796 #ifdef USE_IO_OPS

   797 	if (tp->mmio_addr)

   798 		ioport_unmap (tp->mmio_addr);

   799 #else

   800 	if (tp->mmio_addr)

   801 		pci_iounmap (pdev, tp->mmio_addr);

   802 #endif /* USE_IO_OPS */

   803 

   804 	/* it's ok to call this even if we have no regions to free */

   805 	pci_release_regions (pdev);

   806 

   807 	free_netdev(dev);

   808 	pci_set_drvdata (pdev, NULL);

   809 }

   810 

   811 

   812 static void rtl8139_chip_reset (void __iomem *ioaddr)

   813 {

   814 	int i;

   815 

   816 	/* Soft reset the chip. */

   817 	RTL_W8 (ChipCmd, CmdReset);

   818 

   819 	/* Check that the chip has finished the reset. */

   820 	for (i = 1000; i > 0; i--) {

   821 		barrier();

   822 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   823 		    break;

   824 		udelay (10);

   825 	}

   826 }

   827 

   828 

   829 static int __devinit rtl8139_init_board (struct pci_dev *pdev,

   830 					 struct net_device **dev_out)

   831 {

   832 	void __iomem *ioaddr;

   833 	struct net_device *dev;

   834 	struct rtl8139_private *tp;

   835 	u8 tmp8;

   836 	int rc, disable_dev_on_err = 0;

   837 	unsigned int i;

   838 	unsigned long pio_start, pio_end, pio_flags, pio_len;

   839 	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;

   840 	u32 version;

   841 

   842 	assert (pdev != NULL);

   843 

   844 	*dev_out = NULL;

   845 

   846 	/* dev and priv zeroed in alloc_etherdev */

   847 	dev = alloc_etherdev (sizeof (*tp));

   848 	if (dev == NULL) {

   849 		printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));

   850 		return -ENOMEM;

   851 	}

   852 	SET_MODULE_OWNER(dev);

   853 	SET_NETDEV_DEV(dev, &pdev->dev);

   854 

   855 	tp = netdev_priv(dev);

   856 	tp->pci_dev = pdev;

   857 

   858 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   859 	rc = pci_enable_device (pdev);

   860 	if (rc)

   861 		goto err_out;

   862 

   863 	pio_start = pci_resource_start (pdev, 0);

   864 	pio_end = pci_resource_end (pdev, 0);

   865 	pio_flags = pci_resource_flags (pdev, 0);

   866 	pio_len = pci_resource_len (pdev, 0);

   867 

   868 	mmio_start = pci_resource_start (pdev, 1);

   869 	mmio_end = pci_resource_end (pdev, 1);

   870 	mmio_flags = pci_resource_flags (pdev, 1);

   871 	mmio_len = pci_resource_len (pdev, 1);

   872 

   873 	/* set this immediately, we need to know before

   874 	 * we talk to the chip directly */

   875 	DPRINTK("PIO region size == 0x%02X\n", pio_len);

   876 	DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);

   877 

   878 #ifdef USE_IO_OPS

   879 	/* make sure PCI base addr 0 is PIO */

   880 	if (!(pio_flags & IORESOURCE_IO)) {

   881 		printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));

   882 		rc = -ENODEV;

   883 		goto err_out;

   884 	}

   885 	/* check for weird/broken PCI region reporting */

   886 	if (pio_len < RTL_MIN_IO_SIZE) {

   887 		printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));

   888 		rc = -ENODEV;

   889 		goto err_out;

   890 	}

   891 #else

   892 	/* make sure PCI base addr 1 is MMIO */

   893 	if (!(mmio_flags & IORESOURCE_MEM)) {

   894 		printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));

   895 		rc = -ENODEV;

   896 		goto err_out;

   897 	}

   898 	if (mmio_len < RTL_MIN_IO_SIZE) {

   899 		printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));

   900 		rc = -ENODEV;

   901 		goto err_out;

   902 	}

   903 #endif

   904 

   905 	rc = pci_request_regions (pdev, "8139too");

   906 	if (rc)

   907 		goto err_out;

   908 	disable_dev_on_err = 1;

   909 

   910 	/* enable PCI bus-mastering */

   911 	pci_set_master (pdev);

   912 

   913 #ifdef USE_IO_OPS

   914 	ioaddr = ioport_map(pio_start, pio_len);

   915 	if (!ioaddr) {

   916 		printk (KERN_ERR PFX "%s: cannot map PIO, aborting\n", pci_name(pdev));

   917 		rc = -EIO;

   918 		goto err_out;

   919 	}

   920 	dev->base_addr = pio_start;

   921 	tp->mmio_addr = ioaddr;

   922 	tp->regs_len = pio_len;

   923 #else

   924 	/* ioremap MMIO region */

   925 	ioaddr = pci_iomap(pdev, 1, 0);

   926 	if (ioaddr == NULL) {

   927 		printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));

   928 		rc = -EIO;

   929 		goto err_out;

   930 	}

   931 	dev->base_addr = (long) ioaddr;

   932 	tp->mmio_addr = ioaddr;

   933 	tp->regs_len = mmio_len;

   934 #endif /* USE_IO_OPS */

   935 

   936 	/* Bring old chips out of low-power mode. */

   937 	RTL_W8 (HltClk, 'R');

   938 

   939 	/* check for missing/broken hardware */

   940 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   941 		printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",

   942 			pci_name(pdev));

   943 		rc = -EIO;

   944 		goto err_out;

   945 	}

   946 

   947 	/* identify chip attached to board */

   948 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   949 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   950 		if (version == rtl_chip_info[i].version) {

   951 			tp->chipset = i;

   952 			goto match;

   953 		}

   954 

   955 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   956 	printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",

   957 		pci_name(pdev));

   958         printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));

   959 	tp->chipset = 0;

   960 

   961 match:

   962 	DPRINTK ("chipset id (%d) == index %d, '%s'\n",

   963 		 version, i, rtl_chip_info[i].name);

   964 

   965 	if (tp->chipset >= CH_8139B) {

   966 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   967 		DPRINTK("PCI PM wakeup\n");

   968 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   969 		    (tmp8 & LWAKE))

   970 			new_tmp8 &= ~LWAKE;

   971 		new_tmp8 |= Cfg1_PM_Enable;

   972 		if (new_tmp8 != tmp8) {

   973 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   974 			RTL_W8 (Config1, tmp8);

   975 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   976 		}

   977 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   978 			tmp8 = RTL_R8 (Config4);

   979 			if (tmp8 & LWPTN) {

   980 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   981 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   982 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   983 			}

   984 		}

   985 	} else {

   986 		DPRINTK("Old chip wakeup\n");

   987 		tmp8 = RTL_R8 (Config1);

   988 		tmp8 &= ~(SLEEP | PWRDN);

   989 		RTL_W8 (Config1, tmp8);

   990 	}

   991 

   992 	rtl8139_chip_reset (ioaddr);

   993 

   994 	*dev_out = dev;

   995 	return 0;

   996 

   997 err_out:

   998 	__rtl8139_cleanup_dev (dev);

   999 	if (disable_dev_on_err)

  1000 		pci_disable_device (pdev);

  1001 	return rc;

  1002 }

  1003 

  1004 

  1005 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

  1006 				       const struct pci_device_id *ent)

  1007 {

  1008 	struct net_device *dev = NULL;

  1009 	struct rtl8139_private *tp;

  1010 	int i, addr_len, option;

  1011 	void __iomem *ioaddr;

  1012 	static int board_idx = -1;

  1013 	u8 pci_rev;

  1014 

  1015 	assert (pdev != NULL);

  1016 	assert (ent != NULL);

  1017 

  1018 	board_idx++;

  1019 

  1020 	/* when we're built into the kernel, the driver version message

  1021 	 * is only printed if at least one 8139 board has been found

  1022 	 */

  1023 #ifndef MODULE

  1024 	{

  1025 		static int printed_version;

  1026 		if (!printed_version++)

  1027 			printk (KERN_INFO RTL8139_DRIVER_NAME "\n");

  1028 	}

  1029 #endif

  1030 

  1031 	pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);

  1032 

  1033 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1034 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {

  1035 		printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",

  1036 		       pci_name(pdev), pdev->vendor, pdev->device, pci_rev);

  1037 		printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");

  1038 	}

  1039 

  1040 	i = rtl8139_init_board (pdev, &dev);

  1041 	if (i < 0)

  1042 		return i;

  1043 

  1044 	assert (dev != NULL);

  1045 	tp = netdev_priv(dev);

  1046 

  1047 	/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

  1048 

  1049 	if (board_idx == ec_device_index) {

  1050         rtl_ec_net_dev = dev;

  1051         strcpy(dev->name, "ec0");

  1052 	}

  1053 

  1054 	/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

  1055 

  1056 	ioaddr = tp->mmio_addr;

  1057 	assert (ioaddr != NULL);

  1058 

  1059 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1060 	for (i = 0; i < 3; i++)

  1061 		((u16 *) (dev->dev_addr))[i] =

  1062 		    le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));

  1063 

  1064 	/* The Rtl8139-specific entries in the device structure. */

  1065 	dev->open = rtl8139_open;

  1066 	dev->hard_start_xmit = rtl8139_start_xmit;

  1067 	dev->poll = rtl8139_poll;

  1068 	dev->weight = 64;

  1069 	dev->stop = rtl8139_close;

  1070 	dev->get_stats = rtl8139_get_stats;

  1071 	dev->set_multicast_list = rtl8139_set_rx_mode;

  1072 	dev->do_ioctl = netdev_ioctl;

  1073 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1074 	dev->tx_timeout = rtl8139_tx_timeout;

  1075 	dev->watchdog_timeo = TX_TIMEOUT;

  1076 #ifdef CONFIG_NET_POLL_CONTROLLER

  1077 	dev->poll_controller = rtl8139_poll_controller;

  1078 #endif

  1079 

  1080 	/* note: the hardware is not capable of sg/csum/highdma, however

  1081 	 * through the use of skb_copy_and_csum_dev we enable these

  1082 	 * features

  1083 	 */

  1084 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1085 

  1086 	dev->irq = pdev->irq;

  1087 

  1088 	/* tp zeroed and aligned in alloc_etherdev */

  1089 	tp = netdev_priv(dev);

  1090 

  1091 	/* note: tp->chipset set in rtl8139_init_board */

  1092 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1093 	tp->mmio_addr = ioaddr;

  1094 	tp->msg_enable =

  1095 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1096 	spin_lock_init (&tp->lock);

  1097 	spin_lock_init (&tp->rx_lock);

  1098 	init_waitqueue_head (&tp->thr_wait);

  1099 	init_completion (&tp->thr_exited);

  1100 	tp->mii.dev = dev;

  1101 	tp->mii.mdio_read = mdio_read;

  1102 	tp->mii.mdio_write = mdio_write;

  1103 	tp->mii.phy_id_mask = 0x3f;

  1104 	tp->mii.reg_num_mask = 0x1f;

  1105 

  1106 	/* dev is fully set up and ready to use now */

  1107 

  1108 	/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

  1109 

  1110     if (dev != rtl_ec_net_dev) {

  1111         DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);

  1112         i = register_netdev (dev);

  1113         if (i) goto err_out;

  1114 	}

  1115 

  1116 	/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

  1117 

  1118 	pci_set_drvdata (pdev, dev);

  1119 

  1120 	printk (KERN_INFO "%s: %s at 0x%lx, "

  1121 		"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "

  1122 		"IRQ %d\n",

  1123 		dev->name,

  1124 		board_info[ent->driver_data].name,

  1125 		dev->base_addr,

  1126 		dev->dev_addr[0], dev->dev_addr[1],

  1127 		dev->dev_addr[2], dev->dev_addr[3],

  1128 		dev->dev_addr[4], dev->dev_addr[5],

  1129 		dev->irq);

  1130 

  1131 	printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",

  1132 		dev->name, rtl_chip_info[tp->chipset].name);

  1133 

  1134 	/* Find the connected MII xcvrs.

  1135 	   Doing this in open() would allow detecting external xcvrs later, but

  1136 	   takes too much time. */