1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006-2009  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10  *  modify it under the terms of the GNU General Public License version 2, as

    11  *  published by the Free Software Foundation.

    12  *

    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16  *  Public License for more details.

    17  *

    18  *  You should have received a copy of the GNU General Public License along

    19  *  with the IgH EtherCAT Master; if not, write to the Free Software

    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21  *

    22  *  ---

    23  *

    24  *  The license mentioned above concerns the source code only. Using the

    25  *  EtherCAT technology and brand is only permitted in compliance with the

    26  *  industrial property and similar rights of Beckhoff Automation GmbH.

    27  *

    28  *****************************************************************************/

    29 

    30 /**

    31    \file

    32    EtherCAT driver for RTL8139-compatible NICs.

    33 */

    34 

    35 /*****************************************************************************/

    36 

    37 /*

    38   Former documentation:

    39 

    40 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41 

    42 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    43 	Copyright 2000-2002 Jeff Garzik

    44 

    45 	Much code comes from Donald Becker's rtl8139.c driver,

    46 	versions 1.13 and older.  This driver was originally based

    47 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48 

    49 	-----<snip>-----

    50 

    51         	Written 1997-2001 by Donald Becker.

    52 		This software may be used and distributed according to the

    53 		terms of the GNU General Public License (GPL), incorporated

    54 		herein by reference.  Drivers based on or derived from this

    55 		code fall under the GPL and must retain the authorship,

    56 		copyright and license notice.  This file is not a complete

    57 		program and may only be used when the entire operating

    58 		system is licensed under the GPL.

    59 

    60 		This driver is for boards based on the RTL8129 and RTL8139

    61 		PCI ethernet chips.

    62 

    63 		The author may be reached as becker@scyld.com, or C/O Scyld

    64 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65 		MD 21403

    66 

    67 		Support and updates available at

    68 		http://www.scyld.com/network/rtl8139.html

    69 

    70 		Twister-tuning table provided by Kinston

    71 		<shangh@realtek.com.tw>.

    72 

    73 	-----<snip>-----

    74 

    75 	This software may be used and distributed according to the terms

    76 	of the GNU General Public License, incorporated herein by reference.

    77 

    78 	Contributors:

    79 

    80 		Donald Becker - he wrote the original driver, kudos to him!

    81 		(but please don't e-mail him for support, this isn't his driver)

    82 

    83 		Tigran Aivazian - bug fixes, skbuff free cleanup

    84 

    85 		Martin Mares - suggestions for PCI cleanup

    86 

    87 		David S. Miller - PCI DMA and softnet updates

    88 

    89 		Ernst Gill - fixes ported from BSD driver

    90 

    91 		Daniel Kobras - identified specific locations of

    92 			posted MMIO write bugginess

    93 

    94 		Gerard Sharp - bug fix, testing and feedback

    95 

    96 		David Ford - Rx ring wrap fix

    97 

    98 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    99 		to find and fix a crucial bug on older chipsets.

   100 

   101 		Donald Becker/Chris Butterworth/Marcus Westergren -

   102 		Noticed various Rx packet size-related buglets.

   103 

   104 		Santiago Garcia Mantinan - testing and feedback

   105 

   106 		Jens David - 2.2.x kernel backports

   107 

   108 		Martin Dennett - incredibly helpful insight on undocumented

   109 		features of the 8139 chips

   110 

   111 		Jean-Jacques Michel - bug fix

   112 

   113 		Tobias Ringström - Rx interrupt status checking suggestion

   114 

   115 		Andrew Morton - Clear blocked signals, avoid

   116 		buffer overrun setting current->comm.

   117 

   118 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   119 

   120 		Robert Kuebel - Save kernel thread from dying on any signal.

   121 

   122 	Submitting bug reports:

   123 

   124 		"rtl8139-diag -mmmaaavvveefN" output

   125 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   126 

   127 */

   128 

   129 #define DRV_NAME	"ec_8139too"

   130 #define DRV_VERSION	"0.9.28"

   131 

   132 

   133 #include <linux/module.h>

   134 #include <linux/kernel.h>

   135 #include <linux/compiler.h>

   136 #include <linux/pci.h>

   137 #include <linux/init.h>

   138 #include <linux/netdevice.h>

   139 #include <linux/etherdevice.h>

   140 #include <linux/rtnetlink.h>

   141 #include <linux/delay.h>

   142 #include <linux/ethtool.h>

   143 #include <linux/mii.h>

   144 #include <linux/completion.h>

   145 #include <linux/crc32.h>

   146 #include <linux/io.h>

   147 #include <linux/uaccess.h>

   148 #include <asm/irq.h>

   149 

   150 #include "../globals.h"

   151 #include "ecdev.h"

   152 

   153 #define RTL8139_DRIVER_NAME DRV_NAME \

   154                             " EtherCAT-capable Fast Ethernet driver " \

   155                             DRV_VERSION ", master " EC_MASTER_VERSION

   156 

   157 #define PFX DRV_NAME ": "

   158 

   159 /* Default Message level */

   160 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   161                                  NETIF_MSG_PROBE  | \

   162                                  NETIF_MSG_LINK)

   163 

   164 

   165 /* define to 1, 2 or 3 to enable copious debugging info */

   166 #define RTL8139_DEBUG 0

   167 

   168 /* define to 1 to disable lightweight runtime debugging checks */

   169 #undef RTL8139_NDEBUG

   170 

   171 

   172 #if RTL8139_DEBUG

   173 /* note: prints function name for you */

   174 #  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)

   175 #else

   176 #  define DPRINTK(fmt, args...)

   177 #endif

   178 

   179 #ifdef RTL8139_NDEBUG

   180 #  define assert(expr) do {} while (0)

   181 #else

   182 #  define assert(expr) \

   183         if(unlikely(!(expr))) {				        \

   184         printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   185 	#expr, __FILE__, __func__, __LINE__);			\

   186         }

   187 #endif

   188 

   189 

   190 /* A few user-configurable values. */

   191 /* media options */

   192 #define MAX_UNITS 8

   193 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   194 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   195 

   196 /* Whether to use MMIO or PIO. Default to MMIO. */

   197 #ifdef CONFIG_8139TOO_PIO

   198 static int use_io = 1;

   199 #else

   200 static int use_io = 0;

   201 #endif

   202 

   203 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   204    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   205 static int multicast_filter_limit = 32;

   206 

   207 /* bitmapped message enable number */

   208 static int debug = -1;

   209 

   210 /*

   211  * Receive ring size

   212  * Warning: 64K ring has hardware issues and may lock up.

   213  */

   214 #if defined(CONFIG_SH_DREAMCAST)

   215 #define RX_BUF_IDX 0	/* 8K ring */

   216 #else

   217 #define RX_BUF_IDX	2	/* 32K ring */

   218 #endif

   219 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   220 #define RX_BUF_PAD	16

   221 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   222 

   223 #if RX_BUF_LEN == 65536

   224 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   225 #else

   226 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   227 #endif

   228 

   229 /* Number of Tx descriptor registers. */

   230 #define NUM_TX_DESC	4

   231 

   232 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   233 #define MAX_ETH_FRAME_SIZE	1536

   234 

   235 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   236 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   237 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   238 

   239 /* PCI Tuning Parameters

   240    Threshold is bytes transferred to chip before transmission starts. */

   241 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   242 

   243 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   244 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   245 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   246 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   247 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   248 

   249 /* Operational parameters that usually are not changed. */

   250 /* Time in jiffies before concluding the transmitter is hung. */

   251 #define TX_TIMEOUT  (6*HZ)

   252 

   253 

   254 enum {

   255 	HAS_MII_XCVR = 0x010000,

   256 	HAS_CHIP_XCVR = 0x020000,

   257 	HAS_LNK_CHNG = 0x040000,

   258 };

   259 

   260 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   261 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   262 #define RTL_MIN_IO_SIZE 0x80

   263 #define RTL8139B_IO_SIZE 256

   264 

   265 #define RTL8129_CAPS	HAS_MII_XCVR

   266 #define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   267 

   268 typedef enum {

   269 	RTL8139 = 0,

   270 	RTL8129,

   271 } board_t;

   272 

   273 

   274 /* indexed by board_t, above */

   275 static const struct {

   276 	const char *name;

   277 	u32 hw_flags;

   278 } board_info[] __devinitdata = {

   279 	{ "RealTek RTL8139", RTL8139_CAPS },

   280 	{ "RealTek RTL8129", RTL8129_CAPS },

   281 };

   282 

   283 

   284 static struct pci_device_id rtl8139_pci_tbl[] = {

   285 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   302 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304 

   305 #ifdef CONFIG_SH_SECUREEDGE5410

   306 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   307 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   308 #endif

   309 #ifdef CONFIG_8139TOO_8129

   310 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   311 #endif

   312 

   313 	/* some crazy cards report invalid vendor ids like

   314 	 * 0x0001 here.  The other ids are valid and constant,

   315 	 * so we simply don't match on the main vendor id.

   316 	 */

   317 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   318 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   319 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   320 

   321 	{0,}

   322 };

   323 

   324 /* prevent driver from being loaded automatically */

   325 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   326 

   327 static struct {

   328 	const char str[ETH_GSTRING_LEN];

   329 } ethtool_stats_keys[] = {

   330 	{ "early_rx" },

   331 	{ "tx_buf_mapped" },

   332 	{ "tx_timeouts" },

   333 	{ "rx_lost_in_ring" },

   334 };

   335 

   336 /* The rest of these values should never change. */

   337 

   338 /* Symbolic offsets to registers. */

   339 enum RTL8139_registers {

   340 	MAC0		= 0,	 /* Ethernet hardware address. */

   341 	MAR0		= 8,	 /* Multicast filter. */

   342 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   343 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   344 	RxBuf		= 0x30,

   345 	ChipCmd		= 0x37,

   346 	RxBufPtr	= 0x38,

   347 	RxBufAddr	= 0x3A,

   348 	IntrMask	= 0x3C,

   349 	IntrStatus	= 0x3E,

   350 	TxConfig	= 0x40,

   351 	RxConfig	= 0x44,

   352 	Timer		= 0x48,	 /* A general-purpose counter. */

   353 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   354 	Cfg9346		= 0x50,

   355 	Config0		= 0x51,

   356 	Config1		= 0x52,

   357 	TimerInt	= 0x54,

   358 	MediaStatus	= 0x58,

   359 	Config3		= 0x59,

   360 	Config4		= 0x5A,	 /* absent on RTL-8139A */

   361 	HltClk		= 0x5B,

   362 	MultiIntr	= 0x5C,

   363 	TxSummary	= 0x60,

   364 	BasicModeCtrl	= 0x62,

   365 	BasicModeStatus	= 0x64,

   366 	NWayAdvert	= 0x66,

   367 	NWayLPAR	= 0x68,

   368 	NWayExpansion	= 0x6A,

   369 	/* Undocumented registers, but required for proper operation. */

   370 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   371 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   372 	PARA78		= 0x78,

   373 	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   374 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   375 	Config5		= 0xD8,	 /* absent on RTL-8139A */

   376 };

   377 

   378 enum ClearBitMasks {

   379 	MultiIntrClear	= 0xF000,

   380 	ChipCmdClear	= 0xE2,

   381 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   382 };

   383 

   384 enum ChipCmdBits {

   385 	CmdReset	= 0x10,

   386 	CmdRxEnb	= 0x08,

   387 	CmdTxEnb	= 0x04,

   388 	RxBufEmpty	= 0x01,

   389 };

   390 

   391 /* Interrupt register bits, using my own meaningful names. */

   392 enum IntrStatusBits {

   393 	PCIErr		= 0x8000,

   394 	PCSTimeout	= 0x4000,

   395 	RxFIFOOver	= 0x40,

   396 	RxUnderrun	= 0x20,

   397 	RxOverflow	= 0x10,

   398 	TxErr		= 0x08,

   399 	TxOK		= 0x04,

   400 	RxErr		= 0x02,

   401 	RxOK		= 0x01,

   402 

   403 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   404 };

   405 

   406 enum TxStatusBits {

   407 	TxHostOwns	= 0x2000,

   408 	TxUnderrun	= 0x4000,

   409 	TxStatOK	= 0x8000,

   410 	TxOutOfWindow	= 0x20000000,

   411 	TxAborted	= 0x40000000,

   412 	TxCarrierLost	= 0x80000000,

   413 };

   414 enum RxStatusBits {

   415 	RxMulticast	= 0x8000,

   416 	RxPhysical	= 0x4000,

   417 	RxBroadcast	= 0x2000,

   418 	RxBadSymbol	= 0x0020,

   419 	RxRunt		= 0x0010,

   420 	RxTooLong	= 0x0008,

   421 	RxCRCErr	= 0x0004,

   422 	RxBadAlign	= 0x0002,

   423 	RxStatusOK	= 0x0001,

   424 };

   425 

   426 /* Bits in RxConfig. */

   427 enum rx_mode_bits {

   428 	AcceptErr	= 0x20,

   429 	AcceptRunt	= 0x10,

   430 	AcceptBroadcast	= 0x08,

   431 	AcceptMulticast	= 0x04,

   432 	AcceptMyPhys	= 0x02,

   433 	AcceptAllPhys	= 0x01,

   434 };

   435 

   436 /* Bits in TxConfig. */

   437 enum tx_config_bits {

   438         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   439         TxIFGShift	= 24,

   440         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   441         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   442         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   443         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   444 

   445 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   446 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   447 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   448 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   449 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   450 

   451 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   452 };

   453 

   454 /* Bits in Config1 */

   455 enum Config1Bits {

   456 	Cfg1_PM_Enable	= 0x01,

   457 	Cfg1_VPD_Enable	= 0x02,

   458 	Cfg1_PIO	= 0x04,

   459 	Cfg1_MMIO	= 0x08,

   460 	LWAKE		= 0x10,		/* not on 8139, 8139A */

   461 	Cfg1_Driver_Load = 0x20,

   462 	Cfg1_LED0	= 0x40,

   463 	Cfg1_LED1	= 0x80,

   464 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   465 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   466 };

   467 

   468 /* Bits in Config3 */

   469 enum Config3Bits {

   470 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   471 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   472 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   473 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   474 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   475 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   476 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   477 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   478 };

   479 

   480 /* Bits in Config4 */

   481 enum Config4Bits {

   482 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   483 };

   484 

   485 /* Bits in Config5 */

   486 enum Config5Bits {

   487 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   488 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   489 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   490 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   491 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   492 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   493 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   494 };

   495 

   496 enum RxConfigBits {

   497 	/* rx fifo threshold */

   498 	RxCfgFIFOShift	= 13,

   499 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   500 

   501 	/* Max DMA burst */

   502 	RxCfgDMAShift	= 8,

   503 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   504 

   505 	/* rx ring buffer length */

   506 	RxCfgRcv8K	= 0,

   507 	RxCfgRcv16K	= (1 << 11),

   508 	RxCfgRcv32K	= (1 << 12),

   509 	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   510 

   511 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   512 	RxNoWrap	= (1 << 7),

   513 };

   514 

   515 /* Twister tuning parameters from RealTek.

   516    Completely undocumented, but required to tune bad links on some boards. */

   517 enum CSCRBits {

   518 	CSCR_LinkOKBit		= 0x0400,

   519 	CSCR_LinkChangeBit	= 0x0800,

   520 	CSCR_LinkStatusBits	= 0x0f000,

   521 	CSCR_LinkDownOffCmd	= 0x003c0,

   522 	CSCR_LinkDownCmd	= 0x0f3c0,

   523 };

   524 

   525 enum Cfg9346Bits {

   526 	Cfg9346_Lock	= 0x00,

   527 	Cfg9346_Unlock	= 0xC0,

   528 };

   529 

   530 typedef enum {

   531 	CH_8139	= 0,

   532 	CH_8139_K,

   533 	CH_8139A,

   534 	CH_8139A_G,

   535 	CH_8139B,

   536 	CH_8130,

   537 	CH_8139C,

   538 	CH_8100,

   539 	CH_8100B_8139D,

   540 	CH_8101,

   541 } chip_t;

   542 

   543 enum chip_flags {

   544 	HasHltClk	= (1 << 0),

   545 	HasLWake	= (1 << 1),

   546 };

   547 

   548 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   549 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   550 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   551 

   552 /* directly indexed by chip_t, above */

   553 static const struct {

   554 	const char *name;

   555 	u32 version; /* from RTL8139C/RTL8139D docs */

   556 	u32 flags;

   557 } rtl_chip_info[] = {

   558 	{ "RTL-8139",

   559 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   560 	  HasHltClk,

   561 	},

   562 

   563 	{ "RTL-8139 rev K",

   564 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   565 	  HasHltClk,

   566 	},

   567 

   568 	{ "RTL-8139A",

   569 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   570 	  HasHltClk, /* XXX undocumented? */

   571 	},

   572 

   573 	{ "RTL-8139A rev G",

   574 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   575 	  HasHltClk, /* XXX undocumented? */

   576 	},

   577 

   578 	{ "RTL-8139B",

   579 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   580 	  HasLWake,

   581 	},

   582 

   583 	{ "RTL-8130",

   584 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   585 	  HasLWake,

   586 	},

   587 

   588 	{ "RTL-8139C",

   589 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   590 	  HasLWake,

   591 	},

   592 

   593 	{ "RTL-8100",

   594 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   595  	  HasLWake,

   596  	},

   597 

   598 	{ "RTL-8100B/8139D",

   599 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   600 	  HasHltClk /* XXX undocumented? */

   601 	| HasLWake,

   602 	},

   603 

   604 	{ "RTL-8101",

   605 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   606 	  HasLWake,

   607 	},

   608 };

   609 

   610 struct rtl_extra_stats {

   611 	unsigned long early_rx;

   612 	unsigned long tx_buf_mapped;

   613 	unsigned long tx_timeouts;

   614 	unsigned long rx_lost_in_ring;

   615 };

   616 

   617 struct rtl8139_private {

   618 	void __iomem		*mmio_addr;

   619 	int			drv_flags;

   620 	struct pci_dev		*pci_dev;

   621 	u32			msg_enable;

   622 	struct napi_struct	napi;

   623 	struct net_device	*dev;

   624 

   625 	unsigned char		*rx_ring;

   626 	unsigned int		cur_rx;	/* RX buf index of next pkt */

   627 	dma_addr_t		rx_ring_dma;

   628 

   629 	unsigned int		tx_flag;

   630 	unsigned long		cur_tx;

   631 	unsigned long		dirty_tx;

   632 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   633 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */

   634 	dma_addr_t		tx_bufs_dma;

   635 

   636 	signed char		phys[4];	/* MII device addresses. */

   637 

   638 				/* Twister tune state. */

   639 	char			twistie, twist_row, twist_col;

   640 

   641 	unsigned int		watchdog_fired : 1;

   642 	unsigned int		default_port : 4; /* Last dev->if_port value. */

   643 	unsigned int		have_thread : 1;

   644 

   645 	spinlock_t		lock;

   646 	spinlock_t		rx_lock;

   647 

   648 	chip_t			chipset;

   649 	u32			rx_config;

   650 	struct rtl_extra_stats	xstats;

   651 

   652 	struct delayed_work	thread;

   653 

   654 	struct mii_if_info	mii;

   655 	unsigned int		regs_len;

   656 	unsigned long		fifo_copy_timeout;

   657     

   658 	ec_device_t *ecdev;

   659 };

   660 

   661 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   662 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   663 MODULE_LICENSE("GPL");

   664 MODULE_VERSION(EC_MASTER_VERSION);

   665 

   666 module_param(use_io, int, 0);

   667 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");

   668 module_param(multicast_filter_limit, int, 0);

   669 module_param_array(media, int, NULL, 0);

   670 module_param_array(full_duplex, int, NULL, 0);

   671 module_param(debug, int, 0);

   672 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   673 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   674 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   675 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   676 

   677 void ec_poll(struct net_device *);

   678 

   679 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   680 static int rtl8139_open (struct net_device *dev);

   681 static int mdio_read (struct net_device *dev, int phy_id, int location);

   682 static void mdio_write (struct net_device *dev, int phy_id, int location,

   683 			int val);

   684 static void rtl8139_start_thread(struct rtl8139_private *tp);

   685 static void rtl8139_tx_timeout (struct net_device *dev);

   686 static void rtl8139_init_ring (struct net_device *dev);

   687 static int rtl8139_start_xmit (struct sk_buff *skb,

   688 			       struct net_device *dev);

   689 #ifdef CONFIG_NET_POLL_CONTROLLER

   690 static void rtl8139_poll_controller(struct net_device *dev);

   691 #endif

   692 static int rtl8139_poll(struct napi_struct *napi, int budget);

   693 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);

   694 static int rtl8139_close (struct net_device *dev);

   695 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   696 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   697 static void rtl8139_set_rx_mode (struct net_device *dev);

   698 static void __set_rx_mode (struct net_device *dev);

   699 static void rtl8139_hw_start (struct net_device *dev);

   700 static void rtl8139_thread (struct work_struct *work);

   701 static void rtl8139_tx_timeout_task(struct work_struct *work);

   702 static const struct ethtool_ops rtl8139_ethtool_ops;

   703 

   704 /* write MMIO register, with flush */

   705 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   706 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   707 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   708 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   709 

   710 /* write MMIO register */

   711 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   712 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   713 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   714 

   715 /* read MMIO register */

   716 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   717 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   718 #define RTL_R32(reg)		((unsigned long) ioread32 (ioaddr + (reg)))

   719 

   720 

   721 static const u16 rtl8139_intr_mask =

   722 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   723 	TxErr | TxOK | RxErr | RxOK;

   724 

   725 static const u16 rtl8139_norx_intr_mask =

   726 	PCIErr | PCSTimeout | RxUnderrun |

   727 	TxErr | TxOK | RxErr ;

   728 

   729 #if RX_BUF_IDX == 0

   730 static const unsigned int rtl8139_rx_config =

   731 	RxCfgRcv8K | RxNoWrap |

   732 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   733 	(RX_DMA_BURST << RxCfgDMAShift);

   734 #elif RX_BUF_IDX == 1

   735 static const unsigned int rtl8139_rx_config =

   736 	RxCfgRcv16K | RxNoWrap |

   737 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   738 	(RX_DMA_BURST << RxCfgDMAShift);

   739 #elif RX_BUF_IDX == 2

   740 static const unsigned int rtl8139_rx_config =

   741 	RxCfgRcv32K | RxNoWrap |

   742 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   743 	(RX_DMA_BURST << RxCfgDMAShift);

   744 #elif RX_BUF_IDX == 3

   745 static const unsigned int rtl8139_rx_config =

   746 	RxCfgRcv64K |

   747 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   748 	(RX_DMA_BURST << RxCfgDMAShift);

   749 #else

   750 #error "Invalid configuration for 8139_RXBUF_IDX"

   751 #endif

   752 

   753 static const unsigned int rtl8139_tx_config =

   754 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   755 

   756 static void __rtl8139_cleanup_dev (struct net_device *dev)

   757 {

   758 	struct rtl8139_private *tp = netdev_priv(dev);

   759 	struct pci_dev *pdev;

   760 

   761 	assert (dev != NULL);

   762 	assert (tp->pci_dev != NULL);

   763 	pdev = tp->pci_dev;

   764 

   765 	if (tp->mmio_addr)

   766 		pci_iounmap (pdev, tp->mmio_addr);

   767 

   768 	/* it's ok to call this even if we have no regions to free */

   769 	pci_release_regions (pdev);

   770 

   771 	free_netdev(dev);

   772 	pci_set_drvdata (pdev, NULL);

   773 }

   774 

   775 

   776 static void rtl8139_chip_reset (void __iomem *ioaddr)

   777 {

   778 	int i;

   779 

   780 	/* Soft reset the chip. */

   781 	RTL_W8 (ChipCmd, CmdReset);

   782 

   783 	/* Check that the chip has finished the reset. */

   784 	for (i = 1000; i > 0; i--) {

   785 		barrier();

   786 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   787 			break;

   788 		udelay (10);

   789 	}

   790 }

   791 

   792 

   793 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)

   794 {

   795 	void __iomem *ioaddr;

   796 	struct net_device *dev;

   797 	struct rtl8139_private *tp;

   798 	u8 tmp8;

   799 	int rc, disable_dev_on_err = 0;

   800 	unsigned int i;

   801 	unsigned long pio_start, pio_end, pio_flags, pio_len;

   802 	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;

   803 	u32 version;

   804 

   805 	assert (pdev != NULL);

   806 

   807 	/* dev and priv zeroed in alloc_etherdev */

   808 	dev = alloc_etherdev (sizeof (*tp));

   809 	if (dev == NULL) {

   810 		dev_err(&pdev->dev, "Unable to alloc new net device\n");

   811 		return ERR_PTR(-ENOMEM);

   812 	}

   813 	SET_NETDEV_DEV(dev, &pdev->dev);

   814 

   815 	tp = netdev_priv(dev);

   816 	tp->pci_dev = pdev;

   817 

   818 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   819 	rc = pci_enable_device (pdev);

   820 	if (rc)

   821 		goto err_out;

   822 

   823 	pio_start = pci_resource_start (pdev, 0);

   824 	pio_end = pci_resource_end (pdev, 0);

   825 	pio_flags = pci_resource_flags (pdev, 0);

   826 	pio_len = pci_resource_len (pdev, 0);

   827 

   828 	mmio_start = pci_resource_start (pdev, 1);

   829 	mmio_end = pci_resource_end (pdev, 1);

   830 	mmio_flags = pci_resource_flags (pdev, 1);

   831 	mmio_len = pci_resource_len (pdev, 1);

   832 

   833 	/* set this immediately, we need to know before

   834 	 * we talk to the chip directly */

   835 	DPRINTK("PIO region size == 0x%02X\n", pio_len);

   836 	DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);

   837 

   838 retry:

   839 	if (use_io) {

   840 		/* make sure PCI base addr 0 is PIO */

   841 		if (!(pio_flags & IORESOURCE_IO)) {

   842 			dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");

   843 			rc = -ENODEV;

   844 			goto err_out;

   845 		}

   846 		/* check for weird/broken PCI region reporting */

   847 		if (pio_len < RTL_MIN_IO_SIZE) {

   848 			dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");

   849 			rc = -ENODEV;

   850 			goto err_out;

   851 		}

   852 	} else {

   853 		/* make sure PCI base addr 1 is MMIO */

   854 		if (!(mmio_flags & IORESOURCE_MEM)) {

   855 			dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");

   856 			rc = -ENODEV;

   857 			goto err_out;

   858 		}

   859 		if (mmio_len < RTL_MIN_IO_SIZE) {

   860 			dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");

   861 			rc = -ENODEV;

   862 			goto err_out;

   863 		}

   864 	}

   865 

   866 	rc = pci_request_regions (pdev, DRV_NAME);

   867 	if (rc)

   868 		goto err_out;

   869 	disable_dev_on_err = 1;

   870 

   871 	/* enable PCI bus-mastering */

   872 	pci_set_master (pdev);

   873 

   874 	if (use_io) {

   875 		ioaddr = pci_iomap(pdev, 0, 0);

   876 		if (!ioaddr) {

   877 			dev_err(&pdev->dev, "cannot map PIO, aborting\n");

   878 			rc = -EIO;

   879 			goto err_out;

   880 		}

   881 		dev->base_addr = pio_start;

   882 		tp->regs_len = pio_len;

   883 	} else {

   884 		/* ioremap MMIO region */

   885 		ioaddr = pci_iomap(pdev, 1, 0);

   886 		if (ioaddr == NULL) {

   887 			dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");

   888 			pci_release_regions(pdev);

   889 			use_io = 1;

   890 			goto retry;

   891 		}

   892 		dev->base_addr = (long) ioaddr;

   893 		tp->regs_len = mmio_len;

   894 	}

   895 	tp->mmio_addr = ioaddr;

   896 

   897 	/* Bring old chips out of low-power mode. */

   898 	RTL_W8 (HltClk, 'R');

   899 

   900 	/* check for missing/broken hardware */

   901 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   902 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");

   903 		rc = -EIO;

   904 		goto err_out;

   905 	}

   906 

   907 	/* identify chip attached to board */

   908 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   909 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   910 		if (version == rtl_chip_info[i].version) {

   911 			tp->chipset = i;

   912 			goto match;

   913 		}

   914 

   915 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   916 	dev_printk (KERN_DEBUG, &pdev->dev,

   917 		    "unknown chip version, assuming RTL-8139\n");

   918 	dev_printk (KERN_DEBUG, &pdev->dev,

   919 		    "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));

   920 	tp->chipset = 0;

   921 

   922 match:

   923 	DPRINTK ("chipset id (%d) == index %d, '%s'\n",

   924 		 version, i, rtl_chip_info[i].name);

   925 

   926 	if (tp->chipset >= CH_8139B) {

   927 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   928 		DPRINTK("PCI PM wakeup\n");

   929 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   930 		    (tmp8 & LWAKE))

   931 			new_tmp8 &= ~LWAKE;

   932 		new_tmp8 |= Cfg1_PM_Enable;

   933 		if (new_tmp8 != tmp8) {

   934 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   935 			RTL_W8 (Config1, tmp8);

   936 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   937 		}

   938 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   939 			tmp8 = RTL_R8 (Config4);

   940 			if (tmp8 & LWPTN) {

   941 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   942 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   943 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   944 			}

   945 		}

   946 	} else {

   947 		DPRINTK("Old chip wakeup\n");

   948 		tmp8 = RTL_R8 (Config1);

   949 		tmp8 &= ~(SLEEP | PWRDN);

   950 		RTL_W8 (Config1, tmp8);

   951 	}

   952 

   953 	rtl8139_chip_reset (ioaddr);

   954 

   955 	return dev;

   956 

   957 err_out:

   958 	__rtl8139_cleanup_dev (dev);

   959 	if (disable_dev_on_err)

   960 		pci_disable_device (pdev);

   961 	return ERR_PTR(rc);

   962 }

   963 

   964 static const struct net_device_ops rtl8139_netdev_ops = {

   965 	.ndo_open		= rtl8139_open,

   966 	.ndo_stop		= rtl8139_close,

   967 	.ndo_get_stats		= rtl8139_get_stats,

   968 	.ndo_validate_addr	= eth_validate_addr,

   969 	.ndo_set_mac_address 	= eth_mac_addr,

   970 	.ndo_start_xmit		= rtl8139_start_xmit,

   971 	.ndo_set_multicast_list	= rtl8139_set_rx_mode,

   972 	.ndo_do_ioctl		= netdev_ioctl,

   973 	.ndo_tx_timeout		= rtl8139_tx_timeout,

   974 #ifdef CONFIG_NET_POLL_CONTROLLER

   975 	.ndo_poll_controller	= rtl8139_poll_controller,

   976 #endif

   977 };

   978 

   979 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

   980 				       const struct pci_device_id *ent)

   981 {

   982 	struct net_device *dev = NULL;

   983 	struct rtl8139_private *tp;

   984 	int i, addr_len, option;

   985 	void __iomem *ioaddr;

   986 	static int board_idx = -1;

   987 

   988 	assert (pdev != NULL);

   989 	assert (ent != NULL);

   990 

   991 	board_idx++;

   992 

   993 	/* when we're built into the kernel, the driver version message

   994 	 * is only printed if at least one 8139 board has been found

   995 	 */

   996 #ifndef MODULE

   997 	{

   998 		static int printed_version;

   999 		if (!printed_version++)

  1000 			printk (KERN_INFO RTL8139_DRIVER_NAME "\n");

  1001 	}

  1002 #endif

  1003 

  1004 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1005 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {

  1006 		dev_info(&pdev->dev,

  1007 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",

  1008 		       	   pdev->vendor, pdev->device, pdev->revision);

  1009 		return -ENODEV;

  1010 	}

  1011 

  1012 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1013 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&

  1014 	    pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&

  1015 	    pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {

  1016 		printk(KERN_INFO "8139too: OQO Model 2 detected. Forcing PIO\n");

  1017 		use_io = 1;

  1018 	}

  1019 

  1020 	dev = rtl8139_init_board (pdev);

  1021 	if (IS_ERR(dev))

  1022 		return PTR_ERR(dev);

  1023 

  1024 	assert (dev != NULL);

  1025 	tp = netdev_priv(dev);

  1026 	tp->dev = dev;

  1027 

  1028 	ioaddr = tp->mmio_addr;

  1029 	assert (ioaddr != NULL);

  1030 

  1031 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1032 	for (i = 0; i < 3; i++)

  1033 		((__le16 *) (dev->dev_addr))[i] =

  1034 		    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));

  1035 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

  1036 

  1037 	/* The Rtl8139-specific entries in the device structure. */

  1038 	dev->netdev_ops = &rtl8139_netdev_ops;

  1039 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1040 	dev->watchdog_timeo = TX_TIMEOUT;

  1041 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);

  1042 

  1043 	/* note: the hardware is not capable of sg/csum/highdma, however

  1044 	 * through the use of skb_copy_and_csum_dev we enable these

  1045 	 * features

  1046 	 */

  1047 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1048 

  1049 	dev->irq = pdev->irq;

  1050 

  1051 	/* tp zeroed and aligned in alloc_etherdev */

  1052 	tp = netdev_priv(dev);

  1053 

  1054 	/* note: tp->chipset set in rtl8139_init_board */

  1055 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1056 	tp->mmio_addr = ioaddr;

  1057 	tp->msg_enable =

  1058 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1059 	spin_lock_init (&tp->lock);

  1060 	spin_lock_init (&tp->rx_lock);

  1061 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);

  1062 	tp->mii.dev = dev;

  1063 	tp->mii.mdio_read = mdio_read;

  1064 	tp->mii.mdio_write = mdio_write;

  1065 	tp->mii.phy_id_mask = 0x3f;

  1066 	tp->mii.reg_num_mask = 0x1f;

  1067 

  1068 	/* dev is fully set up and ready to use now */

  1069     

  1070 	// offer device to EtherCAT master module

  1071 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);

  1072 

  1073 	if (!tp->ecdev) {

  1074 		DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);

  1075 		i = register_netdev (dev);

  1076 		if (i) goto err_out;

  1077 	}

  1078 

  1079 	pci_set_drvdata (pdev, dev);

  1080 

  1081 	printk (KERN_INFO "%s: %s at 0x%lx, "

  1082 		"%pM, IRQ %d\n",

  1083 		dev->name,

  1084 		board_info[ent->driver_data].name,

  1085 		dev->base_addr,

  1086 		dev->dev_addr,

  1087 		dev->irq);

  1088 

  1089 	printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",

  1090 		dev->name, rtl_chip_info[tp->chipset].name);

  1091 

  1092 	/* Find the connected MII xcvrs.

  1093 	   Doing this in open() would allow detecting external xcvrs later, but

  1094 	   takes too much time. */

  1095 #ifdef CONFIG_8139TOO_8129

  1096 	if (tp->drv_flags & HAS_MII_XCVR) {

  1097 		int phy, phy_idx = 0;

  1098 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1099 			int mii_status = mdio_read(dev, phy, 1);

  1100 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1101 				u16 advertising = mdio_read(dev, phy, 4);

  1102 				tp->phys[phy_idx++] = phy;

  1103 				printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "

  1104 					   "advertising %4.4x.\n",

  1105 					   dev->name, phy, mii_status, advertising);

  1106 			}

  1107 		}

  1108 		if (phy_idx == 0) {

  1109 			printk(KERN_INFO "%s: No MII transceivers found!  Assuming SYM "

  1110 				   "transceiver.\n",

  1111 				   dev->name);

  1112 			tp->phys[0] = 32;

  1113 		}

  1114 	} else

  1115 #endif

  1116 		tp->phys[0] = 32;

  1117 	tp->mii.phy_id = tp->phys[0];

  1118 

  1119 	/* The lower four bits are the media type. */

  1120 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];

  1121 	if (option > 0) {

  1122 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;

  1123 		tp->default_port = option & 0xFF;

  1124 		if (tp->default_port)

  1125 			tp->mii.force_media = 1;

  1126 	}

  1127 	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)

  1128 		tp->mii.full_duplex = full_duplex[board_idx];

  1129 	if (tp->mii.full_duplex) {

  1130 		printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);

  1131 		/* Changing the MII-advertised media because might prevent

  1132 		   re-connection. */

  1133 		tp->mii.force_media = 1;

  1134 	}

  1135 	if (tp->default_port) {