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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2009 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 #ifndef _E1000_DEFINES_H_ |
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30 #define _E1000_DEFINES_H_ |
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31 |
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32 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ |
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33 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ |
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34 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ |
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35 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ |
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36 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ |
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37 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ |
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38 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ |
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39 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ |
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40 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ |
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41 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ |
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42 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ |
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43 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ |
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44 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ |
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45 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ |
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46 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ |
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47 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ |
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48 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ |
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49 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ |
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50 |
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51 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ |
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52 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 |
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53 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 |
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54 |
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55 /* Definitions for power management and wakeup registers */ |
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56 /* Wake Up Control */ |
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57 #define E1000_WUC_APME 0x00000001 /* APM Enable */ |
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58 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ |
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59 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ |
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60 |
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61 /* Wake Up Filter Control */ |
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62 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ |
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63 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
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64 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
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65 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ |
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66 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
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67 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ |
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68 |
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69 /* Wake Up Status */ |
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70 #define E1000_WUS_LNKC E1000_WUFC_LNKC |
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71 #define E1000_WUS_MAG E1000_WUFC_MAG |
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72 #define E1000_WUS_EX E1000_WUFC_EX |
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73 #define E1000_WUS_MC E1000_WUFC_MC |
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74 #define E1000_WUS_BC E1000_WUFC_BC |
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75 |
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76 /* Extended Device Control */ |
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77 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ |
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78 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ |
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79 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ |
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80 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ |
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81 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ |
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82 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
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83 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 |
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84 #define E1000_CTRL_EXT_EIAME 0x01000000 |
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85 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ |
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86 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ |
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87 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ |
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88 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ |
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89 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 |
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90 |
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91 /* Receive Descriptor bit definitions */ |
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92 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
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93 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ |
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94 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ |
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95 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
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96 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
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97 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
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98 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ |
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99 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ |
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100 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ |
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101 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ |
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102 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ |
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103 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ |
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104 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ |
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105 |
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106 #define E1000_RXDEXT_STATERR_CE 0x01000000 |
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107 #define E1000_RXDEXT_STATERR_SE 0x02000000 |
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108 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 |
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109 #define E1000_RXDEXT_STATERR_CXE 0x10000000 |
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110 #define E1000_RXDEXT_STATERR_RXE 0x80000000 |
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111 |
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112 /* mask to determine if packets should be dropped due to frame errors */ |
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113 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ |
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114 E1000_RXD_ERR_CE | \ |
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115 E1000_RXD_ERR_SE | \ |
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116 E1000_RXD_ERR_SEQ | \ |
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117 E1000_RXD_ERR_CXE | \ |
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118 E1000_RXD_ERR_RXE) |
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119 |
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120 /* Same mask, but for extended and packet split descriptors */ |
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121 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ |
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122 E1000_RXDEXT_STATERR_CE | \ |
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123 E1000_RXDEXT_STATERR_SE | \ |
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124 E1000_RXDEXT_STATERR_SEQ | \ |
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125 E1000_RXDEXT_STATERR_CXE | \ |
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126 E1000_RXDEXT_STATERR_RXE) |
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127 |
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128 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 |
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129 |
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130 /* Management Control */ |
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131 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ |
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132 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ |
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133 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ |
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134 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ |
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135 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ |
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136 /* Enable MAC address filtering */ |
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137 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 |
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138 /* Enable MNG packets to host memory */ |
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139 #define E1000_MANC_EN_MNG2HOST 0x00200000 |
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140 |
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141 /* Receive Control */ |
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142 #define E1000_RCTL_EN 0x00000002 /* enable */ |
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143 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ |
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144 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ |
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145 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ |
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146 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ |
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147 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ |
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148 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ |
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149 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ |
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150 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ |
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151 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ |
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152 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ |
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153 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ |
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154 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ |
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155 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ |
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156 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ |
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157 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ |
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158 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ |
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159 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ |
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160 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ |
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161 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ |
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162 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ |
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163 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ |
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164 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ |
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165 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ |
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166 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ |
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167 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ |
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168 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ |
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169 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ |
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170 |
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171 /* |
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172 * Use byte values for the following shift parameters |
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173 * Usage: |
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174 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & |
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175 * E1000_PSRCTL_BSIZE0_MASK) | |
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176 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & |
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177 * E1000_PSRCTL_BSIZE1_MASK) | |
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178 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & |
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179 * E1000_PSRCTL_BSIZE2_MASK) | |
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180 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; |
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181 * E1000_PSRCTL_BSIZE3_MASK)) |
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182 * where value0 = [128..16256], default=256 |
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183 * value1 = [1024..64512], default=4096 |
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184 * value2 = [0..64512], default=4096 |
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185 * value3 = [0..64512], default=0 |
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186 */ |
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187 |
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188 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F |
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189 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 |
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190 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 |
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191 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 |
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192 |
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193 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ |
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194 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ |
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195 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ |
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196 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ |
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197 |
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198 /* SWFW_SYNC Definitions */ |
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199 #define E1000_SWFW_EEP_SM 0x1 |
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200 #define E1000_SWFW_PHY0_SM 0x2 |
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201 #define E1000_SWFW_PHY1_SM 0x4 |
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202 #define E1000_SWFW_CSR_SM 0x8 |
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203 |
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204 /* Device Control */ |
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205 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ |
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206 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ |
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207 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ |
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208 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ |
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209 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ |
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210 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ |
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211 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ |
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212 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ |
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213 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ |
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214 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ |
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215 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ |
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216 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ |
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217 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ |
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218 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ |
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219 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ |
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220 #define E1000_CTRL_RST 0x04000000 /* Global reset */ |
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221 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ |
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222 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ |
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223 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ |
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224 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ |
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225 |
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226 /* |
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227 * Bit definitions for the Management Data IO (MDIO) and Management Data |
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228 * Clock (MDC) pins in the Device Control Register. |
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229 */ |
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230 |
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231 /* Device Status */ |
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232 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ |
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233 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ |
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234 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ |
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235 #define E1000_STATUS_FUNC_SHIFT 2 |
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236 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ |
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237 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ |
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238 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ |
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239 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ |
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240 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ |
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241 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ |
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242 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ |
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243 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ |
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244 |
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245 /* Constants used to interpret the masked PCI-X bus speed. */ |
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246 |
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247 #define HALF_DUPLEX 1 |
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248 #define FULL_DUPLEX 2 |
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249 |
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250 |
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251 #define ADVERTISE_10_HALF 0x0001 |
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252 #define ADVERTISE_10_FULL 0x0002 |
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253 #define ADVERTISE_100_HALF 0x0004 |
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254 #define ADVERTISE_100_FULL 0x0008 |
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255 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ |
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256 #define ADVERTISE_1000_FULL 0x0020 |
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257 |
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258 /* 1000/H is not supported, nor spec-compliant. */ |
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259 #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ |
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260 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ |
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261 ADVERTISE_1000_FULL) |
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262 #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ |
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263 ADVERTISE_100_HALF | ADVERTISE_100_FULL) |
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264 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) |
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265 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) |
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266 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) |
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267 |
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268 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX |
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269 |
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270 /* LED Control */ |
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271 #define E1000_PHY_LED0_MODE_MASK 0x00000007 |
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272 #define E1000_PHY_LED0_IVRT 0x00000008 |
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273 #define E1000_PHY_LED0_MASK 0x0000001F |
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274 |
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275 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F |
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276 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 |
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277 #define E1000_LEDCTL_LED0_IVRT 0x00000040 |
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278 #define E1000_LEDCTL_LED0_BLINK 0x00000080 |
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279 |
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280 #define E1000_LEDCTL_MODE_LINK_UP 0x2 |
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281 #define E1000_LEDCTL_MODE_LED_ON 0xE |
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282 #define E1000_LEDCTL_MODE_LED_OFF 0xF |
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283 |
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284 /* Transmit Descriptor bit definitions */ |
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285 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ |
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286 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ |
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287 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ |
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288 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ |
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289 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ |
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290 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ |
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291 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ |
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292 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ |
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293 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ |
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294 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ |
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295 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ |
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296 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ |
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297 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ |
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298 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ |
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299 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ |
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300 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ |
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301 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ |
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302 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ |
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303 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ |
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304 |
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305 /* Transmit Control */ |
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306 #define E1000_TCTL_EN 0x00000002 /* enable Tx */ |
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307 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ |
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308 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ |
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309 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ |
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310 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ |
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311 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ |
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312 |
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313 /* Transmit Arbitration Count */ |
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314 |
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315 /* SerDes Control */ |
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316 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 |
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317 |
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318 /* Receive Checksum Control */ |
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319 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ |
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320 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ |
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321 |
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322 /* Header split receive */ |
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323 #define E1000_RFCTL_ACK_DIS 0x00001000 |
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324 #define E1000_RFCTL_EXTEN 0x00008000 |
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325 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 |
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326 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 |
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327 |
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328 /* Collision related configuration parameters */ |
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329 #define E1000_COLLISION_THRESHOLD 15 |
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330 #define E1000_CT_SHIFT 4 |
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331 #define E1000_COLLISION_DISTANCE 63 |
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332 #define E1000_COLD_SHIFT 12 |
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333 |
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334 /* Default values for the transmit IPG register */ |
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335 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 |
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336 |
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337 #define E1000_TIPG_IPGT_MASK 0x000003FF |
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338 |
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339 #define DEFAULT_82543_TIPG_IPGR1 8 |
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340 #define E1000_TIPG_IPGR1_SHIFT 10 |
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341 |
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342 #define DEFAULT_82543_TIPG_IPGR2 6 |
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343 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 |
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344 #define E1000_TIPG_IPGR2_SHIFT 20 |
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345 |
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346 #define MAX_JUMBO_FRAME_SIZE 0x3F00 |
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347 |
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348 /* Extended Configuration Control and Size */ |
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349 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 |
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350 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 |
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351 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 |
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352 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 |
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353 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 |
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354 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 |
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355 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 |
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356 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 |
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357 |
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358 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 |
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359 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 |
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360 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 |
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361 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 |
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362 |
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363 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 |
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364 |
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365 /* PBA constants */ |
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366 #define E1000_PBA_8K 0x0008 /* 8KB */ |
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367 #define E1000_PBA_16K 0x0010 /* 16KB */ |
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368 |
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369 #define E1000_PBS_16K E1000_PBA_16K |
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370 |
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371 #define IFS_MAX 80 |
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372 #define IFS_MIN 40 |
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373 #define IFS_RATIO 4 |
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374 #define IFS_STEP 10 |
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375 #define MIN_NUM_XMITS 1000 |
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376 |
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377 /* SW Semaphore Register */ |
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378 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ |
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379 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ |
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380 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ |
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381 |
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382 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ |
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383 |
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384 /* Interrupt Cause Read */ |
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385 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ |
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386 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ |
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387 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ |
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388 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ |
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389 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ |
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390 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ |
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391 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ |
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392 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ |
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393 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ |
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394 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ |
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395 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ |
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396 |
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397 /* PBA ECC Register */ |
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398 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ |
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399 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ |
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400 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ |
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401 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ |
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402 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ |
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403 |
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404 /* |
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405 * This defines the bits that are set in the Interrupt Mask |
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406 * Set/Read Register. Each bit is documented below: |
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407 * o RXT0 = Receiver Timer Interrupt (ring 0) |
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408 * o TXDW = Transmit Descriptor Written Back |
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409 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) |
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410 * o RXSEQ = Receive Sequence Error |
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411 * o LSC = Link Status Change |
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412 */ |
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413 #define IMS_ENABLE_MASK ( \ |
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414 E1000_IMS_RXT0 | \ |
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415 E1000_IMS_TXDW | \ |
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416 E1000_IMS_RXDMT0 | \ |
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417 E1000_IMS_RXSEQ | \ |
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418 E1000_IMS_LSC) |
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419 |
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420 /* Interrupt Mask Set */ |
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421 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
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422 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ |
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423 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ |
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424 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ |
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425 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ |
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426 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ |
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427 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ |
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428 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ |
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429 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ |
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430 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ |
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431 |
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432 /* Interrupt Cause Set */ |
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433 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ |
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434 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ |
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435 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ |
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436 |
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437 /* Transmit Descriptor Control */ |
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438 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ |
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439 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ |
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440 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ |
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441 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ |
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442 /* Enable the counting of desc. still to be processed. */ |
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443 #define E1000_TXDCTL_COUNT_DESC 0x00400000 |
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444 |
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445 /* Flow Control Constants */ |
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446 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 |
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447 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 |
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448 #define FLOW_CONTROL_TYPE 0x8808 |
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449 |
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450 /* 802.1q VLAN Packet Size */ |
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451 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ |
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452 |
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453 /* Receive Address */ |
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454 /* |
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455 * Number of high/low register pairs in the RAR. The RAR (Receive Address |
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456 * Registers) holds the directed and multicast addresses that we monitor. |
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457 * Technically, we have 16 spots. However, we reserve one of these spots |
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458 * (RAR[15]) for our directed address used by controllers with |
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459 * manageability enabled, allowing us room for 15 multicast addresses. |
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460 */ |
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461 #define E1000_RAR_ENTRIES 15 |
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462 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ |
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463 |
|
464 /* Error Codes */ |
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465 #define E1000_ERR_NVM 1 |
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466 #define E1000_ERR_PHY 2 |
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467 #define E1000_ERR_CONFIG 3 |
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468 #define E1000_ERR_PARAM 4 |
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469 #define E1000_ERR_MAC_INIT 5 |
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470 #define E1000_ERR_PHY_TYPE 6 |
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471 #define E1000_ERR_RESET 9 |
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472 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 |
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473 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 |
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474 #define E1000_BLK_PHY_RESET 12 |
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475 #define E1000_ERR_SWFW_SYNC 13 |
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476 #define E1000_NOT_IMPLEMENTED 14 |
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477 |
|
478 /* Loop limit on how long we wait for auto-negotiation to complete */ |
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479 #define FIBER_LINK_UP_LIMIT 50 |
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480 #define COPPER_LINK_UP_LIMIT 10 |
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481 #define PHY_AUTO_NEG_LIMIT 45 |
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482 #define PHY_FORCE_LIMIT 20 |
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483 /* Number of 100 microseconds we wait for PCI Express master disable */ |
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484 #define MASTER_DISABLE_TIMEOUT 800 |
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485 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ |
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486 #define PHY_CFG_TIMEOUT 100 |
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487 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ |
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488 #define MDIO_OWNERSHIP_TIMEOUT 10 |
|
489 /* Number of milliseconds for NVM auto read done after MAC reset. */ |
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490 #define AUTO_READ_DONE_TIMEOUT 10 |
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491 |
|
492 /* Flow Control */ |
|
493 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ |
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494 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ |
|
495 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ |
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496 |
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497 /* Transmit Configuration Word */ |
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498 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ |
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499 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ |
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500 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ |
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501 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ |
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502 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ |
|
503 |
|
504 /* Receive Configuration Word */ |
|
505 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ |
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506 #define E1000_RXCW_C 0x20000000 /* Receive config */ |
|
507 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ |
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508 |
|
509 /* PCI Express Control */ |
|
510 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 |
|
511 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 |
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512 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 |
|
513 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 |
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514 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 |
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515 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 |
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516 |
|
517 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ |
|
518 E1000_GCR_RXDSCW_NO_SNOOP | \ |
|
519 E1000_GCR_RXDSCR_NO_SNOOP | \ |
|
520 E1000_GCR_TXD_NO_SNOOP | \ |
|
521 E1000_GCR_TXDSCW_NO_SNOOP | \ |
|
522 E1000_GCR_TXDSCR_NO_SNOOP) |
|
523 |
|
524 /* PHY Control Register */ |
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525 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
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526 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
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527 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ |
|
528 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
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529 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
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530 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
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531 #define MII_CR_SPEED_1000 0x0040 |
|
532 #define MII_CR_SPEED_100 0x2000 |
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533 #define MII_CR_SPEED_10 0x0000 |
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534 |
|
535 /* PHY Status Register */ |
|
536 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ |
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537 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ |
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538 |
|
539 /* Autoneg Advertisement Register */ |
|
540 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ |
|
541 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ |
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542 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ |
|
543 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ |
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544 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ |
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545 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ |
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546 |
|
547 /* Link Partner Ability Register (Base Page) */ |
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548 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ |
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549 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ |
|
550 |
|
551 /* Autoneg Expansion Register */ |
|
552 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ |
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553 |
|
554 /* 1000BASE-T Control Register */ |
|
555 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ |
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556 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ |
|
557 /* 0=DTE device */ |
|
558 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ |
|
559 /* 0=Configure PHY as Slave */ |
|
560 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ |
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561 /* 0=Automatic Master/Slave config */ |
|
562 |
|
563 /* 1000BASE-T Status Register */ |
|
564 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ |
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565 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ |
|
566 |
|
567 |
|
568 /* PHY 1000 MII Register/Bit Definitions */ |
|
569 /* PHY Registers defined by IEEE */ |
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570 #define PHY_CONTROL 0x00 /* Control Register */ |
|
571 #define PHY_STATUS 0x01 /* Status Register */ |
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572 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ |
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573 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ |
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574 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ |
|
575 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ |
|
576 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ |
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577 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ |
|
578 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ |
|
579 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ |
|
580 |
|
581 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ |
|
582 |
|
583 /* NVM Control */ |
|
584 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ |
|
585 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ |
|
586 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ |
|
587 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ |
|
588 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ |
|
589 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ |
|
590 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ |
|
591 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ |
|
592 /* NVM Addressing bits based on type (0-small, 1-large) */ |
|
593 #define E1000_EECD_ADDR_BITS 0x00000400 |
|
594 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ |
|
595 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ |
|
596 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ |
|
597 #define E1000_EECD_SIZE_EX_SHIFT 11 |
|
598 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ |
|
599 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ |
|
600 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ |
|
601 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) |
|
602 |
|
603 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ |
|
604 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ |
|
605 #define E1000_NVM_RW_REG_START 1 /* Start operation */ |
|
606 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ |
|
607 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ |
|
608 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ |
|
609 #define E1000_FLASH_UPDATES 2000 |
|
610 |
|
611 /* NVM Word Offsets */ |
|
612 #define NVM_ID_LED_SETTINGS 0x0004 |
|
613 #define NVM_INIT_CONTROL2_REG 0x000F |
|
614 #define NVM_INIT_CONTROL3_PORT_B 0x0014 |
|
615 #define NVM_INIT_3GIO_3 0x001A |
|
616 #define NVM_INIT_CONTROL3_PORT_A 0x0024 |
|
617 #define NVM_CFG 0x0012 |
|
618 #define NVM_ALT_MAC_ADDR_PTR 0x0037 |
|
619 #define NVM_CHECKSUM_REG 0x003F |
|
620 |
|
621 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ |
|
622 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ |
|
623 |
|
624 /* Mask bits for fields in Word 0x0f of the NVM */ |
|
625 #define NVM_WORD0F_PAUSE_MASK 0x3000 |
|
626 #define NVM_WORD0F_PAUSE 0x1000 |
|
627 #define NVM_WORD0F_ASM_DIR 0x2000 |
|
628 |
|
629 /* Mask bits for fields in Word 0x1a of the NVM */ |
|
630 #define NVM_WORD1A_ASPM_MASK 0x000C |
|
631 |
|
632 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ |
|
633 #define NVM_SUM 0xBABA |
|
634 |
|
635 /* PBA (printed board assembly) number words */ |
|
636 #define NVM_PBA_OFFSET_0 8 |
|
637 #define NVM_PBA_OFFSET_1 9 |
|
638 |
|
639 #define NVM_WORD_SIZE_BASE_SHIFT 6 |
|
640 |
|
641 /* NVM Commands - SPI */ |
|
642 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ |
|
643 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ |
|
644 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ |
|
645 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ |
|
646 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ |
|
647 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ |
|
648 |
|
649 /* SPI NVM Status Register */ |
|
650 #define NVM_STATUS_RDY_SPI 0x01 |
|
651 |
|
652 /* Word definitions for ID LED Settings */ |
|
653 #define ID_LED_RESERVED_0000 0x0000 |
|
654 #define ID_LED_RESERVED_FFFF 0xFFFF |
|
655 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ |
|
656 (ID_LED_OFF1_OFF2 << 8) | \ |
|
657 (ID_LED_DEF1_DEF2 << 4) | \ |
|
658 (ID_LED_DEF1_DEF2)) |
|
659 #define ID_LED_DEF1_DEF2 0x1 |
|
660 #define ID_LED_DEF1_ON2 0x2 |
|
661 #define ID_LED_DEF1_OFF2 0x3 |
|
662 #define ID_LED_ON1_DEF2 0x4 |
|
663 #define ID_LED_ON1_ON2 0x5 |
|
664 #define ID_LED_ON1_OFF2 0x6 |
|
665 #define ID_LED_OFF1_DEF2 0x7 |
|
666 #define ID_LED_OFF1_ON2 0x8 |
|
667 #define ID_LED_OFF1_OFF2 0x9 |
|
668 |
|
669 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF |
|
670 #define IGP_ACTIVITY_LED_ENABLE 0x0300 |
|
671 #define IGP_LED3_MODE 0x07000000 |
|
672 |
|
673 /* PCI/PCI-X/PCI-EX Config space */ |
|
674 #define PCI_HEADER_TYPE_REGISTER 0x0E |
|
675 #define PCIE_LINK_STATUS 0x12 |
|
676 |
|
677 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 |
|
678 #define PCIE_LINK_WIDTH_MASK 0x3F0 |
|
679 #define PCIE_LINK_WIDTH_SHIFT 4 |
|
680 |
|
681 #define PHY_REVISION_MASK 0xFFFFFFF0 |
|
682 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ |
|
683 #define MAX_PHY_MULTI_PAGE_REG 0xF |
|
684 |
|
685 /* Bit definitions for valid PHY IDs. */ |
|
686 /* |
|
687 * I = Integrated |
|
688 * E = External |
|
689 */ |
|
690 #define M88E1000_E_PHY_ID 0x01410C50 |
|
691 #define M88E1000_I_PHY_ID 0x01410C30 |
|
692 #define M88E1011_I_PHY_ID 0x01410C20 |
|
693 #define IGP01E1000_I_PHY_ID 0x02A80380 |
|
694 #define M88E1111_I_PHY_ID 0x01410CC0 |
|
695 #define GG82563_E_PHY_ID 0x01410CA0 |
|
696 #define IGP03E1000_E_PHY_ID 0x02A80390 |
|
697 #define IFE_E_PHY_ID 0x02A80330 |
|
698 #define IFE_PLUS_E_PHY_ID 0x02A80320 |
|
699 #define IFE_C_E_PHY_ID 0x02A80310 |
|
700 #define BME1000_E_PHY_ID 0x01410CB0 |
|
701 #define BME1000_E_PHY_ID_R2 0x01410CB1 |
|
702 #define I82577_E_PHY_ID 0x01540050 |
|
703 #define I82578_E_PHY_ID 0x004DD040 |
|
704 |
|
705 /* M88E1000 Specific Registers */ |
|
706 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ |
|
707 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ |
|
708 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ |
|
709 |
|
710 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ |
|
711 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ |
|
712 |
|
713 /* M88E1000 PHY Specific Control Register */ |
|
714 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ |
|
715 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ |
|
716 /* Manual MDI configuration */ |
|
717 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ |
|
718 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ |
|
719 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 |
|
720 /* Auto crossover enabled all speeds */ |
|
721 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 |
|
722 /* |
|
723 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold) |
|
724 * 0=Normal 10BASE-T Rx Threshold |
|
725 */ |
|
726 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ |
|
727 |
|
728 /* M88E1000 PHY Specific Status Register */ |
|
729 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ |
|
730 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ |
|
731 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ |
|
732 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ |
|
733 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 |
|
734 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ |
|
735 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ |
|
736 |
|
737 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 |
|
738 |
|
739 /* |
|
740 * Number of times we will attempt to autonegotiate before downshifting if we |
|
741 * are the master |
|
742 */ |
|
743 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 |
|
744 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 |
|
745 /* |
|
746 * Number of times we will attempt to autonegotiate before downshifting if we |
|
747 * are the slave |
|
748 */ |
|
749 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 |
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750 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 |
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751 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ |
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752 |
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753 /* M88EC018 Rev 2 specific DownShift settings */ |
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754 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 |
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755 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 |
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756 |
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757 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 |
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758 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C |
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759 |
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760 /* BME1000 PHY Specific Control Register */ |
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761 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ |
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762 |
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763 |
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764 #define PHY_PAGE_SHIFT 5 |
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765 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ |
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766 ((reg) & MAX_PHY_REG_ADDRESS)) |
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767 |
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768 /* |
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769 * Bits... |
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770 * 15-5: page |
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771 * 4-0: register offset |
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772 */ |
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773 #define GG82563_PAGE_SHIFT 5 |
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774 #define GG82563_REG(page, reg) \ |
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775 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) |
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776 #define GG82563_MIN_ALT_REG 30 |
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777 |
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778 /* GG82563 Specific Registers */ |
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779 #define GG82563_PHY_SPEC_CTRL \ |
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780 GG82563_REG(0, 16) /* PHY Specific Control */ |
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781 #define GG82563_PHY_PAGE_SELECT \ |
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782 GG82563_REG(0, 22) /* Page Select */ |
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783 #define GG82563_PHY_SPEC_CTRL_2 \ |
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784 GG82563_REG(0, 26) /* PHY Specific Control 2 */ |
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785 #define GG82563_PHY_PAGE_SELECT_ALT \ |
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786 GG82563_REG(0, 29) /* Alternate Page Select */ |
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787 |
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788 #define GG82563_PHY_MAC_SPEC_CTRL \ |
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789 GG82563_REG(2, 21) /* MAC Specific Control Register */ |
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790 |
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791 #define GG82563_PHY_DSP_DISTANCE \ |
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792 GG82563_REG(5, 26) /* DSP Distance */ |
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793 |
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794 /* Page 193 - Port Control Registers */ |
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795 #define GG82563_PHY_KMRN_MODE_CTRL \ |
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796 GG82563_REG(193, 16) /* Kumeran Mode Control */ |
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797 #define GG82563_PHY_PWR_MGMT_CTRL \ |
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798 GG82563_REG(193, 20) /* Power Management Control */ |
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799 |
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800 /* Page 194 - KMRN Registers */ |
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801 #define GG82563_PHY_INBAND_CTRL \ |
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802 GG82563_REG(194, 18) /* Inband Control */ |
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803 |
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804 /* MDI Control */ |
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805 #define E1000_MDIC_REG_SHIFT 16 |
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806 #define E1000_MDIC_PHY_SHIFT 21 |
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807 #define E1000_MDIC_OP_WRITE 0x04000000 |
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808 #define E1000_MDIC_OP_READ 0x08000000 |
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809 #define E1000_MDIC_READY 0x10000000 |
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810 #define E1000_MDIC_ERROR 0x40000000 |
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811 |
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812 /* SerDes Control */ |
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813 #define E1000_GEN_POLL_TIMEOUT 640 |
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814 |
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815 #endif /* _E1000_DEFINES_H_ */ |