master/fsm_slave_config.c
changeset 1458 bba02b6a4492
parent 1438 1d30b96bb04f
child 1471 2ec173081b7f
equal deleted inserted replaced
1457:ec3ad6641d65 1458:bba02b6a4492
  1041         if (!slave->base_dc_supported || !slave->has_dc_system_time) {
  1041         if (!slave->base_dc_supported || !slave->has_dc_system_time) {
  1042             EC_WARN("Slave %u seems not to support distributed clocks!\n",
  1042             EC_WARN("Slave %u seems not to support distributed clocks!\n",
  1043                     slave->ring_position);
  1043                     slave->ring_position);
  1044         }
  1044         }
  1045 
  1045 
       
  1046         if (slave->master->debug_level)
       
  1047             EC_DBG("Slave %u: Setting DC cycle times to %u / %u.\n",
       
  1048                     slave->ring_position,
       
  1049                     config->dc_sync[0].cycle_time,
       
  1050                     config->dc_sync[1].cycle_time);
       
  1051 
  1046         // set DC cycle times
  1052         // set DC cycle times
  1047         ec_datagram_fpwr(datagram, slave->station_address, 0x09A0, 8);
  1053         ec_datagram_fpwr(datagram, slave->station_address, 0x09A0, 8);
  1048         EC_WRITE_U32(datagram->data, config->dc_sync[0].cycle_time);
  1054         EC_WRITE_U32(datagram->data, config->dc_sync[0].cycle_time);
  1049         EC_WRITE_U32(datagram->data + 4, config->dc_sync[1].cycle_time);
  1055         EC_WRITE_U32(datagram->data + 4, config->dc_sync[1].cycle_time);
  1050         fsm->retries = EC_FSM_RETRIES;
  1056         fsm->retries = EC_FSM_RETRIES;
  1120                 EC_DBG("         start=%llu\n", start);
  1126                 EC_DBG("         start=%llu\n", start);
  1121             }
  1127             }
  1122             start_time = start;
  1128             start_time = start;
  1123         } else {
  1129         } else {
  1124             EC_WARN("No application time supplied. Cyclic start time will "
  1130             EC_WARN("No application time supplied. Cyclic start time will "
  1125                     "not be in phase for slave %u.", slave->ring_position);
  1131                     "not be in phase for slave %u.\n", slave->ring_position);
  1126         }
  1132         }
  1127     }
  1133     }
  1128 
  1134 
  1129     if (master->debug_level)
  1135     if (master->debug_level)
  1130         EC_DBG("Slave %u: Setting DC cyclic operation start time to %llu.\n",
  1136         EC_DBG("Slave %u: Setting DC cyclic operation start time to %llu.\n",
  1170         EC_ERR("Failed to set DC start time of slave %u: ",
  1176         EC_ERR("Failed to set DC start time of slave %u: ",
  1171                 slave->ring_position);
  1177                 slave->ring_position);
  1172         ec_datagram_print_wc_error(datagram);
  1178         ec_datagram_print_wc_error(datagram);
  1173         return;
  1179         return;
  1174     }
  1180     }
       
  1181 
       
  1182     if (slave->master->debug_level)
       
  1183         EC_DBG("Slave %u: Setting DC AssignActivate to 0x%04x.\n",
       
  1184                 slave->ring_position, config->dc_assign_activate);
  1175 
  1185 
  1176     // assign sync unit to EtherCAT or PDI
  1186     // assign sync unit to EtherCAT or PDI
  1177     ec_datagram_fpwr(datagram, slave->station_address, 0x0980, 2);
  1187     ec_datagram_fpwr(datagram, slave->station_address, 0x0980, 2);
  1178     EC_WRITE_U16(datagram->data, config->dc_assign_activate);
  1188     EC_WRITE_U16(datagram->data, config->dc_assign_activate);
  1179     fsm->retries = EC_FSM_RETRIES;
  1189     fsm->retries = EC_FSM_RETRIES;