devices/r8169-2.6.33-orig.c
changeset 2066 b544025bd696
parent 2053 cceb9aacf4a6
equal deleted inserted replaced
2065:4d8c9a441ef6 2066:b544025bd696
       
     1 /*
       
     2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
       
     3  *
       
     4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
       
     5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
       
     6  * Copyright (c) a lot of people too. Please respect their work.
       
     7  *
       
     8  * See MAINTAINERS file for support contact information.
       
     9  */
       
    10 
       
    11 #include <linux/module.h>
       
    12 #include <linux/moduleparam.h>
       
    13 #include <linux/pci.h>
       
    14 #include <linux/netdevice.h>
       
    15 #include <linux/etherdevice.h>
       
    16 #include <linux/delay.h>
       
    17 #include <linux/ethtool.h>
       
    18 #include <linux/mii.h>
       
    19 #include <linux/if_vlan.h>
       
    20 #include <linux/crc32.h>
       
    21 #include <linux/in.h>
       
    22 #include <linux/ip.h>
       
    23 #include <linux/tcp.h>
       
    24 #include <linux/init.h>
       
    25 #include <linux/dma-mapping.h>
       
    26 
       
    27 #include <asm/system.h>
       
    28 #include <asm/io.h>
       
    29 #include <asm/irq.h>
       
    30 
       
    31 #define RTL8169_VERSION "2.3LK-NAPI"
       
    32 #define MODULENAME "r8169"
       
    33 #define PFX MODULENAME ": "
       
    34 
       
    35 #ifdef RTL8169_DEBUG
       
    36 #define assert(expr) \
       
    37 	if (!(expr)) {					\
       
    38 		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
       
    39 		#expr,__FILE__,__func__,__LINE__);		\
       
    40 	}
       
    41 #define dprintk(fmt, args...) \
       
    42 	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
       
    43 #else
       
    44 #define assert(expr) do {} while (0)
       
    45 #define dprintk(fmt, args...)	do {} while (0)
       
    46 #endif /* RTL8169_DEBUG */
       
    47 
       
    48 #define R8169_MSG_DEFAULT \
       
    49 	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
       
    50 
       
    51 #define TX_BUFFS_AVAIL(tp) \
       
    52 	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
       
    53 
       
    54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
       
    55    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
       
    56 static const int multicast_filter_limit = 32;
       
    57 
       
    58 /* MAC address length */
       
    59 #define MAC_ADDR_LEN	6
       
    60 
       
    61 #define MAX_READ_REQUEST_SHIFT	12
       
    62 #define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */
       
    63 #define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
       
    64 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
       
    65 #define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */
       
    66 #define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */
       
    67 #define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */
       
    68 
       
    69 #define R8169_REGS_SIZE		256
       
    70 #define R8169_NAPI_WEIGHT	64
       
    71 #define NUM_TX_DESC	64	/* Number of Tx descriptor registers */
       
    72 #define NUM_RX_DESC	256	/* Number of Rx descriptor registers */
       
    73 #define RX_BUF_SIZE	1536	/* Rx Buffer size */
       
    74 #define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
       
    75 #define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))
       
    76 
       
    77 #define RTL8169_TX_TIMEOUT	(6*HZ)
       
    78 #define RTL8169_PHY_TIMEOUT	(10*HZ)
       
    79 
       
    80 #define RTL_EEPROM_SIG		cpu_to_le32(0x8129)
       
    81 #define RTL_EEPROM_SIG_MASK	cpu_to_le32(0xffff)
       
    82 #define RTL_EEPROM_SIG_ADDR	0x0000
       
    83 
       
    84 /* write/read MMIO register */
       
    85 #define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
       
    86 #define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
       
    87 #define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
       
    88 #define RTL_R8(reg)		readb (ioaddr + (reg))
       
    89 #define RTL_R16(reg)		readw (ioaddr + (reg))
       
    90 #define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))
       
    91 
       
    92 enum mac_version {
       
    93 	RTL_GIGA_MAC_NONE   = 0x00,
       
    94 	RTL_GIGA_MAC_VER_01 = 0x01, // 8169
       
    95 	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
       
    96 	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
       
    97 	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
       
    98 	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
       
    99 	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
       
   100 	RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
       
   101 	RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
       
   102 	RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
       
   103 	RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
       
   104 	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
       
   105 	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
       
   106 	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
       
   107 	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
       
   108 	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
       
   109 	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
       
   110 	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
       
   111 	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
       
   112 	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
       
   113 	RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
       
   114 	RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
       
   115 	RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
       
   116 	RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
       
   117 	RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
       
   118 	RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
       
   119 	RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
       
   120 	RTL_GIGA_MAC_VER_27 = 0x1b  // 8168DP
       
   121 };
       
   122 
       
   123 #define _R(NAME,MAC,MASK) \
       
   124 	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
       
   125 
       
   126 static const struct {
       
   127 	const char *name;
       
   128 	u8 mac_version;
       
   129 	u32 RxConfigMask;	/* Clears the bits supported by this chip */
       
   130 } rtl_chip_info[] = {
       
   131 	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
       
   132 	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
       
   133 	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
       
   134 	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
       
   135 	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
       
   136 	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
       
   137 	_R("RTL8102e",		RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
       
   138 	_R("RTL8102e",		RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
       
   139 	_R("RTL8102e",		RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
       
   140 	_R("RTL8101e",		RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
       
   141 	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
       
   142 	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
       
   143 	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
       
   144 	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
       
   145 	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
       
   146 	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
       
   147 	_R("RTL8101e",		RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
       
   148 	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
       
   149 	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
       
   150 	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
       
   151 	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
       
   152 	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
       
   153 	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
       
   154 	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
       
   155 	_R("RTL8168d/8111d",	RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
       
   156 	_R("RTL8168d/8111d",	RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
       
   157 	_R("RTL8168dp/8111dp",	RTL_GIGA_MAC_VER_27, 0xff7e1880)  // PCI-E
       
   158 };
       
   159 #undef _R
       
   160 
       
   161 enum cfg_version {
       
   162 	RTL_CFG_0 = 0x00,
       
   163 	RTL_CFG_1,
       
   164 	RTL_CFG_2
       
   165 };
       
   166 
       
   167 static void rtl_hw_start_8169(struct net_device *);
       
   168 static void rtl_hw_start_8168(struct net_device *);
       
   169 static void rtl_hw_start_8101(struct net_device *);
       
   170 
       
   171 static struct pci_device_id rtl8169_pci_tbl[] = {
       
   172 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },
       
   173 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },
       
   174 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },
       
   175 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },
       
   176 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },
       
   177 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },
       
   178 	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },
       
   179 	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },
       
   180 	{ PCI_VENDOR_ID_LINKSYS,		0x1032,
       
   181 		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
       
   182 	{ 0x0001,				0x8168,
       
   183 		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
       
   184 	{0,},
       
   185 };
       
   186 
       
   187 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
       
   188 
       
   189 /*
       
   190  * we set our copybreak very high so that we don't have
       
   191  * to allocate 16k frames all the time (see note in
       
   192  * rtl8169_open()
       
   193  */
       
   194 static int rx_copybreak = 16383;
       
   195 static int use_dac;
       
   196 static struct {
       
   197 	u32 msg_enable;
       
   198 } debug = { -1 };
       
   199 
       
   200 enum rtl_registers {
       
   201 	MAC0		= 0,	/* Ethernet hardware address. */
       
   202 	MAC4		= 4,
       
   203 	MAR0		= 8,	/* Multicast filter. */
       
   204 	CounterAddrLow		= 0x10,
       
   205 	CounterAddrHigh		= 0x14,
       
   206 	TxDescStartAddrLow	= 0x20,
       
   207 	TxDescStartAddrHigh	= 0x24,
       
   208 	TxHDescStartAddrLow	= 0x28,
       
   209 	TxHDescStartAddrHigh	= 0x2c,
       
   210 	FLASH		= 0x30,
       
   211 	ERSR		= 0x36,
       
   212 	ChipCmd		= 0x37,
       
   213 	TxPoll		= 0x38,
       
   214 	IntrMask	= 0x3c,
       
   215 	IntrStatus	= 0x3e,
       
   216 	TxConfig	= 0x40,
       
   217 	RxConfig	= 0x44,
       
   218 	RxMissed	= 0x4c,
       
   219 	Cfg9346		= 0x50,
       
   220 	Config0		= 0x51,
       
   221 	Config1		= 0x52,
       
   222 	Config2		= 0x53,
       
   223 	Config3		= 0x54,
       
   224 	Config4		= 0x55,
       
   225 	Config5		= 0x56,
       
   226 	MultiIntr	= 0x5c,
       
   227 	PHYAR		= 0x60,
       
   228 	PHYstatus	= 0x6c,
       
   229 	RxMaxSize	= 0xda,
       
   230 	CPlusCmd	= 0xe0,
       
   231 	IntrMitigate	= 0xe2,
       
   232 	RxDescAddrLow	= 0xe4,
       
   233 	RxDescAddrHigh	= 0xe8,
       
   234 	EarlyTxThres	= 0xec,
       
   235 	FuncEvent	= 0xf0,
       
   236 	FuncEventMask	= 0xf4,
       
   237 	FuncPresetState	= 0xf8,
       
   238 	FuncForceEvent	= 0xfc,
       
   239 };
       
   240 
       
   241 enum rtl8110_registers {
       
   242 	TBICSR			= 0x64,
       
   243 	TBI_ANAR		= 0x68,
       
   244 	TBI_LPAR		= 0x6a,
       
   245 };
       
   246 
       
   247 enum rtl8168_8101_registers {
       
   248 	CSIDR			= 0x64,
       
   249 	CSIAR			= 0x68,
       
   250 #define	CSIAR_FLAG			0x80000000
       
   251 #define	CSIAR_WRITE_CMD			0x80000000
       
   252 #define	CSIAR_BYTE_ENABLE		0x0f
       
   253 #define	CSIAR_BYTE_ENABLE_SHIFT		12
       
   254 #define	CSIAR_ADDR_MASK			0x0fff
       
   255 
       
   256 	EPHYAR			= 0x80,
       
   257 #define	EPHYAR_FLAG			0x80000000
       
   258 #define	EPHYAR_WRITE_CMD		0x80000000
       
   259 #define	EPHYAR_REG_MASK			0x1f
       
   260 #define	EPHYAR_REG_SHIFT		16
       
   261 #define	EPHYAR_DATA_MASK		0xffff
       
   262 	DBG_REG			= 0xd1,
       
   263 #define	FIX_NAK_1			(1 << 4)
       
   264 #define	FIX_NAK_2			(1 << 3)
       
   265 	EFUSEAR			= 0xdc,
       
   266 #define	EFUSEAR_FLAG			0x80000000
       
   267 #define	EFUSEAR_WRITE_CMD		0x80000000
       
   268 #define	EFUSEAR_READ_CMD		0x00000000
       
   269 #define	EFUSEAR_REG_MASK		0x03ff
       
   270 #define	EFUSEAR_REG_SHIFT		8
       
   271 #define	EFUSEAR_DATA_MASK		0xff
       
   272 };
       
   273 
       
   274 enum rtl_register_content {
       
   275 	/* InterruptStatusBits */
       
   276 	SYSErr		= 0x8000,
       
   277 	PCSTimeout	= 0x4000,
       
   278 	SWInt		= 0x0100,
       
   279 	TxDescUnavail	= 0x0080,
       
   280 	RxFIFOOver	= 0x0040,
       
   281 	LinkChg		= 0x0020,
       
   282 	RxOverflow	= 0x0010,
       
   283 	TxErr		= 0x0008,
       
   284 	TxOK		= 0x0004,
       
   285 	RxErr		= 0x0002,
       
   286 	RxOK		= 0x0001,
       
   287 
       
   288 	/* RxStatusDesc */
       
   289 	RxFOVF	= (1 << 23),
       
   290 	RxRWT	= (1 << 22),
       
   291 	RxRES	= (1 << 21),
       
   292 	RxRUNT	= (1 << 20),
       
   293 	RxCRC	= (1 << 19),
       
   294 
       
   295 	/* ChipCmdBits */
       
   296 	CmdReset	= 0x10,
       
   297 	CmdRxEnb	= 0x08,
       
   298 	CmdTxEnb	= 0x04,
       
   299 	RxBufEmpty	= 0x01,
       
   300 
       
   301 	/* TXPoll register p.5 */
       
   302 	HPQ		= 0x80,		/* Poll cmd on the high prio queue */
       
   303 	NPQ		= 0x40,		/* Poll cmd on the low prio queue */
       
   304 	FSWInt		= 0x01,		/* Forced software interrupt */
       
   305 
       
   306 	/* Cfg9346Bits */
       
   307 	Cfg9346_Lock	= 0x00,
       
   308 	Cfg9346_Unlock	= 0xc0,
       
   309 
       
   310 	/* rx_mode_bits */
       
   311 	AcceptErr	= 0x20,
       
   312 	AcceptRunt	= 0x10,
       
   313 	AcceptBroadcast	= 0x08,
       
   314 	AcceptMulticast	= 0x04,
       
   315 	AcceptMyPhys	= 0x02,
       
   316 	AcceptAllPhys	= 0x01,
       
   317 
       
   318 	/* RxConfigBits */
       
   319 	RxCfgFIFOShift	= 13,
       
   320 	RxCfgDMAShift	=  8,
       
   321 
       
   322 	/* TxConfigBits */
       
   323 	TxInterFrameGapShift = 24,
       
   324 	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */
       
   325 
       
   326 	/* Config1 register p.24 */
       
   327 	LEDS1		= (1 << 7),
       
   328 	LEDS0		= (1 << 6),
       
   329 	MSIEnable	= (1 << 5),	/* Enable Message Signaled Interrupt */
       
   330 	Speed_down	= (1 << 4),
       
   331 	MEMMAP		= (1 << 3),
       
   332 	IOMAP		= (1 << 2),
       
   333 	VPD		= (1 << 1),
       
   334 	PMEnable	= (1 << 0),	/* Power Management Enable */
       
   335 
       
   336 	/* Config2 register p. 25 */
       
   337 	PCI_Clock_66MHz = 0x01,
       
   338 	PCI_Clock_33MHz = 0x00,
       
   339 
       
   340 	/* Config3 register p.25 */
       
   341 	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */
       
   342 	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */
       
   343 	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */
       
   344 
       
   345 	/* Config5 register p.27 */
       
   346 	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */
       
   347 	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */
       
   348 	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */
       
   349 	LanWake		= (1 << 1),	/* LanWake enable/disable */
       
   350 	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */
       
   351 
       
   352 	/* TBICSR p.28 */
       
   353 	TBIReset	= 0x80000000,
       
   354 	TBILoopback	= 0x40000000,
       
   355 	TBINwEnable	= 0x20000000,
       
   356 	TBINwRestart	= 0x10000000,
       
   357 	TBILinkOk	= 0x02000000,
       
   358 	TBINwComplete	= 0x01000000,
       
   359 
       
   360 	/* CPlusCmd p.31 */
       
   361 	EnableBist	= (1 << 15),	// 8168 8101
       
   362 	Mac_dbgo_oe	= (1 << 14),	// 8168 8101
       
   363 	Normal_mode	= (1 << 13),	// unused
       
   364 	Force_half_dup	= (1 << 12),	// 8168 8101
       
   365 	Force_rxflow_en	= (1 << 11),	// 8168 8101
       
   366 	Force_txflow_en	= (1 << 10),	// 8168 8101
       
   367 	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101
       
   368 	ASF		= (1 << 8),	// 8168 8101
       
   369 	PktCntrDisable	= (1 << 7),	// 8168 8101
       
   370 	Mac_dbgo_sel	= 0x001c,	// 8168
       
   371 	RxVlan		= (1 << 6),
       
   372 	RxChkSum	= (1 << 5),
       
   373 	PCIDAC		= (1 << 4),
       
   374 	PCIMulRW	= (1 << 3),
       
   375 	INTT_0		= 0x0000,	// 8168
       
   376 	INTT_1		= 0x0001,	// 8168
       
   377 	INTT_2		= 0x0002,	// 8168
       
   378 	INTT_3		= 0x0003,	// 8168
       
   379 
       
   380 	/* rtl8169_PHYstatus */
       
   381 	TBI_Enable	= 0x80,
       
   382 	TxFlowCtrl	= 0x40,
       
   383 	RxFlowCtrl	= 0x20,
       
   384 	_1000bpsF	= 0x10,
       
   385 	_100bps		= 0x08,
       
   386 	_10bps		= 0x04,
       
   387 	LinkStatus	= 0x02,
       
   388 	FullDup		= 0x01,
       
   389 
       
   390 	/* _TBICSRBit */
       
   391 	TBILinkOK	= 0x02000000,
       
   392 
       
   393 	/* DumpCounterCommand */
       
   394 	CounterDump	= 0x8,
       
   395 };
       
   396 
       
   397 enum desc_status_bit {
       
   398 	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */
       
   399 	RingEnd		= (1 << 30), /* End of descriptor ring */
       
   400 	FirstFrag	= (1 << 29), /* First segment of a packet */
       
   401 	LastFrag	= (1 << 28), /* Final segment of a packet */
       
   402 
       
   403 	/* Tx private */
       
   404 	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */
       
   405 	MSSShift	= 16,        /* MSS value position */
       
   406 	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */
       
   407 	IPCS		= (1 << 18), /* Calculate IP checksum */
       
   408 	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */
       
   409 	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */
       
   410 	TxVlanTag	= (1 << 17), /* Add VLAN tag */
       
   411 
       
   412 	/* Rx private */
       
   413 	PID1		= (1 << 18), /* Protocol ID bit 1/2 */
       
   414 	PID0		= (1 << 17), /* Protocol ID bit 2/2 */
       
   415 
       
   416 #define RxProtoUDP	(PID1)
       
   417 #define RxProtoTCP	(PID0)
       
   418 #define RxProtoIP	(PID1 | PID0)
       
   419 #define RxProtoMask	RxProtoIP
       
   420 
       
   421 	IPFail		= (1 << 16), /* IP checksum failed */
       
   422 	UDPFail		= (1 << 15), /* UDP/IP checksum failed */
       
   423 	TCPFail		= (1 << 14), /* TCP/IP checksum failed */
       
   424 	RxVlanTag	= (1 << 16), /* VLAN tag available */
       
   425 };
       
   426 
       
   427 #define RsvdMask	0x3fffc000
       
   428 
       
   429 struct TxDesc {
       
   430 	__le32 opts1;
       
   431 	__le32 opts2;
       
   432 	__le64 addr;
       
   433 };
       
   434 
       
   435 struct RxDesc {
       
   436 	__le32 opts1;
       
   437 	__le32 opts2;
       
   438 	__le64 addr;
       
   439 };
       
   440 
       
   441 struct ring_info {
       
   442 	struct sk_buff	*skb;
       
   443 	u32		len;
       
   444 	u8		__pad[sizeof(void *) - sizeof(u32)];
       
   445 };
       
   446 
       
   447 enum features {
       
   448 	RTL_FEATURE_WOL		= (1 << 0),
       
   449 	RTL_FEATURE_MSI		= (1 << 1),
       
   450 	RTL_FEATURE_GMII	= (1 << 2),
       
   451 };
       
   452 
       
   453 struct rtl8169_counters {
       
   454 	__le64	tx_packets;
       
   455 	__le64	rx_packets;
       
   456 	__le64	tx_errors;
       
   457 	__le32	rx_errors;
       
   458 	__le16	rx_missed;
       
   459 	__le16	align_errors;
       
   460 	__le32	tx_one_collision;
       
   461 	__le32	tx_multi_collision;
       
   462 	__le64	rx_unicast;
       
   463 	__le64	rx_broadcast;
       
   464 	__le32	rx_multicast;
       
   465 	__le16	tx_aborted;
       
   466 	__le16	tx_underun;
       
   467 };
       
   468 
       
   469 struct rtl8169_private {
       
   470 	void __iomem *mmio_addr;	/* memory map physical address */
       
   471 	struct pci_dev *pci_dev;	/* Index of PCI device */
       
   472 	struct net_device *dev;
       
   473 	struct napi_struct napi;
       
   474 	spinlock_t lock;		/* spin lock flag */
       
   475 	u32 msg_enable;
       
   476 	int chipset;
       
   477 	int mac_version;
       
   478 	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
       
   479 	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
       
   480 	u32 dirty_rx;
       
   481 	u32 dirty_tx;
       
   482 	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */
       
   483 	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */
       
   484 	dma_addr_t TxPhyAddr;
       
   485 	dma_addr_t RxPhyAddr;
       
   486 	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */
       
   487 	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */
       
   488 	unsigned align;
       
   489 	unsigned rx_buf_sz;
       
   490 	struct timer_list timer;
       
   491 	u16 cp_cmd;
       
   492 	u16 intr_event;
       
   493 	u16 napi_event;
       
   494 	u16 intr_mask;
       
   495 	int phy_1000_ctrl_reg;
       
   496 #ifdef CONFIG_R8169_VLAN
       
   497 	struct vlan_group *vlgrp;
       
   498 #endif
       
   499 	int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
       
   500 	int (*get_settings)(struct net_device *, struct ethtool_cmd *);
       
   501 	void (*phy_reset_enable)(void __iomem *);
       
   502 	void (*hw_start)(struct net_device *);
       
   503 	unsigned int (*phy_reset_pending)(void __iomem *);
       
   504 	unsigned int (*link_ok)(void __iomem *);
       
   505 	int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
       
   506 	int pcie_cap;
       
   507 	struct delayed_work task;
       
   508 	unsigned features;
       
   509 
       
   510 	struct mii_if_info mii;
       
   511 	struct rtl8169_counters counters;
       
   512 };
       
   513 
       
   514 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
       
   515 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
       
   516 module_param(rx_copybreak, int, 0);
       
   517 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
       
   518 module_param(use_dac, int, 0);
       
   519 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
       
   520 module_param_named(debug, debug.msg_enable, int, 0);
       
   521 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
       
   522 MODULE_LICENSE("GPL");
       
   523 MODULE_VERSION(RTL8169_VERSION);
       
   524 
       
   525 static int rtl8169_open(struct net_device *dev);
       
   526 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
       
   527 				      struct net_device *dev);
       
   528 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
       
   529 static int rtl8169_init_ring(struct net_device *dev);
       
   530 static void rtl_hw_start(struct net_device *dev);
       
   531 static int rtl8169_close(struct net_device *dev);
       
   532 static void rtl_set_rx_mode(struct net_device *dev);
       
   533 static void rtl8169_tx_timeout(struct net_device *dev);
       
   534 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
       
   535 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
       
   536 				void __iomem *, u32 budget);
       
   537 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
       
   538 static void rtl8169_down(struct net_device *dev);
       
   539 static void rtl8169_rx_clear(struct rtl8169_private *tp);
       
   540 static int rtl8169_poll(struct napi_struct *napi, int budget);
       
   541 
       
   542 static const unsigned int rtl8169_rx_config =
       
   543 	(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
       
   544 
       
   545 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
       
   546 {
       
   547 	int i;
       
   548 
       
   549 	RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
       
   550 
       
   551 	for (i = 20; i > 0; i--) {
       
   552 		/*
       
   553 		 * Check if the RTL8169 has completed writing to the specified
       
   554 		 * MII register.
       
   555 		 */
       
   556 		if (!(RTL_R32(PHYAR) & 0x80000000))
       
   557 			break;
       
   558 		udelay(25);
       
   559 	}
       
   560 }
       
   561 
       
   562 static int mdio_read(void __iomem *ioaddr, int reg_addr)
       
   563 {
       
   564 	int i, value = -1;
       
   565 
       
   566 	RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
       
   567 
       
   568 	for (i = 20; i > 0; i--) {
       
   569 		/*
       
   570 		 * Check if the RTL8169 has completed retrieving data from
       
   571 		 * the specified MII register.
       
   572 		 */
       
   573 		if (RTL_R32(PHYAR) & 0x80000000) {
       
   574 			value = RTL_R32(PHYAR) & 0xffff;
       
   575 			break;
       
   576 		}
       
   577 		udelay(25);
       
   578 	}
       
   579 	return value;
       
   580 }
       
   581 
       
   582 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
       
   583 {
       
   584 	mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
       
   585 }
       
   586 
       
   587 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
       
   588 {
       
   589 	int val;
       
   590 
       
   591 	val = mdio_read(ioaddr, reg_addr);
       
   592 	mdio_write(ioaddr, reg_addr, (val | p) & ~m);
       
   593 }
       
   594 
       
   595 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
       
   596 			   int val)
       
   597 {
       
   598 	struct rtl8169_private *tp = netdev_priv(dev);
       
   599 	void __iomem *ioaddr = tp->mmio_addr;
       
   600 
       
   601 	mdio_write(ioaddr, location, val);
       
   602 }
       
   603 
       
   604 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
       
   605 {
       
   606 	struct rtl8169_private *tp = netdev_priv(dev);
       
   607 	void __iomem *ioaddr = tp->mmio_addr;
       
   608 
       
   609 	return mdio_read(ioaddr, location);
       
   610 }
       
   611 
       
   612 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
       
   613 {
       
   614 	unsigned int i;
       
   615 
       
   616 	RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
       
   617 		(reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
       
   618 
       
   619 	for (i = 0; i < 100; i++) {
       
   620 		if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
       
   621 			break;
       
   622 		udelay(10);
       
   623 	}
       
   624 }
       
   625 
       
   626 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
       
   627 {
       
   628 	u16 value = 0xffff;
       
   629 	unsigned int i;
       
   630 
       
   631 	RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
       
   632 
       
   633 	for (i = 0; i < 100; i++) {
       
   634 		if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
       
   635 			value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
       
   636 			break;
       
   637 		}
       
   638 		udelay(10);
       
   639 	}
       
   640 
       
   641 	return value;
       
   642 }
       
   643 
       
   644 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
       
   645 {
       
   646 	unsigned int i;
       
   647 
       
   648 	RTL_W32(CSIDR, value);
       
   649 	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
       
   650 		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
       
   651 
       
   652 	for (i = 0; i < 100; i++) {
       
   653 		if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
       
   654 			break;
       
   655 		udelay(10);
       
   656 	}
       
   657 }
       
   658 
       
   659 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
       
   660 {
       
   661 	u32 value = ~0x00;
       
   662 	unsigned int i;
       
   663 
       
   664 	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
       
   665 		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
       
   666 
       
   667 	for (i = 0; i < 100; i++) {
       
   668 		if (RTL_R32(CSIAR) & CSIAR_FLAG) {
       
   669 			value = RTL_R32(CSIDR);
       
   670 			break;
       
   671 		}
       
   672 		udelay(10);
       
   673 	}
       
   674 
       
   675 	return value;
       
   676 }
       
   677 
       
   678 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
       
   679 {
       
   680 	u8 value = 0xff;
       
   681 	unsigned int i;
       
   682 
       
   683 	RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
       
   684 
       
   685 	for (i = 0; i < 300; i++) {
       
   686 		if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
       
   687 			value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
       
   688 			break;
       
   689 		}
       
   690 		udelay(100);
       
   691 	}
       
   692 
       
   693 	return value;
       
   694 }
       
   695 
       
   696 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
       
   697 {
       
   698 	RTL_W16(IntrMask, 0x0000);
       
   699 
       
   700 	RTL_W16(IntrStatus, 0xffff);
       
   701 }
       
   702 
       
   703 static void rtl8169_asic_down(void __iomem *ioaddr)
       
   704 {
       
   705 	RTL_W8(ChipCmd, 0x00);
       
   706 	rtl8169_irq_mask_and_ack(ioaddr);
       
   707 	RTL_R16(CPlusCmd);
       
   708 }
       
   709 
       
   710 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
       
   711 {
       
   712 	return RTL_R32(TBICSR) & TBIReset;
       
   713 }
       
   714 
       
   715 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
       
   716 {
       
   717 	return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
       
   718 }
       
   719 
       
   720 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
       
   721 {
       
   722 	return RTL_R32(TBICSR) & TBILinkOk;
       
   723 }
       
   724 
       
   725 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
       
   726 {
       
   727 	return RTL_R8(PHYstatus) & LinkStatus;
       
   728 }
       
   729 
       
   730 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
       
   731 {
       
   732 	RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
       
   733 }
       
   734 
       
   735 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
       
   736 {
       
   737 	unsigned int val;
       
   738 
       
   739 	val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
       
   740 	mdio_write(ioaddr, MII_BMCR, val & 0xffff);
       
   741 }
       
   742 
       
   743 static void rtl8169_check_link_status(struct net_device *dev,
       
   744 				      struct rtl8169_private *tp,
       
   745 				      void __iomem *ioaddr)
       
   746 {
       
   747 	unsigned long flags;
       
   748 
       
   749 	spin_lock_irqsave(&tp->lock, flags);
       
   750 	if (tp->link_ok(ioaddr)) {
       
   751 		netif_carrier_on(dev);
       
   752 		if (netif_msg_ifup(tp))
       
   753 			printk(KERN_INFO PFX "%s: link up\n", dev->name);
       
   754 	} else {
       
   755 		if (netif_msg_ifdown(tp))
       
   756 			printk(KERN_INFO PFX "%s: link down\n", dev->name);
       
   757 		netif_carrier_off(dev);
       
   758 	}
       
   759 	spin_unlock_irqrestore(&tp->lock, flags);
       
   760 }
       
   761 
       
   762 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
       
   763 {
       
   764 	struct rtl8169_private *tp = netdev_priv(dev);
       
   765 	void __iomem *ioaddr = tp->mmio_addr;
       
   766 	u8 options;
       
   767 
       
   768 	wol->wolopts = 0;
       
   769 
       
   770 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
       
   771 	wol->supported = WAKE_ANY;
       
   772 
       
   773 	spin_lock_irq(&tp->lock);
       
   774 
       
   775 	options = RTL_R8(Config1);
       
   776 	if (!(options & PMEnable))
       
   777 		goto out_unlock;
       
   778 
       
   779 	options = RTL_R8(Config3);
       
   780 	if (options & LinkUp)
       
   781 		wol->wolopts |= WAKE_PHY;
       
   782 	if (options & MagicPacket)
       
   783 		wol->wolopts |= WAKE_MAGIC;
       
   784 
       
   785 	options = RTL_R8(Config5);
       
   786 	if (options & UWF)
       
   787 		wol->wolopts |= WAKE_UCAST;
       
   788 	if (options & BWF)
       
   789 		wol->wolopts |= WAKE_BCAST;
       
   790 	if (options & MWF)
       
   791 		wol->wolopts |= WAKE_MCAST;
       
   792 
       
   793 out_unlock:
       
   794 	spin_unlock_irq(&tp->lock);
       
   795 }
       
   796 
       
   797 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
       
   798 {
       
   799 	struct rtl8169_private *tp = netdev_priv(dev);
       
   800 	void __iomem *ioaddr = tp->mmio_addr;
       
   801 	unsigned int i;
       
   802 	static const struct {
       
   803 		u32 opt;
       
   804 		u16 reg;
       
   805 		u8  mask;
       
   806 	} cfg[] = {
       
   807 		{ WAKE_ANY,   Config1, PMEnable },
       
   808 		{ WAKE_PHY,   Config3, LinkUp },
       
   809 		{ WAKE_MAGIC, Config3, MagicPacket },
       
   810 		{ WAKE_UCAST, Config5, UWF },
       
   811 		{ WAKE_BCAST, Config5, BWF },
       
   812 		{ WAKE_MCAST, Config5, MWF },
       
   813 		{ WAKE_ANY,   Config5, LanWake }
       
   814 	};
       
   815 
       
   816 	spin_lock_irq(&tp->lock);
       
   817 
       
   818 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
   819 
       
   820 	for (i = 0; i < ARRAY_SIZE(cfg); i++) {
       
   821 		u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
       
   822 		if (wol->wolopts & cfg[i].opt)
       
   823 			options |= cfg[i].mask;
       
   824 		RTL_W8(cfg[i].reg, options);
       
   825 	}
       
   826 
       
   827 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
   828 
       
   829 	if (wol->wolopts)
       
   830 		tp->features |= RTL_FEATURE_WOL;
       
   831 	else
       
   832 		tp->features &= ~RTL_FEATURE_WOL;
       
   833 	device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
       
   834 
       
   835 	spin_unlock_irq(&tp->lock);
       
   836 
       
   837 	return 0;
       
   838 }
       
   839 
       
   840 static void rtl8169_get_drvinfo(struct net_device *dev,
       
   841 				struct ethtool_drvinfo *info)
       
   842 {
       
   843 	struct rtl8169_private *tp = netdev_priv(dev);
       
   844 
       
   845 	strcpy(info->driver, MODULENAME);
       
   846 	strcpy(info->version, RTL8169_VERSION);
       
   847 	strcpy(info->bus_info, pci_name(tp->pci_dev));
       
   848 }
       
   849 
       
   850 static int rtl8169_get_regs_len(struct net_device *dev)
       
   851 {
       
   852 	return R8169_REGS_SIZE;
       
   853 }
       
   854 
       
   855 static int rtl8169_set_speed_tbi(struct net_device *dev,
       
   856 				 u8 autoneg, u16 speed, u8 duplex)
       
   857 {
       
   858 	struct rtl8169_private *tp = netdev_priv(dev);
       
   859 	void __iomem *ioaddr = tp->mmio_addr;
       
   860 	int ret = 0;
       
   861 	u32 reg;
       
   862 
       
   863 	reg = RTL_R32(TBICSR);
       
   864 	if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
       
   865 	    (duplex == DUPLEX_FULL)) {
       
   866 		RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
       
   867 	} else if (autoneg == AUTONEG_ENABLE)
       
   868 		RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
       
   869 	else {
       
   870 		if (netif_msg_link(tp)) {
       
   871 			printk(KERN_WARNING "%s: "
       
   872 			       "incorrect speed setting refused in TBI mode\n",
       
   873 			       dev->name);
       
   874 		}
       
   875 		ret = -EOPNOTSUPP;
       
   876 	}
       
   877 
       
   878 	return ret;
       
   879 }
       
   880 
       
   881 static int rtl8169_set_speed_xmii(struct net_device *dev,
       
   882 				  u8 autoneg, u16 speed, u8 duplex)
       
   883 {
       
   884 	struct rtl8169_private *tp = netdev_priv(dev);
       
   885 	void __iomem *ioaddr = tp->mmio_addr;
       
   886 	int giga_ctrl, bmcr;
       
   887 
       
   888 	if (autoneg == AUTONEG_ENABLE) {
       
   889 		int auto_nego;
       
   890 
       
   891 		auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
       
   892 		auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
       
   893 			      ADVERTISE_100HALF | ADVERTISE_100FULL);
       
   894 		auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
       
   895 
       
   896 		giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
       
   897 		giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
       
   898 
       
   899 		/* The 8100e/8101e/8102e do Fast Ethernet only. */
       
   900 		if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
       
   901 		    (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
       
   902 		    (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
       
   903 		    (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
       
   904 		    (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
       
   905 		    (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
       
   906 		    (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
       
   907 		    (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
       
   908 			giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
       
   909 		} else if (netif_msg_link(tp)) {
       
   910 			printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
       
   911 			       dev->name);
       
   912 		}
       
   913 
       
   914 		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
       
   915 
       
   916 		if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
       
   917 		    (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
       
   918 		    (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
       
   919 			/*
       
   920 			 * Wake up the PHY.
       
   921 			 * Vendor specific (0x1f) and reserved (0x0e) MII
       
   922 			 * registers.
       
   923 			 */
       
   924 			mdio_write(ioaddr, 0x1f, 0x0000);
       
   925 			mdio_write(ioaddr, 0x0e, 0x0000);
       
   926 		}
       
   927 
       
   928 		mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
       
   929 		mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
       
   930 	} else {
       
   931 		giga_ctrl = 0;
       
   932 
       
   933 		if (speed == SPEED_10)
       
   934 			bmcr = 0;
       
   935 		else if (speed == SPEED_100)
       
   936 			bmcr = BMCR_SPEED100;
       
   937 		else
       
   938 			return -EINVAL;
       
   939 
       
   940 		if (duplex == DUPLEX_FULL)
       
   941 			bmcr |= BMCR_FULLDPLX;
       
   942 
       
   943 		mdio_write(ioaddr, 0x1f, 0x0000);
       
   944 	}
       
   945 
       
   946 	tp->phy_1000_ctrl_reg = giga_ctrl;
       
   947 
       
   948 	mdio_write(ioaddr, MII_BMCR, bmcr);
       
   949 
       
   950 	if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
       
   951 	    (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
       
   952 		if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
       
   953 			mdio_write(ioaddr, 0x17, 0x2138);
       
   954 			mdio_write(ioaddr, 0x0e, 0x0260);
       
   955 		} else {
       
   956 			mdio_write(ioaddr, 0x17, 0x2108);
       
   957 			mdio_write(ioaddr, 0x0e, 0x0000);
       
   958 		}
       
   959 	}
       
   960 
       
   961 	return 0;
       
   962 }
       
   963 
       
   964 static int rtl8169_set_speed(struct net_device *dev,
       
   965 			     u8 autoneg, u16 speed, u8 duplex)
       
   966 {
       
   967 	struct rtl8169_private *tp = netdev_priv(dev);
       
   968 	int ret;
       
   969 
       
   970 	ret = tp->set_speed(dev, autoneg, speed, duplex);
       
   971 
       
   972 	if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
       
   973 		mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
       
   974 
       
   975 	return ret;
       
   976 }
       
   977 
       
   978 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
       
   979 {
       
   980 	struct rtl8169_private *tp = netdev_priv(dev);
       
   981 	unsigned long flags;
       
   982 	int ret;
       
   983 
       
   984 	spin_lock_irqsave(&tp->lock, flags);
       
   985 	ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
       
   986 	spin_unlock_irqrestore(&tp->lock, flags);
       
   987 
       
   988 	return ret;
       
   989 }
       
   990 
       
   991 static u32 rtl8169_get_rx_csum(struct net_device *dev)
       
   992 {
       
   993 	struct rtl8169_private *tp = netdev_priv(dev);
       
   994 
       
   995 	return tp->cp_cmd & RxChkSum;
       
   996 }
       
   997 
       
   998 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
       
   999 {
       
  1000 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1001 	void __iomem *ioaddr = tp->mmio_addr;
       
  1002 	unsigned long flags;
       
  1003 
       
  1004 	spin_lock_irqsave(&tp->lock, flags);
       
  1005 
       
  1006 	if (data)
       
  1007 		tp->cp_cmd |= RxChkSum;
       
  1008 	else
       
  1009 		tp->cp_cmd &= ~RxChkSum;
       
  1010 
       
  1011 	RTL_W16(CPlusCmd, tp->cp_cmd);
       
  1012 	RTL_R16(CPlusCmd);
       
  1013 
       
  1014 	spin_unlock_irqrestore(&tp->lock, flags);
       
  1015 
       
  1016 	return 0;
       
  1017 }
       
  1018 
       
  1019 #ifdef CONFIG_R8169_VLAN
       
  1020 
       
  1021 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
       
  1022 				      struct sk_buff *skb)
       
  1023 {
       
  1024 	return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
       
  1025 		TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
       
  1026 }
       
  1027 
       
  1028 static void rtl8169_vlan_rx_register(struct net_device *dev,
       
  1029 				     struct vlan_group *grp)
       
  1030 {
       
  1031 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1032 	void __iomem *ioaddr = tp->mmio_addr;
       
  1033 	unsigned long flags;
       
  1034 
       
  1035 	spin_lock_irqsave(&tp->lock, flags);
       
  1036 	tp->vlgrp = grp;
       
  1037 	/*
       
  1038 	 * Do not disable RxVlan on 8110SCd.
       
  1039 	 */
       
  1040 	if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
       
  1041 		tp->cp_cmd |= RxVlan;
       
  1042 	else
       
  1043 		tp->cp_cmd &= ~RxVlan;
       
  1044 	RTL_W16(CPlusCmd, tp->cp_cmd);
       
  1045 	RTL_R16(CPlusCmd);
       
  1046 	spin_unlock_irqrestore(&tp->lock, flags);
       
  1047 }
       
  1048 
       
  1049 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
       
  1050 			       struct sk_buff *skb)
       
  1051 {
       
  1052 	u32 opts2 = le32_to_cpu(desc->opts2);
       
  1053 	struct vlan_group *vlgrp = tp->vlgrp;
       
  1054 	int ret;
       
  1055 
       
  1056 	if (vlgrp && (opts2 & RxVlanTag)) {
       
  1057 		vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
       
  1058 		ret = 0;
       
  1059 	} else
       
  1060 		ret = -1;
       
  1061 	desc->opts2 = 0;
       
  1062 	return ret;
       
  1063 }
       
  1064 
       
  1065 #else /* !CONFIG_R8169_VLAN */
       
  1066 
       
  1067 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
       
  1068 				      struct sk_buff *skb)
       
  1069 {
       
  1070 	return 0;
       
  1071 }
       
  1072 
       
  1073 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
       
  1074 			       struct sk_buff *skb)
       
  1075 {
       
  1076 	return -1;
       
  1077 }
       
  1078 
       
  1079 #endif
       
  1080 
       
  1081 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
       
  1082 {
       
  1083 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1084 	void __iomem *ioaddr = tp->mmio_addr;
       
  1085 	u32 status;
       
  1086 
       
  1087 	cmd->supported =
       
  1088 		SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
       
  1089 	cmd->port = PORT_FIBRE;
       
  1090 	cmd->transceiver = XCVR_INTERNAL;
       
  1091 
       
  1092 	status = RTL_R32(TBICSR);
       
  1093 	cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
       
  1094 	cmd->autoneg = !!(status & TBINwEnable);
       
  1095 
       
  1096 	cmd->speed = SPEED_1000;
       
  1097 	cmd->duplex = DUPLEX_FULL; /* Always set */
       
  1098 
       
  1099 	return 0;
       
  1100 }
       
  1101 
       
  1102 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
       
  1103 {
       
  1104 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1105 
       
  1106 	return mii_ethtool_gset(&tp->mii, cmd);
       
  1107 }
       
  1108 
       
  1109 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
       
  1110 {
       
  1111 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1112 	unsigned long flags;
       
  1113 	int rc;
       
  1114 
       
  1115 	spin_lock_irqsave(&tp->lock, flags);
       
  1116 
       
  1117 	rc = tp->get_settings(dev, cmd);
       
  1118 
       
  1119 	spin_unlock_irqrestore(&tp->lock, flags);
       
  1120 	return rc;
       
  1121 }
       
  1122 
       
  1123 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
       
  1124 			     void *p)
       
  1125 {
       
  1126 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1127 	unsigned long flags;
       
  1128 
       
  1129 	if (regs->len > R8169_REGS_SIZE)
       
  1130 		regs->len = R8169_REGS_SIZE;
       
  1131 
       
  1132 	spin_lock_irqsave(&tp->lock, flags);
       
  1133 	memcpy_fromio(p, tp->mmio_addr, regs->len);
       
  1134 	spin_unlock_irqrestore(&tp->lock, flags);
       
  1135 }
       
  1136 
       
  1137 static u32 rtl8169_get_msglevel(struct net_device *dev)
       
  1138 {
       
  1139 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1140 
       
  1141 	return tp->msg_enable;
       
  1142 }
       
  1143 
       
  1144 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
       
  1145 {
       
  1146 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1147 
       
  1148 	tp->msg_enable = value;
       
  1149 }
       
  1150 
       
  1151 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
       
  1152 	"tx_packets",
       
  1153 	"rx_packets",
       
  1154 	"tx_errors",
       
  1155 	"rx_errors",
       
  1156 	"rx_missed",
       
  1157 	"align_errors",
       
  1158 	"tx_single_collisions",
       
  1159 	"tx_multi_collisions",
       
  1160 	"unicast",
       
  1161 	"broadcast",
       
  1162 	"multicast",
       
  1163 	"tx_aborted",
       
  1164 	"tx_underrun",
       
  1165 };
       
  1166 
       
  1167 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
       
  1168 {
       
  1169 	switch (sset) {
       
  1170 	case ETH_SS_STATS:
       
  1171 		return ARRAY_SIZE(rtl8169_gstrings);
       
  1172 	default:
       
  1173 		return -EOPNOTSUPP;
       
  1174 	}
       
  1175 }
       
  1176 
       
  1177 static void rtl8169_update_counters(struct net_device *dev)
       
  1178 {
       
  1179 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1180 	void __iomem *ioaddr = tp->mmio_addr;
       
  1181 	struct rtl8169_counters *counters;
       
  1182 	dma_addr_t paddr;
       
  1183 	u32 cmd;
       
  1184 	int wait = 1000;
       
  1185 
       
  1186 	/*
       
  1187 	 * Some chips are unable to dump tally counters when the receiver
       
  1188 	 * is disabled.
       
  1189 	 */
       
  1190 	if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
       
  1191 		return;
       
  1192 
       
  1193 	counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
       
  1194 	if (!counters)
       
  1195 		return;
       
  1196 
       
  1197 	RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
       
  1198 	cmd = (u64)paddr & DMA_BIT_MASK(32);
       
  1199 	RTL_W32(CounterAddrLow, cmd);
       
  1200 	RTL_W32(CounterAddrLow, cmd | CounterDump);
       
  1201 
       
  1202 	while (wait--) {
       
  1203 		if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
       
  1204 			/* copy updated counters */
       
  1205 			memcpy(&tp->counters, counters, sizeof(*counters));
       
  1206 			break;
       
  1207 		}
       
  1208 		udelay(10);
       
  1209 	}
       
  1210 
       
  1211 	RTL_W32(CounterAddrLow, 0);
       
  1212 	RTL_W32(CounterAddrHigh, 0);
       
  1213 
       
  1214 	pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
       
  1215 }
       
  1216 
       
  1217 static void rtl8169_get_ethtool_stats(struct net_device *dev,
       
  1218 				      struct ethtool_stats *stats, u64 *data)
       
  1219 {
       
  1220 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1221 
       
  1222 	ASSERT_RTNL();
       
  1223 
       
  1224 	rtl8169_update_counters(dev);
       
  1225 
       
  1226 	data[0] = le64_to_cpu(tp->counters.tx_packets);
       
  1227 	data[1] = le64_to_cpu(tp->counters.rx_packets);
       
  1228 	data[2] = le64_to_cpu(tp->counters.tx_errors);
       
  1229 	data[3] = le32_to_cpu(tp->counters.rx_errors);
       
  1230 	data[4] = le16_to_cpu(tp->counters.rx_missed);
       
  1231 	data[5] = le16_to_cpu(tp->counters.align_errors);
       
  1232 	data[6] = le32_to_cpu(tp->counters.tx_one_collision);
       
  1233 	data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
       
  1234 	data[8] = le64_to_cpu(tp->counters.rx_unicast);
       
  1235 	data[9] = le64_to_cpu(tp->counters.rx_broadcast);
       
  1236 	data[10] = le32_to_cpu(tp->counters.rx_multicast);
       
  1237 	data[11] = le16_to_cpu(tp->counters.tx_aborted);
       
  1238 	data[12] = le16_to_cpu(tp->counters.tx_underun);
       
  1239 }
       
  1240 
       
  1241 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
       
  1242 {
       
  1243 	switch(stringset) {
       
  1244 	case ETH_SS_STATS:
       
  1245 		memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
       
  1246 		break;
       
  1247 	}
       
  1248 }
       
  1249 
       
  1250 static const struct ethtool_ops rtl8169_ethtool_ops = {
       
  1251 	.get_drvinfo		= rtl8169_get_drvinfo,
       
  1252 	.get_regs_len		= rtl8169_get_regs_len,
       
  1253 	.get_link		= ethtool_op_get_link,
       
  1254 	.get_settings		= rtl8169_get_settings,
       
  1255 	.set_settings		= rtl8169_set_settings,
       
  1256 	.get_msglevel		= rtl8169_get_msglevel,
       
  1257 	.set_msglevel		= rtl8169_set_msglevel,
       
  1258 	.get_rx_csum		= rtl8169_get_rx_csum,
       
  1259 	.set_rx_csum		= rtl8169_set_rx_csum,
       
  1260 	.set_tx_csum		= ethtool_op_set_tx_csum,
       
  1261 	.set_sg			= ethtool_op_set_sg,
       
  1262 	.set_tso		= ethtool_op_set_tso,
       
  1263 	.get_regs		= rtl8169_get_regs,
       
  1264 	.get_wol		= rtl8169_get_wol,
       
  1265 	.set_wol		= rtl8169_set_wol,
       
  1266 	.get_strings		= rtl8169_get_strings,
       
  1267 	.get_sset_count		= rtl8169_get_sset_count,
       
  1268 	.get_ethtool_stats	= rtl8169_get_ethtool_stats,
       
  1269 };
       
  1270 
       
  1271 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
       
  1272 				    void __iomem *ioaddr)
       
  1273 {
       
  1274 	/*
       
  1275 	 * The driver currently handles the 8168Bf and the 8168Be identically
       
  1276 	 * but they can be identified more specifically through the test below
       
  1277 	 * if needed:
       
  1278 	 *
       
  1279 	 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
       
  1280 	 *
       
  1281 	 * Same thing for the 8101Eb and the 8101Ec:
       
  1282 	 *
       
  1283 	 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
       
  1284 	 */
       
  1285 	static const struct {
       
  1286 		u32 mask;
       
  1287 		u32 val;
       
  1288 		int mac_version;
       
  1289 	} mac_info[] = {
       
  1290 		/* 8168D family. */
       
  1291 		{ 0x7cf00000, 0x28300000,	RTL_GIGA_MAC_VER_26 },
       
  1292 		{ 0x7cf00000, 0x28100000,	RTL_GIGA_MAC_VER_25 },
       
  1293 		{ 0x7c800000, 0x28800000,	RTL_GIGA_MAC_VER_27 },
       
  1294 		{ 0x7c800000, 0x28000000,	RTL_GIGA_MAC_VER_26 },
       
  1295 
       
  1296 		/* 8168C family. */
       
  1297 		{ 0x7cf00000, 0x3ca00000,	RTL_GIGA_MAC_VER_24 },
       
  1298 		{ 0x7cf00000, 0x3c900000,	RTL_GIGA_MAC_VER_23 },
       
  1299 		{ 0x7cf00000, 0x3c800000,	RTL_GIGA_MAC_VER_18 },
       
  1300 		{ 0x7c800000, 0x3c800000,	RTL_GIGA_MAC_VER_24 },
       
  1301 		{ 0x7cf00000, 0x3c000000,	RTL_GIGA_MAC_VER_19 },
       
  1302 		{ 0x7cf00000, 0x3c200000,	RTL_GIGA_MAC_VER_20 },
       
  1303 		{ 0x7cf00000, 0x3c300000,	RTL_GIGA_MAC_VER_21 },
       
  1304 		{ 0x7cf00000, 0x3c400000,	RTL_GIGA_MAC_VER_22 },
       
  1305 		{ 0x7c800000, 0x3c000000,	RTL_GIGA_MAC_VER_22 },
       
  1306 
       
  1307 		/* 8168B family. */
       
  1308 		{ 0x7cf00000, 0x38000000,	RTL_GIGA_MAC_VER_12 },
       
  1309 		{ 0x7cf00000, 0x38500000,	RTL_GIGA_MAC_VER_17 },
       
  1310 		{ 0x7c800000, 0x38000000,	RTL_GIGA_MAC_VER_17 },
       
  1311 		{ 0x7c800000, 0x30000000,	RTL_GIGA_MAC_VER_11 },
       
  1312 
       
  1313 		/* 8101 family. */
       
  1314 		{ 0x7cf00000, 0x34a00000,	RTL_GIGA_MAC_VER_09 },
       
  1315 		{ 0x7cf00000, 0x24a00000,	RTL_GIGA_MAC_VER_09 },
       
  1316 		{ 0x7cf00000, 0x34900000,	RTL_GIGA_MAC_VER_08 },
       
  1317 		{ 0x7cf00000, 0x24900000,	RTL_GIGA_MAC_VER_08 },
       
  1318 		{ 0x7cf00000, 0x34800000,	RTL_GIGA_MAC_VER_07 },
       
  1319 		{ 0x7cf00000, 0x24800000,	RTL_GIGA_MAC_VER_07 },
       
  1320 		{ 0x7cf00000, 0x34000000,	RTL_GIGA_MAC_VER_13 },
       
  1321 		{ 0x7cf00000, 0x34300000,	RTL_GIGA_MAC_VER_10 },
       
  1322 		{ 0x7cf00000, 0x34200000,	RTL_GIGA_MAC_VER_16 },
       
  1323 		{ 0x7c800000, 0x34800000,	RTL_GIGA_MAC_VER_09 },
       
  1324 		{ 0x7c800000, 0x24800000,	RTL_GIGA_MAC_VER_09 },
       
  1325 		{ 0x7c800000, 0x34000000,	RTL_GIGA_MAC_VER_16 },
       
  1326 		/* FIXME: where did these entries come from ? -- FR */
       
  1327 		{ 0xfc800000, 0x38800000,	RTL_GIGA_MAC_VER_15 },
       
  1328 		{ 0xfc800000, 0x30800000,	RTL_GIGA_MAC_VER_14 },
       
  1329 
       
  1330 		/* 8110 family. */
       
  1331 		{ 0xfc800000, 0x98000000,	RTL_GIGA_MAC_VER_06 },
       
  1332 		{ 0xfc800000, 0x18000000,	RTL_GIGA_MAC_VER_05 },
       
  1333 		{ 0xfc800000, 0x10000000,	RTL_GIGA_MAC_VER_04 },
       
  1334 		{ 0xfc800000, 0x04000000,	RTL_GIGA_MAC_VER_03 },
       
  1335 		{ 0xfc800000, 0x00800000,	RTL_GIGA_MAC_VER_02 },
       
  1336 		{ 0xfc800000, 0x00000000,	RTL_GIGA_MAC_VER_01 },
       
  1337 
       
  1338 		/* Catch-all */
       
  1339 		{ 0x00000000, 0x00000000,	RTL_GIGA_MAC_NONE   }
       
  1340 	}, *p = mac_info;
       
  1341 	u32 reg;
       
  1342 
       
  1343 	reg = RTL_R32(TxConfig);
       
  1344 	while ((reg & p->mask) != p->val)
       
  1345 		p++;
       
  1346 	tp->mac_version = p->mac_version;
       
  1347 }
       
  1348 
       
  1349 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
       
  1350 {
       
  1351 	dprintk("mac_version = 0x%02x\n", tp->mac_version);
       
  1352 }
       
  1353 
       
  1354 struct phy_reg {
       
  1355 	u16 reg;
       
  1356 	u16 val;
       
  1357 };
       
  1358 
       
  1359 static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
       
  1360 {
       
  1361 	while (len-- > 0) {
       
  1362 		mdio_write(ioaddr, regs->reg, regs->val);
       
  1363 		regs++;
       
  1364 	}
       
  1365 }
       
  1366 
       
  1367 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
       
  1368 {
       
  1369 	static const struct phy_reg phy_reg_init[] = {
       
  1370 		{ 0x1f, 0x0001 },
       
  1371 		{ 0x06, 0x006e },
       
  1372 		{ 0x08, 0x0708 },
       
  1373 		{ 0x15, 0x4000 },
       
  1374 		{ 0x18, 0x65c7 },
       
  1375 
       
  1376 		{ 0x1f, 0x0001 },
       
  1377 		{ 0x03, 0x00a1 },
       
  1378 		{ 0x02, 0x0008 },
       
  1379 		{ 0x01, 0x0120 },
       
  1380 		{ 0x00, 0x1000 },
       
  1381 		{ 0x04, 0x0800 },
       
  1382 		{ 0x04, 0x0000 },
       
  1383 
       
  1384 		{ 0x03, 0xff41 },
       
  1385 		{ 0x02, 0xdf60 },
       
  1386 		{ 0x01, 0x0140 },
       
  1387 		{ 0x00, 0x0077 },
       
  1388 		{ 0x04, 0x7800 },
       
  1389 		{ 0x04, 0x7000 },
       
  1390 
       
  1391 		{ 0x03, 0x802f },
       
  1392 		{ 0x02, 0x4f02 },
       
  1393 		{ 0x01, 0x0409 },
       
  1394 		{ 0x00, 0xf0f9 },
       
  1395 		{ 0x04, 0x9800 },
       
  1396 		{ 0x04, 0x9000 },
       
  1397 
       
  1398 		{ 0x03, 0xdf01 },
       
  1399 		{ 0x02, 0xdf20 },
       
  1400 		{ 0x01, 0xff95 },
       
  1401 		{ 0x00, 0xba00 },
       
  1402 		{ 0x04, 0xa800 },
       
  1403 		{ 0x04, 0xa000 },
       
  1404 
       
  1405 		{ 0x03, 0xff41 },
       
  1406 		{ 0x02, 0xdf20 },
       
  1407 		{ 0x01, 0x0140 },
       
  1408 		{ 0x00, 0x00bb },
       
  1409 		{ 0x04, 0xb800 },
       
  1410 		{ 0x04, 0xb000 },
       
  1411 
       
  1412 		{ 0x03, 0xdf41 },
       
  1413 		{ 0x02, 0xdc60 },
       
  1414 		{ 0x01, 0x6340 },
       
  1415 		{ 0x00, 0x007d },
       
  1416 		{ 0x04, 0xd800 },
       
  1417 		{ 0x04, 0xd000 },
       
  1418 
       
  1419 		{ 0x03, 0xdf01 },
       
  1420 		{ 0x02, 0xdf20 },
       
  1421 		{ 0x01, 0x100a },
       
  1422 		{ 0x00, 0xa0ff },
       
  1423 		{ 0x04, 0xf800 },
       
  1424 		{ 0x04, 0xf000 },
       
  1425 
       
  1426 		{ 0x1f, 0x0000 },
       
  1427 		{ 0x0b, 0x0000 },
       
  1428 		{ 0x00, 0x9200 }
       
  1429 	};
       
  1430 
       
  1431 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1432 }
       
  1433 
       
  1434 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
       
  1435 {
       
  1436 	static const struct phy_reg phy_reg_init[] = {
       
  1437 		{ 0x1f, 0x0002 },
       
  1438 		{ 0x01, 0x90d0 },
       
  1439 		{ 0x1f, 0x0000 }
       
  1440 	};
       
  1441 
       
  1442 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1443 }
       
  1444 
       
  1445 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
       
  1446 					   void __iomem *ioaddr)
       
  1447 {
       
  1448 	struct pci_dev *pdev = tp->pci_dev;
       
  1449 	u16 vendor_id, device_id;
       
  1450 
       
  1451 	pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
       
  1452 	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
       
  1453 
       
  1454 	if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
       
  1455 		return;
       
  1456 
       
  1457 	mdio_write(ioaddr, 0x1f, 0x0001);
       
  1458 	mdio_write(ioaddr, 0x10, 0xf01b);
       
  1459 	mdio_write(ioaddr, 0x1f, 0x0000);
       
  1460 }
       
  1461 
       
  1462 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
       
  1463 				     void __iomem *ioaddr)
       
  1464 {
       
  1465 	static const struct phy_reg phy_reg_init[] = {
       
  1466 		{ 0x1f, 0x0001 },
       
  1467 		{ 0x04, 0x0000 },
       
  1468 		{ 0x03, 0x00a1 },
       
  1469 		{ 0x02, 0x0008 },
       
  1470 		{ 0x01, 0x0120 },
       
  1471 		{ 0x00, 0x1000 },
       
  1472 		{ 0x04, 0x0800 },
       
  1473 		{ 0x04, 0x9000 },
       
  1474 		{ 0x03, 0x802f },
       
  1475 		{ 0x02, 0x4f02 },
       
  1476 		{ 0x01, 0x0409 },
       
  1477 		{ 0x00, 0xf099 },
       
  1478 		{ 0x04, 0x9800 },
       
  1479 		{ 0x04, 0xa000 },
       
  1480 		{ 0x03, 0xdf01 },
       
  1481 		{ 0x02, 0xdf20 },
       
  1482 		{ 0x01, 0xff95 },
       
  1483 		{ 0x00, 0xba00 },
       
  1484 		{ 0x04, 0xa800 },
       
  1485 		{ 0x04, 0xf000 },
       
  1486 		{ 0x03, 0xdf01 },
       
  1487 		{ 0x02, 0xdf20 },
       
  1488 		{ 0x01, 0x101a },
       
  1489 		{ 0x00, 0xa0ff },
       
  1490 		{ 0x04, 0xf800 },
       
  1491 		{ 0x04, 0x0000 },
       
  1492 		{ 0x1f, 0x0000 },
       
  1493 
       
  1494 		{ 0x1f, 0x0001 },
       
  1495 		{ 0x10, 0xf41b },
       
  1496 		{ 0x14, 0xfb54 },
       
  1497 		{ 0x18, 0xf5c7 },
       
  1498 		{ 0x1f, 0x0000 },
       
  1499 
       
  1500 		{ 0x1f, 0x0001 },
       
  1501 		{ 0x17, 0x0cc0 },
       
  1502 		{ 0x1f, 0x0000 }
       
  1503 	};
       
  1504 
       
  1505 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1506 
       
  1507 	rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
       
  1508 }
       
  1509 
       
  1510 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
       
  1511 {
       
  1512 	static const struct phy_reg phy_reg_init[] = {
       
  1513 		{ 0x1f, 0x0001 },
       
  1514 		{ 0x04, 0x0000 },
       
  1515 		{ 0x03, 0x00a1 },
       
  1516 		{ 0x02, 0x0008 },
       
  1517 		{ 0x01, 0x0120 },
       
  1518 		{ 0x00, 0x1000 },
       
  1519 		{ 0x04, 0x0800 },
       
  1520 		{ 0x04, 0x9000 },
       
  1521 		{ 0x03, 0x802f },
       
  1522 		{ 0x02, 0x4f02 },
       
  1523 		{ 0x01, 0x0409 },
       
  1524 		{ 0x00, 0xf099 },
       
  1525 		{ 0x04, 0x9800 },
       
  1526 		{ 0x04, 0xa000 },
       
  1527 		{ 0x03, 0xdf01 },
       
  1528 		{ 0x02, 0xdf20 },
       
  1529 		{ 0x01, 0xff95 },
       
  1530 		{ 0x00, 0xba00 },
       
  1531 		{ 0x04, 0xa800 },
       
  1532 		{ 0x04, 0xf000 },
       
  1533 		{ 0x03, 0xdf01 },
       
  1534 		{ 0x02, 0xdf20 },
       
  1535 		{ 0x01, 0x101a },
       
  1536 		{ 0x00, 0xa0ff },
       
  1537 		{ 0x04, 0xf800 },
       
  1538 		{ 0x04, 0x0000 },
       
  1539 		{ 0x1f, 0x0000 },
       
  1540 
       
  1541 		{ 0x1f, 0x0001 },
       
  1542 		{ 0x0b, 0x8480 },
       
  1543 		{ 0x1f, 0x0000 },
       
  1544 
       
  1545 		{ 0x1f, 0x0001 },
       
  1546 		{ 0x18, 0x67c7 },
       
  1547 		{ 0x04, 0x2000 },
       
  1548 		{ 0x03, 0x002f },
       
  1549 		{ 0x02, 0x4360 },
       
  1550 		{ 0x01, 0x0109 },
       
  1551 		{ 0x00, 0x3022 },
       
  1552 		{ 0x04, 0x2800 },
       
  1553 		{ 0x1f, 0x0000 },
       
  1554 
       
  1555 		{ 0x1f, 0x0001 },
       
  1556 		{ 0x17, 0x0cc0 },
       
  1557 		{ 0x1f, 0x0000 }
       
  1558 	};
       
  1559 
       
  1560 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1561 }
       
  1562 
       
  1563 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
       
  1564 {
       
  1565 	static const struct phy_reg phy_reg_init[] = {
       
  1566 		{ 0x10, 0xf41b },
       
  1567 		{ 0x1f, 0x0000 }
       
  1568 	};
       
  1569 
       
  1570 	mdio_write(ioaddr, 0x1f, 0x0001);
       
  1571 	mdio_patch(ioaddr, 0x16, 1 << 0);
       
  1572 
       
  1573 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1574 }
       
  1575 
       
  1576 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
       
  1577 {
       
  1578 	static const struct phy_reg phy_reg_init[] = {
       
  1579 		{ 0x1f, 0x0001 },
       
  1580 		{ 0x10, 0xf41b },
       
  1581 		{ 0x1f, 0x0000 }
       
  1582 	};
       
  1583 
       
  1584 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1585 }
       
  1586 
       
  1587 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
       
  1588 {
       
  1589 	static const struct phy_reg phy_reg_init[] = {
       
  1590 		{ 0x1f, 0x0000 },
       
  1591 		{ 0x1d, 0x0f00 },
       
  1592 		{ 0x1f, 0x0002 },
       
  1593 		{ 0x0c, 0x1ec8 },
       
  1594 		{ 0x1f, 0x0000 }
       
  1595 	};
       
  1596 
       
  1597 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1598 }
       
  1599 
       
  1600 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
       
  1601 {
       
  1602 	static const struct phy_reg phy_reg_init[] = {
       
  1603 		{ 0x1f, 0x0001 },
       
  1604 		{ 0x1d, 0x3d98 },
       
  1605 		{ 0x1f, 0x0000 }
       
  1606 	};
       
  1607 
       
  1608 	mdio_write(ioaddr, 0x1f, 0x0000);
       
  1609 	mdio_patch(ioaddr, 0x14, 1 << 5);
       
  1610 	mdio_patch(ioaddr, 0x0d, 1 << 5);
       
  1611 
       
  1612 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1613 }
       
  1614 
       
  1615 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
       
  1616 {
       
  1617 	static const struct phy_reg phy_reg_init[] = {
       
  1618 		{ 0x1f, 0x0001 },
       
  1619 		{ 0x12, 0x2300 },
       
  1620 		{ 0x1f, 0x0002 },
       
  1621 		{ 0x00, 0x88d4 },
       
  1622 		{ 0x01, 0x82b1 },
       
  1623 		{ 0x03, 0x7002 },
       
  1624 		{ 0x08, 0x9e30 },
       
  1625 		{ 0x09, 0x01f0 },
       
  1626 		{ 0x0a, 0x5500 },
       
  1627 		{ 0x0c, 0x00c8 },
       
  1628 		{ 0x1f, 0x0003 },
       
  1629 		{ 0x12, 0xc096 },
       
  1630 		{ 0x16, 0x000a },
       
  1631 		{ 0x1f, 0x0000 },
       
  1632 		{ 0x1f, 0x0000 },
       
  1633 		{ 0x09, 0x2000 },
       
  1634 		{ 0x09, 0x0000 }
       
  1635 	};
       
  1636 
       
  1637 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1638 
       
  1639 	mdio_patch(ioaddr, 0x14, 1 << 5);
       
  1640 	mdio_patch(ioaddr, 0x0d, 1 << 5);
       
  1641 	mdio_write(ioaddr, 0x1f, 0x0000);
       
  1642 }
       
  1643 
       
  1644 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
       
  1645 {
       
  1646 	static const struct phy_reg phy_reg_init[] = {
       
  1647 		{ 0x1f, 0x0001 },
       
  1648 		{ 0x12, 0x2300 },
       
  1649 		{ 0x03, 0x802f },
       
  1650 		{ 0x02, 0x4f02 },
       
  1651 		{ 0x01, 0x0409 },
       
  1652 		{ 0x00, 0xf099 },
       
  1653 		{ 0x04, 0x9800 },
       
  1654 		{ 0x04, 0x9000 },
       
  1655 		{ 0x1d, 0x3d98 },
       
  1656 		{ 0x1f, 0x0002 },
       
  1657 		{ 0x0c, 0x7eb8 },
       
  1658 		{ 0x06, 0x0761 },
       
  1659 		{ 0x1f, 0x0003 },
       
  1660 		{ 0x16, 0x0f0a },
       
  1661 		{ 0x1f, 0x0000 }
       
  1662 	};
       
  1663 
       
  1664 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1665 
       
  1666 	mdio_patch(ioaddr, 0x16, 1 << 0);
       
  1667 	mdio_patch(ioaddr, 0x14, 1 << 5);
       
  1668 	mdio_patch(ioaddr, 0x0d, 1 << 5);
       
  1669 	mdio_write(ioaddr, 0x1f, 0x0000);
       
  1670 }
       
  1671 
       
  1672 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
       
  1673 {
       
  1674 	static const struct phy_reg phy_reg_init[] = {
       
  1675 		{ 0x1f, 0x0001 },
       
  1676 		{ 0x12, 0x2300 },
       
  1677 		{ 0x1d, 0x3d98 },
       
  1678 		{ 0x1f, 0x0002 },
       
  1679 		{ 0x0c, 0x7eb8 },
       
  1680 		{ 0x06, 0x5461 },
       
  1681 		{ 0x1f, 0x0003 },
       
  1682 		{ 0x16, 0x0f0a },
       
  1683 		{ 0x1f, 0x0000 }
       
  1684 	};
       
  1685 
       
  1686 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  1687 
       
  1688 	mdio_patch(ioaddr, 0x16, 1 << 0);
       
  1689 	mdio_patch(ioaddr, 0x14, 1 << 5);
       
  1690 	mdio_patch(ioaddr, 0x0d, 1 << 5);
       
  1691 	mdio_write(ioaddr, 0x1f, 0x0000);
       
  1692 }
       
  1693 
       
  1694 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
       
  1695 {
       
  1696 	rtl8168c_3_hw_phy_config(ioaddr);
       
  1697 }
       
  1698 
       
  1699 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
       
  1700 {
       
  1701 	static const struct phy_reg phy_reg_init_0[] = {
       
  1702 		{ 0x1f, 0x0001 },
       
  1703 		{ 0x06, 0x4064 },
       
  1704 		{ 0x07, 0x2863 },
       
  1705 		{ 0x08, 0x059c },
       
  1706 		{ 0x09, 0x26b4 },
       
  1707 		{ 0x0a, 0x6a19 },
       
  1708 		{ 0x0b, 0xdcc8 },
       
  1709 		{ 0x10, 0xf06d },
       
  1710 		{ 0x14, 0x7f68 },
       
  1711 		{ 0x18, 0x7fd9 },
       
  1712 		{ 0x1c, 0xf0ff },
       
  1713 		{ 0x1d, 0x3d9c },
       
  1714 		{ 0x1f, 0x0003 },
       
  1715 		{ 0x12, 0xf49f },
       
  1716 		{ 0x13, 0x070b },
       
  1717 		{ 0x1a, 0x05ad },
       
  1718 		{ 0x14, 0x94c0 }
       
  1719 	};
       
  1720 	static const struct phy_reg phy_reg_init_1[] = {
       
  1721 		{ 0x1f, 0x0002 },
       
  1722 		{ 0x06, 0x5561 },
       
  1723 		{ 0x1f, 0x0005 },
       
  1724 		{ 0x05, 0x8332 },
       
  1725 		{ 0x06, 0x5561 }
       
  1726 	};
       
  1727 	static const struct phy_reg phy_reg_init_2[] = {
       
  1728 		{ 0x1f, 0x0005 },
       
  1729 		{ 0x05, 0xffc2 },
       
  1730 		{ 0x1f, 0x0005 },
       
  1731 		{ 0x05, 0x8000 },
       
  1732 		{ 0x06, 0xf8f9 },
       
  1733 		{ 0x06, 0xfaef },
       
  1734 		{ 0x06, 0x59ee },
       
  1735 		{ 0x06, 0xf8ea },
       
  1736 		{ 0x06, 0x00ee },
       
  1737 		{ 0x06, 0xf8eb },
       
  1738 		{ 0x06, 0x00e0 },
       
  1739 		{ 0x06, 0xf87c },
       
  1740 		{ 0x06, 0xe1f8 },
       
  1741 		{ 0x06, 0x7d59 },
       
  1742 		{ 0x06, 0x0fef },
       
  1743 		{ 0x06, 0x0139 },
       
  1744 		{ 0x06, 0x029e },
       
  1745 		{ 0x06, 0x06ef },
       
  1746 		{ 0x06, 0x1039 },
       
  1747 		{ 0x06, 0x089f },
       
  1748 		{ 0x06, 0x2aee },
       
  1749 		{ 0x06, 0xf8ea },
       
  1750 		{ 0x06, 0x00ee },
       
  1751 		{ 0x06, 0xf8eb },
       
  1752 		{ 0x06, 0x01e0 },
       
  1753 		{ 0x06, 0xf87c },
       
  1754 		{ 0x06, 0xe1f8 },
       
  1755 		{ 0x06, 0x7d58 },
       
  1756 		{ 0x06, 0x409e },
       
  1757 		{ 0x06, 0x0f39 },
       
  1758 		{ 0x06, 0x46aa },
       
  1759 		{ 0x06, 0x0bbf },
       
  1760 		{ 0x06, 0x8290 },
       
  1761 		{ 0x06, 0xd682 },
       
  1762 		{ 0x06, 0x9802 },
       
  1763 		{ 0x06, 0x014f },
       
  1764 		{ 0x06, 0xae09 },
       
  1765 		{ 0x06, 0xbf82 },
       
  1766 		{ 0x06, 0x98d6 },
       
  1767 		{ 0x06, 0x82a0 },
       
  1768 		{ 0x06, 0x0201 },
       
  1769 		{ 0x06, 0x4fef },
       
  1770 		{ 0x06, 0x95fe },
       
  1771 		{ 0x06, 0xfdfc },
       
  1772 		{ 0x06, 0x05f8 },
       
  1773 		{ 0x06, 0xf9fa },
       
  1774 		{ 0x06, 0xeef8 },
       
  1775 		{ 0x06, 0xea00 },
       
  1776 		{ 0x06, 0xeef8 },
       
  1777 		{ 0x06, 0xeb00 },
       
  1778 		{ 0x06, 0xe2f8 },
       
  1779 		{ 0x06, 0x7ce3 },
       
  1780 		{ 0x06, 0xf87d },
       
  1781 		{ 0x06, 0xa511 },
       
  1782 		{ 0x06, 0x1112 },
       
  1783 		{ 0x06, 0xd240 },
       
  1784 		{ 0x06, 0xd644 },
       
  1785 		{ 0x06, 0x4402 },
       
  1786 		{ 0x06, 0x8217 },
       
  1787 		{ 0x06, 0xd2a0 },
       
  1788 		{ 0x06, 0xd6aa },
       
  1789 		{ 0x06, 0xaa02 },
       
  1790 		{ 0x06, 0x8217 },
       
  1791 		{ 0x06, 0xae0f },
       
  1792 		{ 0x06, 0xa544 },
       
  1793 		{ 0x06, 0x4402 },
       
  1794 		{ 0x06, 0xae4d },
       
  1795 		{ 0x06, 0xa5aa },
       
  1796 		{ 0x06, 0xaa02 },
       
  1797 		{ 0x06, 0xae47 },
       
  1798 		{ 0x06, 0xaf82 },
       
  1799 		{ 0x06, 0x13ee },
       
  1800 		{ 0x06, 0x834e },
       
  1801 		{ 0x06, 0x00ee },
       
  1802 		{ 0x06, 0x834d },
       
  1803 		{ 0x06, 0x0fee },
       
  1804 		{ 0x06, 0x834c },
       
  1805 		{ 0x06, 0x0fee },
       
  1806 		{ 0x06, 0x834f },
       
  1807 		{ 0x06, 0x00ee },
       
  1808 		{ 0x06, 0x8351 },
       
  1809 		{ 0x06, 0x00ee },
       
  1810 		{ 0x06, 0x834a },
       
  1811 		{ 0x06, 0xffee },
       
  1812 		{ 0x06, 0x834b },
       
  1813 		{ 0x06, 0xffe0 },
       
  1814 		{ 0x06, 0x8330 },
       
  1815 		{ 0x06, 0xe183 },
       
  1816 		{ 0x06, 0x3158 },
       
  1817 		{ 0x06, 0xfee4 },
       
  1818 		{ 0x06, 0xf88a },
       
  1819 		{ 0x06, 0xe5f8 },
       
  1820 		{ 0x06, 0x8be0 },
       
  1821 		{ 0x06, 0x8332 },
       
  1822 		{ 0x06, 0xe183 },
       
  1823 		{ 0x06, 0x3359 },
       
  1824 		{ 0x06, 0x0fe2 },
       
  1825 		{ 0x06, 0x834d },
       
  1826 		{ 0x06, 0x0c24 },
       
  1827 		{ 0x06, 0x5af0 },
       
  1828 		{ 0x06, 0x1e12 },
       
  1829 		{ 0x06, 0xe4f8 },
       
  1830 		{ 0x06, 0x8ce5 },
       
  1831 		{ 0x06, 0xf88d },
       
  1832 		{ 0x06, 0xaf82 },
       
  1833 		{ 0x06, 0x13e0 },
       
  1834 		{ 0x06, 0x834f },
       
  1835 		{ 0x06, 0x10e4 },
       
  1836 		{ 0x06, 0x834f },
       
  1837 		{ 0x06, 0xe083 },
       
  1838 		{ 0x06, 0x4e78 },
       
  1839 		{ 0x06, 0x009f },
       
  1840 		{ 0x06, 0x0ae0 },
       
  1841 		{ 0x06, 0x834f },
       
  1842 		{ 0x06, 0xa010 },
       
  1843 		{ 0x06, 0xa5ee },
       
  1844 		{ 0x06, 0x834e },
       
  1845 		{ 0x06, 0x01e0 },
       
  1846 		{ 0x06, 0x834e },
       
  1847 		{ 0x06, 0x7805 },
       
  1848 		{ 0x06, 0x9e9a },
       
  1849 		{ 0x06, 0xe083 },
       
  1850 		{ 0x06, 0x4e78 },
       
  1851 		{ 0x06, 0x049e },
       
  1852 		{ 0x06, 0x10e0 },
       
  1853 		{ 0x06, 0x834e },
       
  1854 		{ 0x06, 0x7803 },
       
  1855 		{ 0x06, 0x9e0f },
       
  1856 		{ 0x06, 0xe083 },
       
  1857 		{ 0x06, 0x4e78 },
       
  1858 		{ 0x06, 0x019e },
       
  1859 		{ 0x06, 0x05ae },
       
  1860 		{ 0x06, 0x0caf },
       
  1861 		{ 0x06, 0x81f8 },
       
  1862 		{ 0x06, 0xaf81 },
       
  1863 		{ 0x06, 0xa3af },
       
  1864 		{ 0x06, 0x81dc },
       
  1865 		{ 0x06, 0xaf82 },
       
  1866 		{ 0x06, 0x13ee },
       
  1867 		{ 0x06, 0x8348 },
       
  1868 		{ 0x06, 0x00ee },
       
  1869 		{ 0x06, 0x8349 },
       
  1870 		{ 0x06, 0x00e0 },
       
  1871 		{ 0x06, 0x8351 },
       
  1872 		{ 0x06, 0x10e4 },
       
  1873 		{ 0x06, 0x8351 },
       
  1874 		{ 0x06, 0x5801 },
       
  1875 		{ 0x06, 0x9fea },
       
  1876 		{ 0x06, 0xd000 },
       
  1877 		{ 0x06, 0xd180 },
       
  1878 		{ 0x06, 0x1f66 },
       
  1879 		{ 0x06, 0xe2f8 },
       
  1880 		{ 0x06, 0xeae3 },
       
  1881 		{ 0x06, 0xf8eb },
       
  1882 		{ 0x06, 0x5af8 },
       
  1883 		{ 0x06, 0x1e20 },
       
  1884 		{ 0x06, 0xe6f8 },
       
  1885 		{ 0x06, 0xeae5 },
       
  1886 		{ 0x06, 0xf8eb },
       
  1887 		{ 0x06, 0xd302 },
       
  1888 		{ 0x06, 0xb3fe },
       
  1889 		{ 0x06, 0xe2f8 },
       
  1890 		{ 0x06, 0x7cef },
       
  1891 		{ 0x06, 0x325b },
       
  1892 		{ 0x06, 0x80e3 },
       
  1893 		{ 0x06, 0xf87d },
       
  1894 		{ 0x06, 0x9e03 },
       
  1895 		{ 0x06, 0x7dff },
       
  1896 		{ 0x06, 0xff0d },
       
  1897 		{ 0x06, 0x581c },
       
  1898 		{ 0x06, 0x551a },
       
  1899 		{ 0x06, 0x6511 },
       
  1900 		{ 0x06, 0xa190 },
       
  1901 		{ 0x06, 0xd3e2 },
       
  1902 		{ 0x06, 0x8348 },
       
  1903 		{ 0x06, 0xe383 },
       
  1904 		{ 0x06, 0x491b },
       
  1905 		{ 0x06, 0x56ab },
       
  1906 		{ 0x06, 0x08ef },
       
  1907 		{ 0x06, 0x56e6 },
       
  1908 		{ 0x06, 0x8348 },
       
  1909 		{ 0x06, 0xe783 },
       
  1910 		{ 0x06, 0x4910 },
       
  1911 		{ 0x06, 0xd180 },
       
  1912 		{ 0x06, 0x1f66 },
       
  1913 		{ 0x06, 0xa004 },
       
  1914 		{ 0x06, 0xb9e2 },
       
  1915 		{ 0x06, 0x8348 },
       
  1916 		{ 0x06, 0xe383 },
       
  1917 		{ 0x06, 0x49ef },
       
  1918 		{ 0x06, 0x65e2 },
       
  1919 		{ 0x06, 0x834a },
       
  1920 		{ 0x06, 0xe383 },
       
  1921 		{ 0x06, 0x4b1b },
       
  1922 		{ 0x06, 0x56aa },
       
  1923 		{ 0x06, 0x0eef },
       
  1924 		{ 0x06, 0x56e6 },
       
  1925 		{ 0x06, 0x834a },
       
  1926 		{ 0x06, 0xe783 },
       
  1927 		{ 0x06, 0x4be2 },
       
  1928 		{ 0x06, 0x834d },
       
  1929 		{ 0x06, 0xe683 },
       
  1930 		{ 0x06, 0x4ce0 },
       
  1931 		{ 0x06, 0x834d },
       
  1932 		{ 0x06, 0xa000 },
       
  1933 		{ 0x06, 0x0caf },
       
  1934 		{ 0x06, 0x81dc },
       
  1935 		{ 0x06, 0xe083 },
       
  1936 		{ 0x06, 0x4d10 },
       
  1937 		{ 0x06, 0xe483 },
       
  1938 		{ 0x06, 0x4dae },
       
  1939 		{ 0x06, 0x0480 },
       
  1940 		{ 0x06, 0xe483 },
       
  1941 		{ 0x06, 0x4de0 },
       
  1942 		{ 0x06, 0x834e },
       
  1943 		{ 0x06, 0x7803 },
       
  1944 		{ 0x06, 0x9e0b },
       
  1945 		{ 0x06, 0xe083 },
       
  1946 		{ 0x06, 0x4e78 },
       
  1947 		{ 0x06, 0x049e },
       
  1948 		{ 0x06, 0x04ee },
       
  1949 		{ 0x06, 0x834e },
       
  1950 		{ 0x06, 0x02e0 },
       
  1951 		{ 0x06, 0x8332 },
       
  1952 		{ 0x06, 0xe183 },
       
  1953 		{ 0x06, 0x3359 },
       
  1954 		{ 0x06, 0x0fe2 },
       
  1955 		{ 0x06, 0x834d },
       
  1956 		{ 0x06, 0x0c24 },
       
  1957 		{ 0x06, 0x5af0 },
       
  1958 		{ 0x06, 0x1e12 },
       
  1959 		{ 0x06, 0xe4f8 },
       
  1960 		{ 0x06, 0x8ce5 },
       
  1961 		{ 0x06, 0xf88d },
       
  1962 		{ 0x06, 0xe083 },
       
  1963 		{ 0x06, 0x30e1 },
       
  1964 		{ 0x06, 0x8331 },
       
  1965 		{ 0x06, 0x6801 },
       
  1966 		{ 0x06, 0xe4f8 },
       
  1967 		{ 0x06, 0x8ae5 },
       
  1968 		{ 0x06, 0xf88b },
       
  1969 		{ 0x06, 0xae37 },
       
  1970 		{ 0x06, 0xee83 },
       
  1971 		{ 0x06, 0x4e03 },
       
  1972 		{ 0x06, 0xe083 },
       
  1973 		{ 0x06, 0x4ce1 },
       
  1974 		{ 0x06, 0x834d },
       
  1975 		{ 0x06, 0x1b01 },
       
  1976 		{ 0x06, 0x9e04 },
       
  1977 		{ 0x06, 0xaaa1 },
       
  1978 		{ 0x06, 0xaea8 },
       
  1979 		{ 0x06, 0xee83 },
       
  1980 		{ 0x06, 0x4e04 },
       
  1981 		{ 0x06, 0xee83 },
       
  1982 		{ 0x06, 0x4f00 },
       
  1983 		{ 0x06, 0xaeab },
       
  1984 		{ 0x06, 0xe083 },
       
  1985 		{ 0x06, 0x4f78 },
       
  1986 		{ 0x06, 0x039f },
       
  1987 		{ 0x06, 0x14ee },
       
  1988 		{ 0x06, 0x834e },
       
  1989 		{ 0x06, 0x05d2 },
       
  1990 		{ 0x06, 0x40d6 },
       
  1991 		{ 0x06, 0x5554 },
       
  1992 		{ 0x06, 0x0282 },
       
  1993 		{ 0x06, 0x17d2 },
       
  1994 		{ 0x06, 0xa0d6 },
       
  1995 		{ 0x06, 0xba00 },
       
  1996 		{ 0x06, 0x0282 },
       
  1997 		{ 0x06, 0x17fe },
       
  1998 		{ 0x06, 0xfdfc },
       
  1999 		{ 0x06, 0x05f8 },
       
  2000 		{ 0x06, 0xe0f8 },
       
  2001 		{ 0x06, 0x60e1 },
       
  2002 		{ 0x06, 0xf861 },
       
  2003 		{ 0x06, 0x6802 },
       
  2004 		{ 0x06, 0xe4f8 },
       
  2005 		{ 0x06, 0x60e5 },
       
  2006 		{ 0x06, 0xf861 },
       
  2007 		{ 0x06, 0xe0f8 },
       
  2008 		{ 0x06, 0x48e1 },
       
  2009 		{ 0x06, 0xf849 },
       
  2010 		{ 0x06, 0x580f },
       
  2011 		{ 0x06, 0x1e02 },
       
  2012 		{ 0x06, 0xe4f8 },
       
  2013 		{ 0x06, 0x48e5 },
       
  2014 		{ 0x06, 0xf849 },
       
  2015 		{ 0x06, 0xd000 },
       
  2016 		{ 0x06, 0x0282 },
       
  2017 		{ 0x06, 0x5bbf },
       
  2018 		{ 0x06, 0x8350 },
       
  2019 		{ 0x06, 0xef46 },
       
  2020 		{ 0x06, 0xdc19 },
       
  2021 		{ 0x06, 0xddd0 },
       
  2022 		{ 0x06, 0x0102 },
       
  2023 		{ 0x06, 0x825b },
       
  2024 		{ 0x06, 0x0282 },
       
  2025 		{ 0x06, 0x77e0 },
       
  2026 		{ 0x06, 0xf860 },
       
  2027 		{ 0x06, 0xe1f8 },
       
  2028 		{ 0x06, 0x6158 },
       
  2029 		{ 0x06, 0xfde4 },
       
  2030 		{ 0x06, 0xf860 },
       
  2031 		{ 0x06, 0xe5f8 },
       
  2032 		{ 0x06, 0x61fc },
       
  2033 		{ 0x06, 0x04f9 },
       
  2034 		{ 0x06, 0xfafb },
       
  2035 		{ 0x06, 0xc6bf },
       
  2036 		{ 0x06, 0xf840 },
       
  2037 		{ 0x06, 0xbe83 },
       
  2038 		{ 0x06, 0x50a0 },
       
  2039 		{ 0x06, 0x0101 },
       
  2040 		{ 0x06, 0x071b },
       
  2041 		{ 0x06, 0x89cf },
       
  2042 		{ 0x06, 0xd208 },
       
  2043 		{ 0x06, 0xebdb },
       
  2044 		{ 0x06, 0x19b2 },
       
  2045 		{ 0x06, 0xfbff },
       
  2046 		{ 0x06, 0xfefd },
       
  2047 		{ 0x06, 0x04f8 },
       
  2048 		{ 0x06, 0xe0f8 },
       
  2049 		{ 0x06, 0x48e1 },
       
  2050 		{ 0x06, 0xf849 },
       
  2051 		{ 0x06, 0x6808 },
       
  2052 		{ 0x06, 0xe4f8 },
       
  2053 		{ 0x06, 0x48e5 },
       
  2054 		{ 0x06, 0xf849 },
       
  2055 		{ 0x06, 0x58f7 },
       
  2056 		{ 0x06, 0xe4f8 },
       
  2057 		{ 0x06, 0x48e5 },
       
  2058 		{ 0x06, 0xf849 },
       
  2059 		{ 0x06, 0xfc04 },
       
  2060 		{ 0x06, 0x4d20 },
       
  2061 		{ 0x06, 0x0002 },
       
  2062 		{ 0x06, 0x4e22 },
       
  2063 		{ 0x06, 0x0002 },
       
  2064 		{ 0x06, 0x4ddf },
       
  2065 		{ 0x06, 0xff01 },
       
  2066 		{ 0x06, 0x4edd },
       
  2067 		{ 0x06, 0xff01 },
       
  2068 		{ 0x05, 0x83d4 },
       
  2069 		{ 0x06, 0x8000 },
       
  2070 		{ 0x05, 0x83d8 },
       
  2071 		{ 0x06, 0x8051 },
       
  2072 		{ 0x02, 0x6010 },
       
  2073 		{ 0x03, 0xdc00 },
       
  2074 		{ 0x05, 0xfff6 },
       
  2075 		{ 0x06, 0x00fc },
       
  2076 		{ 0x1f, 0x0000 },
       
  2077 
       
  2078 		{ 0x1f, 0x0000 },
       
  2079 		{ 0x0d, 0xf880 },
       
  2080 		{ 0x1f, 0x0000 }
       
  2081 	};
       
  2082 
       
  2083 	rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
       
  2084 
       
  2085 	mdio_write(ioaddr, 0x1f, 0x0002);
       
  2086 	mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
       
  2087 	mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
       
  2088 
       
  2089 	rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
       
  2090 
       
  2091 	if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
       
  2092 		static const struct phy_reg phy_reg_init[] = {
       
  2093 			{ 0x1f, 0x0002 },
       
  2094 			{ 0x05, 0x669a },
       
  2095 			{ 0x1f, 0x0005 },
       
  2096 			{ 0x05, 0x8330 },
       
  2097 			{ 0x06, 0x669a },
       
  2098 			{ 0x1f, 0x0002 }
       
  2099 		};
       
  2100 		int val;
       
  2101 
       
  2102 		rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2103 
       
  2104 		val = mdio_read(ioaddr, 0x0d);
       
  2105 
       
  2106 		if ((val & 0x00ff) != 0x006c) {
       
  2107 			static const u32 set[] = {
       
  2108 				0x0065, 0x0066, 0x0067, 0x0068,
       
  2109 				0x0069, 0x006a, 0x006b, 0x006c
       
  2110 			};
       
  2111 			int i;
       
  2112 
       
  2113 			mdio_write(ioaddr, 0x1f, 0x0002);
       
  2114 
       
  2115 			val &= 0xff00;
       
  2116 			for (i = 0; i < ARRAY_SIZE(set); i++)
       
  2117 				mdio_write(ioaddr, 0x0d, val | set[i]);
       
  2118 		}
       
  2119 	} else {
       
  2120 		static const struct phy_reg phy_reg_init[] = {
       
  2121 			{ 0x1f, 0x0002 },
       
  2122 			{ 0x05, 0x6662 },
       
  2123 			{ 0x1f, 0x0005 },
       
  2124 			{ 0x05, 0x8330 },
       
  2125 			{ 0x06, 0x6662 }
       
  2126 		};
       
  2127 
       
  2128 		rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2129 	}
       
  2130 
       
  2131 	mdio_write(ioaddr, 0x1f, 0x0002);
       
  2132 	mdio_patch(ioaddr, 0x0d, 0x0300);
       
  2133 	mdio_patch(ioaddr, 0x0f, 0x0010);
       
  2134 
       
  2135 	mdio_write(ioaddr, 0x1f, 0x0002);
       
  2136 	mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
       
  2137 	mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
       
  2138 
       
  2139 	rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
       
  2140 }
       
  2141 
       
  2142 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
       
  2143 {
       
  2144 	static const struct phy_reg phy_reg_init_0[] = {
       
  2145 		{ 0x1f, 0x0001 },
       
  2146 		{ 0x06, 0x4064 },
       
  2147 		{ 0x07, 0x2863 },
       
  2148 		{ 0x08, 0x059c },
       
  2149 		{ 0x09, 0x26b4 },
       
  2150 		{ 0x0a, 0x6a19 },
       
  2151 		{ 0x0b, 0xdcc8 },
       
  2152 		{ 0x10, 0xf06d },
       
  2153 		{ 0x14, 0x7f68 },
       
  2154 		{ 0x18, 0x7fd9 },
       
  2155 		{ 0x1c, 0xf0ff },
       
  2156 		{ 0x1d, 0x3d9c },
       
  2157 		{ 0x1f, 0x0003 },
       
  2158 		{ 0x12, 0xf49f },
       
  2159 		{ 0x13, 0x070b },
       
  2160 		{ 0x1a, 0x05ad },
       
  2161 		{ 0x14, 0x94c0 },
       
  2162 
       
  2163 		{ 0x1f, 0x0002 },
       
  2164 		{ 0x06, 0x5561 },
       
  2165 		{ 0x1f, 0x0005 },
       
  2166 		{ 0x05, 0x8332 },
       
  2167 		{ 0x06, 0x5561 }
       
  2168 	};
       
  2169 	static const struct phy_reg phy_reg_init_1[] = {
       
  2170 		{ 0x1f, 0x0005 },
       
  2171 		{ 0x05, 0xffc2 },
       
  2172 		{ 0x1f, 0x0005 },
       
  2173 		{ 0x05, 0x8000 },
       
  2174 		{ 0x06, 0xf8f9 },
       
  2175 		{ 0x06, 0xfaee },
       
  2176 		{ 0x06, 0xf8ea },
       
  2177 		{ 0x06, 0x00ee },
       
  2178 		{ 0x06, 0xf8eb },
       
  2179 		{ 0x06, 0x00e2 },
       
  2180 		{ 0x06, 0xf87c },
       
  2181 		{ 0x06, 0xe3f8 },
       
  2182 		{ 0x06, 0x7da5 },
       
  2183 		{ 0x06, 0x1111 },
       
  2184 		{ 0x06, 0x12d2 },
       
  2185 		{ 0x06, 0x40d6 },
       
  2186 		{ 0x06, 0x4444 },
       
  2187 		{ 0x06, 0x0281 },
       
  2188 		{ 0x06, 0xc6d2 },
       
  2189 		{ 0x06, 0xa0d6 },
       
  2190 		{ 0x06, 0xaaaa },
       
  2191 		{ 0x06, 0x0281 },
       
  2192 		{ 0x06, 0xc6ae },
       
  2193 		{ 0x06, 0x0fa5 },
       
  2194 		{ 0x06, 0x4444 },
       
  2195 		{ 0x06, 0x02ae },
       
  2196 		{ 0x06, 0x4da5 },
       
  2197 		{ 0x06, 0xaaaa },
       
  2198 		{ 0x06, 0x02ae },
       
  2199 		{ 0x06, 0x47af },
       
  2200 		{ 0x06, 0x81c2 },
       
  2201 		{ 0x06, 0xee83 },
       
  2202 		{ 0x06, 0x4e00 },
       
  2203 		{ 0x06, 0xee83 },
       
  2204 		{ 0x06, 0x4d0f },
       
  2205 		{ 0x06, 0xee83 },
       
  2206 		{ 0x06, 0x4c0f },
       
  2207 		{ 0x06, 0xee83 },
       
  2208 		{ 0x06, 0x4f00 },
       
  2209 		{ 0x06, 0xee83 },
       
  2210 		{ 0x06, 0x5100 },
       
  2211 		{ 0x06, 0xee83 },
       
  2212 		{ 0x06, 0x4aff },
       
  2213 		{ 0x06, 0xee83 },
       
  2214 		{ 0x06, 0x4bff },
       
  2215 		{ 0x06, 0xe083 },
       
  2216 		{ 0x06, 0x30e1 },
       
  2217 		{ 0x06, 0x8331 },
       
  2218 		{ 0x06, 0x58fe },
       
  2219 		{ 0x06, 0xe4f8 },
       
  2220 		{ 0x06, 0x8ae5 },
       
  2221 		{ 0x06, 0xf88b },
       
  2222 		{ 0x06, 0xe083 },
       
  2223 		{ 0x06, 0x32e1 },
       
  2224 		{ 0x06, 0x8333 },
       
  2225 		{ 0x06, 0x590f },
       
  2226 		{ 0x06, 0xe283 },
       
  2227 		{ 0x06, 0x4d0c },
       
  2228 		{ 0x06, 0x245a },
       
  2229 		{ 0x06, 0xf01e },
       
  2230 		{ 0x06, 0x12e4 },
       
  2231 		{ 0x06, 0xf88c },
       
  2232 		{ 0x06, 0xe5f8 },
       
  2233 		{ 0x06, 0x8daf },
       
  2234 		{ 0x06, 0x81c2 },
       
  2235 		{ 0x06, 0xe083 },
       
  2236 		{ 0x06, 0x4f10 },
       
  2237 		{ 0x06, 0xe483 },
       
  2238 		{ 0x06, 0x4fe0 },
       
  2239 		{ 0x06, 0x834e },
       
  2240 		{ 0x06, 0x7800 },
       
  2241 		{ 0x06, 0x9f0a },
       
  2242 		{ 0x06, 0xe083 },
       
  2243 		{ 0x06, 0x4fa0 },
       
  2244 		{ 0x06, 0x10a5 },
       
  2245 		{ 0x06, 0xee83 },
       
  2246 		{ 0x06, 0x4e01 },
       
  2247 		{ 0x06, 0xe083 },
       
  2248 		{ 0x06, 0x4e78 },
       
  2249 		{ 0x06, 0x059e },
       
  2250 		{ 0x06, 0x9ae0 },
       
  2251 		{ 0x06, 0x834e },
       
  2252 		{ 0x06, 0x7804 },
       
  2253 		{ 0x06, 0x9e10 },
       
  2254 		{ 0x06, 0xe083 },
       
  2255 		{ 0x06, 0x4e78 },
       
  2256 		{ 0x06, 0x039e },
       
  2257 		{ 0x06, 0x0fe0 },
       
  2258 		{ 0x06, 0x834e },
       
  2259 		{ 0x06, 0x7801 },
       
  2260 		{ 0x06, 0x9e05 },
       
  2261 		{ 0x06, 0xae0c },
       
  2262 		{ 0x06, 0xaf81 },
       
  2263 		{ 0x06, 0xa7af },
       
  2264 		{ 0x06, 0x8152 },
       
  2265 		{ 0x06, 0xaf81 },
       
  2266 		{ 0x06, 0x8baf },
       
  2267 		{ 0x06, 0x81c2 },
       
  2268 		{ 0x06, 0xee83 },
       
  2269 		{ 0x06, 0x4800 },
       
  2270 		{ 0x06, 0xee83 },
       
  2271 		{ 0x06, 0x4900 },
       
  2272 		{ 0x06, 0xe083 },
       
  2273 		{ 0x06, 0x5110 },
       
  2274 		{ 0x06, 0xe483 },
       
  2275 		{ 0x06, 0x5158 },
       
  2276 		{ 0x06, 0x019f },
       
  2277 		{ 0x06, 0xead0 },
       
  2278 		{ 0x06, 0x00d1 },
       
  2279 		{ 0x06, 0x801f },
       
  2280 		{ 0x06, 0x66e2 },
       
  2281 		{ 0x06, 0xf8ea },
       
  2282 		{ 0x06, 0xe3f8 },
       
  2283 		{ 0x06, 0xeb5a },
       
  2284 		{ 0x06, 0xf81e },
       
  2285 		{ 0x06, 0x20e6 },
       
  2286 		{ 0x06, 0xf8ea },
       
  2287 		{ 0x06, 0xe5f8 },
       
  2288 		{ 0x06, 0xebd3 },
       
  2289 		{ 0x06, 0x02b3 },
       
  2290 		{ 0x06, 0xfee2 },
       
  2291 		{ 0x06, 0xf87c },
       
  2292 		{ 0x06, 0xef32 },
       
  2293 		{ 0x06, 0x5b80 },
       
  2294 		{ 0x06, 0xe3f8 },
       
  2295 		{ 0x06, 0x7d9e },
       
  2296 		{ 0x06, 0x037d },
       
  2297 		{ 0x06, 0xffff },
       
  2298 		{ 0x06, 0x0d58 },
       
  2299 		{ 0x06, 0x1c55 },
       
  2300 		{ 0x06, 0x1a65 },
       
  2301 		{ 0x06, 0x11a1 },
       
  2302 		{ 0x06, 0x90d3 },
       
  2303 		{ 0x06, 0xe283 },
       
  2304 		{ 0x06, 0x48e3 },
       
  2305 		{ 0x06, 0x8349 },
       
  2306 		{ 0x06, 0x1b56 },
       
  2307 		{ 0x06, 0xab08 },
       
  2308 		{ 0x06, 0xef56 },
       
  2309 		{ 0x06, 0xe683 },
       
  2310 		{ 0x06, 0x48e7 },
       
  2311 		{ 0x06, 0x8349 },
       
  2312 		{ 0x06, 0x10d1 },
       
  2313 		{ 0x06, 0x801f },
       
  2314 		{ 0x06, 0x66a0 },
       
  2315 		{ 0x06, 0x04b9 },
       
  2316 		{ 0x06, 0xe283 },
       
  2317 		{ 0x06, 0x48e3 },
       
  2318 		{ 0x06, 0x8349 },
       
  2319 		{ 0x06, 0xef65 },
       
  2320 		{ 0x06, 0xe283 },
       
  2321 		{ 0x06, 0x4ae3 },
       
  2322 		{ 0x06, 0x834b },
       
  2323 		{ 0x06, 0x1b56 },
       
  2324 		{ 0x06, 0xaa0e },
       
  2325 		{ 0x06, 0xef56 },
       
  2326 		{ 0x06, 0xe683 },
       
  2327 		{ 0x06, 0x4ae7 },
       
  2328 		{ 0x06, 0x834b },
       
  2329 		{ 0x06, 0xe283 },
       
  2330 		{ 0x06, 0x4de6 },
       
  2331 		{ 0x06, 0x834c },
       
  2332 		{ 0x06, 0xe083 },
       
  2333 		{ 0x06, 0x4da0 },
       
  2334 		{ 0x06, 0x000c },
       
  2335 		{ 0x06, 0xaf81 },
       
  2336 		{ 0x06, 0x8be0 },
       
  2337 		{ 0x06, 0x834d },
       
  2338 		{ 0x06, 0x10e4 },
       
  2339 		{ 0x06, 0x834d },
       
  2340 		{ 0x06, 0xae04 },
       
  2341 		{ 0x06, 0x80e4 },
       
  2342 		{ 0x06, 0x834d },
       
  2343 		{ 0x06, 0xe083 },
       
  2344 		{ 0x06, 0x4e78 },
       
  2345 		{ 0x06, 0x039e },
       
  2346 		{ 0x06, 0x0be0 },
       
  2347 		{ 0x06, 0x834e },
       
  2348 		{ 0x06, 0x7804 },
       
  2349 		{ 0x06, 0x9e04 },
       
  2350 		{ 0x06, 0xee83 },
       
  2351 		{ 0x06, 0x4e02 },
       
  2352 		{ 0x06, 0xe083 },
       
  2353 		{ 0x06, 0x32e1 },
       
  2354 		{ 0x06, 0x8333 },
       
  2355 		{ 0x06, 0x590f },
       
  2356 		{ 0x06, 0xe283 },
       
  2357 		{ 0x06, 0x4d0c },
       
  2358 		{ 0x06, 0x245a },
       
  2359 		{ 0x06, 0xf01e },
       
  2360 		{ 0x06, 0x12e4 },
       
  2361 		{ 0x06, 0xf88c },
       
  2362 		{ 0x06, 0xe5f8 },
       
  2363 		{ 0x06, 0x8de0 },
       
  2364 		{ 0x06, 0x8330 },
       
  2365 		{ 0x06, 0xe183 },
       
  2366 		{ 0x06, 0x3168 },
       
  2367 		{ 0x06, 0x01e4 },
       
  2368 		{ 0x06, 0xf88a },
       
  2369 		{ 0x06, 0xe5f8 },
       
  2370 		{ 0x06, 0x8bae },
       
  2371 		{ 0x06, 0x37ee },
       
  2372 		{ 0x06, 0x834e },
       
  2373 		{ 0x06, 0x03e0 },
       
  2374 		{ 0x06, 0x834c },
       
  2375 		{ 0x06, 0xe183 },
       
  2376 		{ 0x06, 0x4d1b },
       
  2377 		{ 0x06, 0x019e },
       
  2378 		{ 0x06, 0x04aa },
       
  2379 		{ 0x06, 0xa1ae },
       
  2380 		{ 0x06, 0xa8ee },
       
  2381 		{ 0x06, 0x834e },
       
  2382 		{ 0x06, 0x04ee },
       
  2383 		{ 0x06, 0x834f },
       
  2384 		{ 0x06, 0x00ae },
       
  2385 		{ 0x06, 0xabe0 },
       
  2386 		{ 0x06, 0x834f },
       
  2387 		{ 0x06, 0x7803 },
       
  2388 		{ 0x06, 0x9f14 },
       
  2389 		{ 0x06, 0xee83 },
       
  2390 		{ 0x06, 0x4e05 },
       
  2391 		{ 0x06, 0xd240 },
       
  2392 		{ 0x06, 0xd655 },
       
  2393 		{ 0x06, 0x5402 },
       
  2394 		{ 0x06, 0x81c6 },
       
  2395 		{ 0x06, 0xd2a0 },
       
  2396 		{ 0x06, 0xd6ba },
       
  2397 		{ 0x06, 0x0002 },
       
  2398 		{ 0x06, 0x81c6 },
       
  2399 		{ 0x06, 0xfefd },
       
  2400 		{ 0x06, 0xfc05 },
       
  2401 		{ 0x06, 0xf8e0 },
       
  2402 		{ 0x06, 0xf860 },
       
  2403 		{ 0x06, 0xe1f8 },
       
  2404 		{ 0x06, 0x6168 },
       
  2405 		{ 0x06, 0x02e4 },
       
  2406 		{ 0x06, 0xf860 },
       
  2407 		{ 0x06, 0xe5f8 },
       
  2408 		{ 0x06, 0x61e0 },
       
  2409 		{ 0x06, 0xf848 },
       
  2410 		{ 0x06, 0xe1f8 },
       
  2411 		{ 0x06, 0x4958 },
       
  2412 		{ 0x06, 0x0f1e },
       
  2413 		{ 0x06, 0x02e4 },
       
  2414 		{ 0x06, 0xf848 },
       
  2415 		{ 0x06, 0xe5f8 },
       
  2416 		{ 0x06, 0x49d0 },
       
  2417 		{ 0x06, 0x0002 },
       
  2418 		{ 0x06, 0x820a },
       
  2419 		{ 0x06, 0xbf83 },
       
  2420 		{ 0x06, 0x50ef },
       
  2421 		{ 0x06, 0x46dc },
       
  2422 		{ 0x06, 0x19dd },
       
  2423 		{ 0x06, 0xd001 },
       
  2424 		{ 0x06, 0x0282 },
       
  2425 		{ 0x06, 0x0a02 },
       
  2426 		{ 0x06, 0x8226 },
       
  2427 		{ 0x06, 0xe0f8 },
       
  2428 		{ 0x06, 0x60e1 },
       
  2429 		{ 0x06, 0xf861 },
       
  2430 		{ 0x06, 0x58fd },
       
  2431 		{ 0x06, 0xe4f8 },
       
  2432 		{ 0x06, 0x60e5 },
       
  2433 		{ 0x06, 0xf861 },
       
  2434 		{ 0x06, 0xfc04 },
       
  2435 		{ 0x06, 0xf9fa },
       
  2436 		{ 0x06, 0xfbc6 },
       
  2437 		{ 0x06, 0xbff8 },
       
  2438 		{ 0x06, 0x40be },
       
  2439 		{ 0x06, 0x8350 },
       
  2440 		{ 0x06, 0xa001 },
       
  2441 		{ 0x06, 0x0107 },
       
  2442 		{ 0x06, 0x1b89 },
       
  2443 		{ 0x06, 0xcfd2 },
       
  2444 		{ 0x06, 0x08eb },
       
  2445 		{ 0x06, 0xdb19 },
       
  2446 		{ 0x06, 0xb2fb },
       
  2447 		{ 0x06, 0xfffe },
       
  2448 		{ 0x06, 0xfd04 },
       
  2449 		{ 0x06, 0xf8e0 },
       
  2450 		{ 0x06, 0xf848 },
       
  2451 		{ 0x06, 0xe1f8 },
       
  2452 		{ 0x06, 0x4968 },
       
  2453 		{ 0x06, 0x08e4 },
       
  2454 		{ 0x06, 0xf848 },
       
  2455 		{ 0x06, 0xe5f8 },
       
  2456 		{ 0x06, 0x4958 },
       
  2457 		{ 0x06, 0xf7e4 },
       
  2458 		{ 0x06, 0xf848 },
       
  2459 		{ 0x06, 0xe5f8 },
       
  2460 		{ 0x06, 0x49fc },
       
  2461 		{ 0x06, 0x044d },
       
  2462 		{ 0x06, 0x2000 },
       
  2463 		{ 0x06, 0x024e },
       
  2464 		{ 0x06, 0x2200 },
       
  2465 		{ 0x06, 0x024d },
       
  2466 		{ 0x06, 0xdfff },
       
  2467 		{ 0x06, 0x014e },
       
  2468 		{ 0x06, 0xddff },
       
  2469 		{ 0x06, 0x0100 },
       
  2470 		{ 0x05, 0x83d8 },
       
  2471 		{ 0x06, 0x8000 },
       
  2472 		{ 0x03, 0xdc00 },
       
  2473 		{ 0x05, 0xfff6 },
       
  2474 		{ 0x06, 0x00fc },
       
  2475 		{ 0x1f, 0x0000 },
       
  2476 
       
  2477 		{ 0x1f, 0x0000 },
       
  2478 		{ 0x0d, 0xf880 },
       
  2479 		{ 0x1f, 0x0000 }
       
  2480 	};
       
  2481 
       
  2482 	rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
       
  2483 
       
  2484 	if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
       
  2485 		static const struct phy_reg phy_reg_init[] = {
       
  2486 			{ 0x1f, 0x0002 },
       
  2487 			{ 0x05, 0x669a },
       
  2488 			{ 0x1f, 0x0005 },
       
  2489 			{ 0x05, 0x8330 },
       
  2490 			{ 0x06, 0x669a },
       
  2491 
       
  2492 			{ 0x1f, 0x0002 }
       
  2493 		};
       
  2494 		int val;
       
  2495 
       
  2496 		rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2497 
       
  2498 		val = mdio_read(ioaddr, 0x0d);
       
  2499 		if ((val & 0x00ff) != 0x006c) {
       
  2500 			u32 set[] = {
       
  2501 				0x0065, 0x0066, 0x0067, 0x0068,
       
  2502 				0x0069, 0x006a, 0x006b, 0x006c
       
  2503 			};
       
  2504 			int i;
       
  2505 
       
  2506 			mdio_write(ioaddr, 0x1f, 0x0002);
       
  2507 
       
  2508 			val &= 0xff00;
       
  2509 			for (i = 0; i < ARRAY_SIZE(set); i++)
       
  2510 				mdio_write(ioaddr, 0x0d, val | set[i]);
       
  2511 		}
       
  2512 	} else {
       
  2513 		static const struct phy_reg phy_reg_init[] = {
       
  2514 			{ 0x1f, 0x0002 },
       
  2515 			{ 0x05, 0x2642 },
       
  2516 			{ 0x1f, 0x0005 },
       
  2517 			{ 0x05, 0x8330 },
       
  2518 			{ 0x06, 0x2642 }
       
  2519 		};
       
  2520 
       
  2521 		rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2522 	}
       
  2523 
       
  2524 	mdio_write(ioaddr, 0x1f, 0x0002);
       
  2525 	mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
       
  2526 	mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
       
  2527 
       
  2528 	mdio_write(ioaddr, 0x1f, 0x0001);
       
  2529 	mdio_write(ioaddr, 0x17, 0x0cc0);
       
  2530 
       
  2531 	mdio_write(ioaddr, 0x1f, 0x0002);
       
  2532 	mdio_patch(ioaddr, 0x0f, 0x0017);
       
  2533 
       
  2534 	rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
       
  2535 }
       
  2536 
       
  2537 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
       
  2538 {
       
  2539 	static const struct phy_reg phy_reg_init[] = {
       
  2540 		{ 0x1f, 0x0002 },
       
  2541 		{ 0x10, 0x0008 },
       
  2542 		{ 0x0d, 0x006c },
       
  2543 
       
  2544 		{ 0x1f, 0x0000 },
       
  2545 		{ 0x0d, 0xf880 },
       
  2546 
       
  2547 		{ 0x1f, 0x0001 },
       
  2548 		{ 0x17, 0x0cc0 },
       
  2549 
       
  2550 		{ 0x1f, 0x0001 },
       
  2551 		{ 0x0b, 0xa4d8 },
       
  2552 		{ 0x09, 0x281c },
       
  2553 		{ 0x07, 0x2883 },
       
  2554 		{ 0x0a, 0x6b35 },
       
  2555 		{ 0x1d, 0x3da4 },
       
  2556 		{ 0x1c, 0xeffd },
       
  2557 		{ 0x14, 0x7f52 },
       
  2558 		{ 0x18, 0x7fc6 },
       
  2559 		{ 0x08, 0x0601 },
       
  2560 		{ 0x06, 0x4063 },
       
  2561 		{ 0x10, 0xf074 },
       
  2562 		{ 0x1f, 0x0003 },
       
  2563 		{ 0x13, 0x0789 },
       
  2564 		{ 0x12, 0xf4bd },
       
  2565 		{ 0x1a, 0x04fd },
       
  2566 		{ 0x14, 0x84b0 },
       
  2567 		{ 0x1f, 0x0000 },
       
  2568 		{ 0x00, 0x9200 },
       
  2569 
       
  2570 		{ 0x1f, 0x0005 },
       
  2571 		{ 0x01, 0x0340 },
       
  2572 		{ 0x1f, 0x0001 },
       
  2573 		{ 0x04, 0x4000 },
       
  2574 		{ 0x03, 0x1d21 },
       
  2575 		{ 0x02, 0x0c32 },
       
  2576 		{ 0x01, 0x0200 },
       
  2577 		{ 0x00, 0x5554 },
       
  2578 		{ 0x04, 0x4800 },
       
  2579 		{ 0x04, 0x4000 },
       
  2580 		{ 0x04, 0xf000 },
       
  2581 		{ 0x03, 0xdf01 },
       
  2582 		{ 0x02, 0xdf20 },
       
  2583 		{ 0x01, 0x101a },
       
  2584 		{ 0x00, 0xa0ff },
       
  2585 		{ 0x04, 0xf800 },
       
  2586 		{ 0x04, 0xf000 },
       
  2587 		{ 0x1f, 0x0000 },
       
  2588 
       
  2589 		{ 0x1f, 0x0007 },
       
  2590 		{ 0x1e, 0x0023 },
       
  2591 		{ 0x16, 0x0000 },
       
  2592 		{ 0x1f, 0x0000 }
       
  2593 	};
       
  2594 
       
  2595 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2596 }
       
  2597 
       
  2598 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
       
  2599 {
       
  2600 	static const struct phy_reg phy_reg_init[] = {
       
  2601 		{ 0x1f, 0x0003 },
       
  2602 		{ 0x08, 0x441d },
       
  2603 		{ 0x01, 0x9100 },
       
  2604 		{ 0x1f, 0x0000 }
       
  2605 	};
       
  2606 
       
  2607 	mdio_write(ioaddr, 0x1f, 0x0000);
       
  2608 	mdio_patch(ioaddr, 0x11, 1 << 12);
       
  2609 	mdio_patch(ioaddr, 0x19, 1 << 13);
       
  2610 	mdio_patch(ioaddr, 0x10, 1 << 15);
       
  2611 
       
  2612 	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2613 }
       
  2614 
       
  2615 static void rtl_hw_phy_config(struct net_device *dev)
       
  2616 {
       
  2617 	struct rtl8169_private *tp = netdev_priv(dev);
       
  2618 	void __iomem *ioaddr = tp->mmio_addr;
       
  2619 
       
  2620 	rtl8169_print_mac_version(tp);
       
  2621 
       
  2622 	switch (tp->mac_version) {
       
  2623 	case RTL_GIGA_MAC_VER_01:
       
  2624 		break;
       
  2625 	case RTL_GIGA_MAC_VER_02:
       
  2626 	case RTL_GIGA_MAC_VER_03:
       
  2627 		rtl8169s_hw_phy_config(ioaddr);
       
  2628 		break;
       
  2629 	case RTL_GIGA_MAC_VER_04:
       
  2630 		rtl8169sb_hw_phy_config(ioaddr);
       
  2631 		break;
       
  2632 	case RTL_GIGA_MAC_VER_05:
       
  2633 		rtl8169scd_hw_phy_config(tp, ioaddr);
       
  2634 		break;
       
  2635 	case RTL_GIGA_MAC_VER_06:
       
  2636 		rtl8169sce_hw_phy_config(ioaddr);
       
  2637 		break;
       
  2638 	case RTL_GIGA_MAC_VER_07:
       
  2639 	case RTL_GIGA_MAC_VER_08:
       
  2640 	case RTL_GIGA_MAC_VER_09:
       
  2641 		rtl8102e_hw_phy_config(ioaddr);
       
  2642 		break;
       
  2643 	case RTL_GIGA_MAC_VER_11:
       
  2644 		rtl8168bb_hw_phy_config(ioaddr);
       
  2645 		break;
       
  2646 	case RTL_GIGA_MAC_VER_12:
       
  2647 		rtl8168bef_hw_phy_config(ioaddr);
       
  2648 		break;
       
  2649 	case RTL_GIGA_MAC_VER_17:
       
  2650 		rtl8168bef_hw_phy_config(ioaddr);
       
  2651 		break;
       
  2652 	case RTL_GIGA_MAC_VER_18:
       
  2653 		rtl8168cp_1_hw_phy_config(ioaddr);
       
  2654 		break;
       
  2655 	case RTL_GIGA_MAC_VER_19:
       
  2656 		rtl8168c_1_hw_phy_config(ioaddr);
       
  2657 		break;
       
  2658 	case RTL_GIGA_MAC_VER_20:
       
  2659 		rtl8168c_2_hw_phy_config(ioaddr);
       
  2660 		break;
       
  2661 	case RTL_GIGA_MAC_VER_21:
       
  2662 		rtl8168c_3_hw_phy_config(ioaddr);
       
  2663 		break;
       
  2664 	case RTL_GIGA_MAC_VER_22:
       
  2665 		rtl8168c_4_hw_phy_config(ioaddr);
       
  2666 		break;
       
  2667 	case RTL_GIGA_MAC_VER_23:
       
  2668 	case RTL_GIGA_MAC_VER_24:
       
  2669 		rtl8168cp_2_hw_phy_config(ioaddr);
       
  2670 		break;
       
  2671 	case RTL_GIGA_MAC_VER_25:
       
  2672 		rtl8168d_1_hw_phy_config(ioaddr);
       
  2673 		break;
       
  2674 	case RTL_GIGA_MAC_VER_26:
       
  2675 		rtl8168d_2_hw_phy_config(ioaddr);
       
  2676 		break;
       
  2677 	case RTL_GIGA_MAC_VER_27:
       
  2678 		rtl8168d_3_hw_phy_config(ioaddr);
       
  2679 		break;
       
  2680 
       
  2681 	default:
       
  2682 		break;
       
  2683 	}
       
  2684 }
       
  2685 
       
  2686 static void rtl8169_phy_timer(unsigned long __opaque)
       
  2687 {
       
  2688 	struct net_device *dev = (struct net_device *)__opaque;
       
  2689 	struct rtl8169_private *tp = netdev_priv(dev);
       
  2690 	struct timer_list *timer = &tp->timer;
       
  2691 	void __iomem *ioaddr = tp->mmio_addr;
       
  2692 	unsigned long timeout = RTL8169_PHY_TIMEOUT;
       
  2693 
       
  2694 	assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
       
  2695 
       
  2696 	if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
       
  2697 		return;
       
  2698 
       
  2699 	spin_lock_irq(&tp->lock);
       
  2700 
       
  2701 	if (tp->phy_reset_pending(ioaddr)) {
       
  2702 		/*
       
  2703 		 * A busy loop could burn quite a few cycles on nowadays CPU.
       
  2704 		 * Let's delay the execution of the timer for a few ticks.
       
  2705 		 */
       
  2706 		timeout = HZ/10;
       
  2707 		goto out_mod_timer;
       
  2708 	}
       
  2709 
       
  2710 	if (tp->link_ok(ioaddr))
       
  2711 		goto out_unlock;
       
  2712 
       
  2713 	if (netif_msg_link(tp))
       
  2714 		printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
       
  2715 
       
  2716 	tp->phy_reset_enable(ioaddr);
       
  2717 
       
  2718 out_mod_timer:
       
  2719 	mod_timer(timer, jiffies + timeout);
       
  2720 out_unlock:
       
  2721 	spin_unlock_irq(&tp->lock);
       
  2722 }
       
  2723 
       
  2724 static inline void rtl8169_delete_timer(struct net_device *dev)
       
  2725 {
       
  2726 	struct rtl8169_private *tp = netdev_priv(dev);
       
  2727 	struct timer_list *timer = &tp->timer;
       
  2728 
       
  2729 	if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
       
  2730 		return;
       
  2731 
       
  2732 	del_timer_sync(timer);
       
  2733 }
       
  2734 
       
  2735 static inline void rtl8169_request_timer(struct net_device *dev)
       
  2736 {
       
  2737 	struct rtl8169_private *tp = netdev_priv(dev);
       
  2738 	struct timer_list *timer = &tp->timer;
       
  2739 
       
  2740 	if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
       
  2741 		return;
       
  2742 
       
  2743 	mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
       
  2744 }
       
  2745 
       
  2746 #ifdef CONFIG_NET_POLL_CONTROLLER
       
  2747 /*
       
  2748  * Polling 'interrupt' - used by things like netconsole to send skbs
       
  2749  * without having to re-enable interrupts. It's not called while
       
  2750  * the interrupt routine is executing.
       
  2751  */
       
  2752 static void rtl8169_netpoll(struct net_device *dev)
       
  2753 {
       
  2754 	struct rtl8169_private *tp = netdev_priv(dev);
       
  2755 	struct pci_dev *pdev = tp->pci_dev;
       
  2756 
       
  2757 	disable_irq(pdev->irq);
       
  2758 	rtl8169_interrupt(pdev->irq, dev);
       
  2759 	enable_irq(pdev->irq);
       
  2760 }
       
  2761 #endif
       
  2762 
       
  2763 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
       
  2764 				  void __iomem *ioaddr)
       
  2765 {
       
  2766 	iounmap(ioaddr);
       
  2767 	pci_release_regions(pdev);
       
  2768 	pci_disable_device(pdev);
       
  2769 	free_netdev(dev);
       
  2770 }
       
  2771 
       
  2772 static void rtl8169_phy_reset(struct net_device *dev,
       
  2773 			      struct rtl8169_private *tp)
       
  2774 {
       
  2775 	void __iomem *ioaddr = tp->mmio_addr;
       
  2776 	unsigned int i;
       
  2777 
       
  2778 	tp->phy_reset_enable(ioaddr);
       
  2779 	for (i = 0; i < 100; i++) {
       
  2780 		if (!tp->phy_reset_pending(ioaddr))
       
  2781 			return;
       
  2782 		msleep(1);
       
  2783 	}
       
  2784 	if (netif_msg_link(tp))
       
  2785 		printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
       
  2786 }
       
  2787 
       
  2788 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
       
  2789 {
       
  2790 	void __iomem *ioaddr = tp->mmio_addr;
       
  2791 
       
  2792 	rtl_hw_phy_config(dev);
       
  2793 
       
  2794 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
       
  2795 		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
       
  2796 		RTL_W8(0x82, 0x01);
       
  2797 	}
       
  2798 
       
  2799 	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
       
  2800 
       
  2801 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
       
  2802 		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
       
  2803 
       
  2804 	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
       
  2805 		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
       
  2806 		RTL_W8(0x82, 0x01);
       
  2807 		dprintk("Set PHY Reg 0x0bh = 0x00h\n");
       
  2808 		mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
       
  2809 	}
       
  2810 
       
  2811 	rtl8169_phy_reset(dev, tp);
       
  2812 
       
  2813 	/*
       
  2814 	 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
       
  2815 	 * only 8101. Don't panic.
       
  2816 	 */
       
  2817 	rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
       
  2818 
       
  2819 	if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
       
  2820 		printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
       
  2821 }
       
  2822 
       
  2823 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
       
  2824 {
       
  2825 	void __iomem *ioaddr = tp->mmio_addr;
       
  2826 	u32 high;
       
  2827 	u32 low;
       
  2828 
       
  2829 	low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
       
  2830 	high = addr[4] | (addr[5] << 8);
       
  2831 
       
  2832 	spin_lock_irq(&tp->lock);
       
  2833 
       
  2834 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  2835 	RTL_W32(MAC0, low);
       
  2836 	RTL_W32(MAC4, high);
       
  2837 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  2838 
       
  2839 	spin_unlock_irq(&tp->lock);
       
  2840 }
       
  2841 
       
  2842 static int rtl_set_mac_address(struct net_device *dev, void *p)
       
  2843 {
       
  2844 	struct rtl8169_private *tp = netdev_priv(dev);
       
  2845 	struct sockaddr *addr = p;
       
  2846 
       
  2847 	if (!is_valid_ether_addr(addr->sa_data))
       
  2848 		return -EADDRNOTAVAIL;
       
  2849 
       
  2850 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
       
  2851 
       
  2852 	rtl_rar_set(tp, dev->dev_addr);
       
  2853 
       
  2854 	return 0;
       
  2855 }
       
  2856 
       
  2857 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
       
  2858 {
       
  2859 	struct rtl8169_private *tp = netdev_priv(dev);
       
  2860 	struct mii_ioctl_data *data = if_mii(ifr);
       
  2861 
       
  2862 	return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
       
  2863 }
       
  2864 
       
  2865 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
       
  2866 {
       
  2867 	switch (cmd) {
       
  2868 	case SIOCGMIIPHY:
       
  2869 		data->phy_id = 32; /* Internal PHY */
       
  2870 		return 0;
       
  2871 
       
  2872 	case SIOCGMIIREG:
       
  2873 		data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
       
  2874 		return 0;
       
  2875 
       
  2876 	case SIOCSMIIREG:
       
  2877 		mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
       
  2878 		return 0;
       
  2879 	}
       
  2880 	return -EOPNOTSUPP;
       
  2881 }
       
  2882 
       
  2883 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
       
  2884 {
       
  2885 	return -EOPNOTSUPP;
       
  2886 }
       
  2887 
       
  2888 static const struct rtl_cfg_info {
       
  2889 	void (*hw_start)(struct net_device *);
       
  2890 	unsigned int region;
       
  2891 	unsigned int align;
       
  2892 	u16 intr_event;
       
  2893 	u16 napi_event;
       
  2894 	unsigned features;
       
  2895 	u8 default_ver;
       
  2896 } rtl_cfg_infos [] = {
       
  2897 	[RTL_CFG_0] = {
       
  2898 		.hw_start	= rtl_hw_start_8169,
       
  2899 		.region		= 1,
       
  2900 		.align		= 0,
       
  2901 		.intr_event	= SYSErr | LinkChg | RxOverflow |
       
  2902 				  RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
       
  2903 		.napi_event	= RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
       
  2904 		.features	= RTL_FEATURE_GMII,
       
  2905 		.default_ver	= RTL_GIGA_MAC_VER_01,
       
  2906 	},
       
  2907 	[RTL_CFG_1] = {
       
  2908 		.hw_start	= rtl_hw_start_8168,
       
  2909 		.region		= 2,
       
  2910 		.align		= 8,
       
  2911 		.intr_event	= SYSErr | LinkChg | RxOverflow |
       
  2912 				  TxErr | TxOK | RxOK | RxErr,
       
  2913 		.napi_event	= TxErr | TxOK | RxOK | RxOverflow,
       
  2914 		.features	= RTL_FEATURE_GMII | RTL_FEATURE_MSI,
       
  2915 		.default_ver	= RTL_GIGA_MAC_VER_11,
       
  2916 	},
       
  2917 	[RTL_CFG_2] = {
       
  2918 		.hw_start	= rtl_hw_start_8101,
       
  2919 		.region		= 2,
       
  2920 		.align		= 8,
       
  2921 		.intr_event	= SYSErr | LinkChg | RxOverflow | PCSTimeout |
       
  2922 				  RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
       
  2923 		.napi_event	= RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
       
  2924 		.features	= RTL_FEATURE_MSI,
       
  2925 		.default_ver	= RTL_GIGA_MAC_VER_13,
       
  2926 	}
       
  2927 };
       
  2928 
       
  2929 /* Cfg9346_Unlock assumed. */
       
  2930 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
       
  2931 			    const struct rtl_cfg_info *cfg)
       
  2932 {
       
  2933 	unsigned msi = 0;
       
  2934 	u8 cfg2;
       
  2935 
       
  2936 	cfg2 = RTL_R8(Config2) & ~MSIEnable;
       
  2937 	if (cfg->features & RTL_FEATURE_MSI) {
       
  2938 		if (pci_enable_msi(pdev)) {
       
  2939 			dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
       
  2940 		} else {
       
  2941 			cfg2 |= MSIEnable;
       
  2942 			msi = RTL_FEATURE_MSI;
       
  2943 		}
       
  2944 	}
       
  2945 	RTL_W8(Config2, cfg2);
       
  2946 	return msi;
       
  2947 }
       
  2948 
       
  2949 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
       
  2950 {
       
  2951 	if (tp->features & RTL_FEATURE_MSI) {
       
  2952 		pci_disable_msi(pdev);
       
  2953 		tp->features &= ~RTL_FEATURE_MSI;
       
  2954 	}
       
  2955 }
       
  2956 
       
  2957 static const struct net_device_ops rtl8169_netdev_ops = {
       
  2958 	.ndo_open		= rtl8169_open,
       
  2959 	.ndo_stop		= rtl8169_close,
       
  2960 	.ndo_get_stats		= rtl8169_get_stats,
       
  2961 	.ndo_start_xmit		= rtl8169_start_xmit,
       
  2962 	.ndo_tx_timeout		= rtl8169_tx_timeout,
       
  2963 	.ndo_validate_addr	= eth_validate_addr,
       
  2964 	.ndo_change_mtu		= rtl8169_change_mtu,
       
  2965 	.ndo_set_mac_address	= rtl_set_mac_address,
       
  2966 	.ndo_do_ioctl		= rtl8169_ioctl,
       
  2967 	.ndo_set_multicast_list	= rtl_set_rx_mode,
       
  2968 #ifdef CONFIG_R8169_VLAN
       
  2969 	.ndo_vlan_rx_register	= rtl8169_vlan_rx_register,
       
  2970 #endif
       
  2971 #ifdef CONFIG_NET_POLL_CONTROLLER
       
  2972 	.ndo_poll_controller	= rtl8169_netpoll,
       
  2973 #endif
       
  2974 
       
  2975 };
       
  2976 
       
  2977 static int __devinit
       
  2978 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
       
  2979 {
       
  2980 	const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
       
  2981 	const unsigned int region = cfg->region;
       
  2982 	struct rtl8169_private *tp;
       
  2983 	struct mii_if_info *mii;
       
  2984 	struct net_device *dev;
       
  2985 	void __iomem *ioaddr;
       
  2986 	unsigned int i;
       
  2987 	int rc;
       
  2988 
       
  2989 	if (netif_msg_drv(&debug)) {
       
  2990 		printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
       
  2991 		       MODULENAME, RTL8169_VERSION);
       
  2992 	}
       
  2993 
       
  2994 	dev = alloc_etherdev(sizeof (*tp));
       
  2995 	if (!dev) {
       
  2996 		if (netif_msg_drv(&debug))
       
  2997 			dev_err(&pdev->dev, "unable to alloc new ethernet\n");
       
  2998 		rc = -ENOMEM;
       
  2999 		goto out;
       
  3000 	}
       
  3001 
       
  3002 	SET_NETDEV_DEV(dev, &pdev->dev);
       
  3003 	dev->netdev_ops = &rtl8169_netdev_ops;
       
  3004 	tp = netdev_priv(dev);
       
  3005 	tp->dev = dev;
       
  3006 	tp->pci_dev = pdev;
       
  3007 	tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
       
  3008 
       
  3009 	mii = &tp->mii;
       
  3010 	mii->dev = dev;
       
  3011 	mii->mdio_read = rtl_mdio_read;
       
  3012 	mii->mdio_write = rtl_mdio_write;
       
  3013 	mii->phy_id_mask = 0x1f;
       
  3014 	mii->reg_num_mask = 0x1f;
       
  3015 	mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
       
  3016 
       
  3017 	/* enable device (incl. PCI PM wakeup and hotplug setup) */
       
  3018 	rc = pci_enable_device(pdev);
       
  3019 	if (rc < 0) {
       
  3020 		if (netif_msg_probe(tp))
       
  3021 			dev_err(&pdev->dev, "enable failure\n");
       
  3022 		goto err_out_free_dev_1;
       
  3023 	}
       
  3024 
       
  3025 	rc = pci_set_mwi(pdev);
       
  3026 	if (rc < 0)
       
  3027 		goto err_out_disable_2;
       
  3028 
       
  3029 	/* make sure PCI base addr 1 is MMIO */
       
  3030 	if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
       
  3031 		if (netif_msg_probe(tp)) {
       
  3032 			dev_err(&pdev->dev,
       
  3033 				"region #%d not an MMIO resource, aborting\n",
       
  3034 				region);
       
  3035 		}
       
  3036 		rc = -ENODEV;
       
  3037 		goto err_out_mwi_3;
       
  3038 	}
       
  3039 
       
  3040 	/* check for weird/broken PCI region reporting */
       
  3041 	if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
       
  3042 		if (netif_msg_probe(tp)) {
       
  3043 			dev_err(&pdev->dev,
       
  3044 				"Invalid PCI region size(s), aborting\n");
       
  3045 		}
       
  3046 		rc = -ENODEV;
       
  3047 		goto err_out_mwi_3;
       
  3048 	}
       
  3049 
       
  3050 	rc = pci_request_regions(pdev, MODULENAME);
       
  3051 	if (rc < 0) {
       
  3052 		if (netif_msg_probe(tp))
       
  3053 			dev_err(&pdev->dev, "could not request regions.\n");
       
  3054 		goto err_out_mwi_3;
       
  3055 	}
       
  3056 
       
  3057 	tp->cp_cmd = PCIMulRW | RxChkSum;
       
  3058 
       
  3059 	if ((sizeof(dma_addr_t) > 4) &&
       
  3060 	    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
       
  3061 		tp->cp_cmd |= PCIDAC;
       
  3062 		dev->features |= NETIF_F_HIGHDMA;
       
  3063 	} else {
       
  3064 		rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
       
  3065 		if (rc < 0) {
       
  3066 			if (netif_msg_probe(tp)) {
       
  3067 				dev_err(&pdev->dev,
       
  3068 					"DMA configuration failed.\n");
       
  3069 			}
       
  3070 			goto err_out_free_res_4;
       
  3071 		}
       
  3072 	}
       
  3073 
       
  3074 	/* ioremap MMIO region */
       
  3075 	ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
       
  3076 	if (!ioaddr) {
       
  3077 		if (netif_msg_probe(tp))
       
  3078 			dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
       
  3079 		rc = -EIO;
       
  3080 		goto err_out_free_res_4;
       
  3081 	}
       
  3082 
       
  3083 	tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
       
  3084 	if (!tp->pcie_cap && netif_msg_probe(tp))
       
  3085 		dev_info(&pdev->dev, "no PCI Express capability\n");
       
  3086 
       
  3087 	RTL_W16(IntrMask, 0x0000);
       
  3088 
       
  3089 	/* Soft reset the chip. */
       
  3090 	RTL_W8(ChipCmd, CmdReset);
       
  3091 
       
  3092 	/* Check that the chip has finished the reset. */
       
  3093 	for (i = 0; i < 100; i++) {
       
  3094 		if ((RTL_R8(ChipCmd) & CmdReset) == 0)
       
  3095 			break;
       
  3096 		msleep_interruptible(1);
       
  3097 	}
       
  3098 
       
  3099 	RTL_W16(IntrStatus, 0xffff);
       
  3100 
       
  3101 	pci_set_master(pdev);
       
  3102 
       
  3103 	/* Identify chip attached to board */
       
  3104 	rtl8169_get_mac_version(tp, ioaddr);
       
  3105 
       
  3106 	/* Use appropriate default if unknown */
       
  3107 	if (tp->mac_version == RTL_GIGA_MAC_NONE) {
       
  3108 		if (netif_msg_probe(tp)) {
       
  3109 			dev_notice(&pdev->dev,
       
  3110 				   "unknown MAC, using family default\n");
       
  3111 		}
       
  3112 		tp->mac_version = cfg->default_ver;
       
  3113 	}
       
  3114 
       
  3115 	rtl8169_print_mac_version(tp);
       
  3116 
       
  3117 	for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
       
  3118 		if (tp->mac_version == rtl_chip_info[i].mac_version)
       
  3119 			break;
       
  3120 	}
       
  3121 	if (i == ARRAY_SIZE(rtl_chip_info)) {
       
  3122 		dev_err(&pdev->dev,
       
  3123 			"driver bug, MAC version not found in rtl_chip_info\n");
       
  3124 		goto err_out_msi_5;
       
  3125 	}
       
  3126 	tp->chipset = i;
       
  3127 
       
  3128 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  3129 	RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
       
  3130 	RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
       
  3131 	if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
       
  3132 		tp->features |= RTL_FEATURE_WOL;
       
  3133 	if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
       
  3134 		tp->features |= RTL_FEATURE_WOL;
       
  3135 	tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
       
  3136 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  3137 
       
  3138 	if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
       
  3139 	    (RTL_R8(PHYstatus) & TBI_Enable)) {
       
  3140 		tp->set_speed = rtl8169_set_speed_tbi;
       
  3141 		tp->get_settings = rtl8169_gset_tbi;
       
  3142 		tp->phy_reset_enable = rtl8169_tbi_reset_enable;
       
  3143 		tp->phy_reset_pending = rtl8169_tbi_reset_pending;
       
  3144 		tp->link_ok = rtl8169_tbi_link_ok;
       
  3145 		tp->do_ioctl = rtl_tbi_ioctl;
       
  3146 
       
  3147 		tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
       
  3148 	} else {
       
  3149 		tp->set_speed = rtl8169_set_speed_xmii;
       
  3150 		tp->get_settings = rtl8169_gset_xmii;
       
  3151 		tp->phy_reset_enable = rtl8169_xmii_reset_enable;
       
  3152 		tp->phy_reset_pending = rtl8169_xmii_reset_pending;
       
  3153 		tp->link_ok = rtl8169_xmii_link_ok;
       
  3154 		tp->do_ioctl = rtl_xmii_ioctl;
       
  3155 	}
       
  3156 
       
  3157 	spin_lock_init(&tp->lock);
       
  3158 
       
  3159 	tp->mmio_addr = ioaddr;
       
  3160 
       
  3161 	/* Get MAC address */
       
  3162 	for (i = 0; i < MAC_ADDR_LEN; i++)
       
  3163 		dev->dev_addr[i] = RTL_R8(MAC0 + i);
       
  3164 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
       
  3165 
       
  3166 	SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
       
  3167 	dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
       
  3168 	dev->irq = pdev->irq;
       
  3169 	dev->base_addr = (unsigned long) ioaddr;
       
  3170 
       
  3171 	netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
       
  3172 
       
  3173 #ifdef CONFIG_R8169_VLAN
       
  3174 	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
       
  3175 #endif
       
  3176 
       
  3177 	tp->intr_mask = 0xffff;
       
  3178 	tp->align = cfg->align;
       
  3179 	tp->hw_start = cfg->hw_start;
       
  3180 	tp->intr_event = cfg->intr_event;
       
  3181 	tp->napi_event = cfg->napi_event;
       
  3182 
       
  3183 	init_timer(&tp->timer);
       
  3184 	tp->timer.data = (unsigned long) dev;
       
  3185 	tp->timer.function = rtl8169_phy_timer;
       
  3186 
       
  3187 	rc = register_netdev(dev);
       
  3188 	if (rc < 0)
       
  3189 		goto err_out_msi_5;
       
  3190 
       
  3191 	pci_set_drvdata(pdev, dev);
       
  3192 
       
  3193 	if (netif_msg_probe(tp)) {
       
  3194 		u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff;
       
  3195 
       
  3196 		printk(KERN_INFO "%s: %s at 0x%lx, "
       
  3197 		       "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
       
  3198 		       "XID %08x IRQ %d\n",
       
  3199 		       dev->name,
       
  3200 		       rtl_chip_info[tp->chipset].name,
       
  3201 		       dev->base_addr,
       
  3202 		       dev->dev_addr[0], dev->dev_addr[1],
       
  3203 		       dev->dev_addr[2], dev->dev_addr[3],
       
  3204 		       dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
       
  3205 	}
       
  3206 
       
  3207 	rtl8169_init_phy(dev, tp);
       
  3208 
       
  3209 	/*
       
  3210 	 * Pretend we are using VLANs; This bypasses a nasty bug where
       
  3211 	 * Interrupts stop flowing on high load on 8110SCd controllers.
       
  3212 	 */
       
  3213 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
       
  3214 		RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
       
  3215 
       
  3216 	device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
       
  3217 
       
  3218 out:
       
  3219 	return rc;
       
  3220 
       
  3221 err_out_msi_5:
       
  3222 	rtl_disable_msi(pdev, tp);
       
  3223 	iounmap(ioaddr);
       
  3224 err_out_free_res_4:
       
  3225 	pci_release_regions(pdev);
       
  3226 err_out_mwi_3:
       
  3227 	pci_clear_mwi(pdev);
       
  3228 err_out_disable_2:
       
  3229 	pci_disable_device(pdev);
       
  3230 err_out_free_dev_1:
       
  3231 	free_netdev(dev);
       
  3232 	goto out;
       
  3233 }
       
  3234 
       
  3235 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
       
  3236 {
       
  3237 	struct net_device *dev = pci_get_drvdata(pdev);
       
  3238 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3239 
       
  3240 	flush_scheduled_work();
       
  3241 
       
  3242 	unregister_netdev(dev);
       
  3243 
       
  3244 	/* restore original MAC address */
       
  3245 	rtl_rar_set(tp, dev->perm_addr);
       
  3246 
       
  3247 	rtl_disable_msi(pdev, tp);
       
  3248 	rtl8169_release_board(pdev, dev, tp->mmio_addr);
       
  3249 	pci_set_drvdata(pdev, NULL);
       
  3250 }
       
  3251 
       
  3252 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
       
  3253 				  unsigned int mtu)
       
  3254 {
       
  3255 	unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
       
  3256 
       
  3257 	if (max_frame != 16383)
       
  3258 		printk(KERN_WARNING "WARNING! Changing of MTU on this NIC"
       
  3259 			"May lead to frame reception errors!\n");
       
  3260 
       
  3261 	tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
       
  3262 }
       
  3263 
       
  3264 static int rtl8169_open(struct net_device *dev)
       
  3265 {
       
  3266 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3267 	struct pci_dev *pdev = tp->pci_dev;
       
  3268 	int retval = -ENOMEM;
       
  3269 
       
  3270 
       
  3271 	/*
       
  3272 	 * Note that we use a magic value here, its wierd I know
       
  3273 	 * its done because, some subset of rtl8169 hardware suffers from
       
  3274 	 * a problem in which frames received that are longer than
       
  3275 	 * the size set in RxMaxSize register return garbage sizes
       
  3276 	 * when received.  To avoid this we need to turn off filtering,
       
  3277 	 * which is done by setting a value of 16383 in the RxMaxSize register
       
  3278 	 * and allocating 16k frames to handle the largest possible rx value
       
  3279 	 * thats what the magic math below does.
       
  3280 	 */
       
  3281 	rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
       
  3282 
       
  3283 	/*
       
  3284 	 * Rx and Tx desscriptors needs 256 bytes alignment.
       
  3285 	 * pci_alloc_consistent provides more.
       
  3286 	 */
       
  3287 	tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
       
  3288 					       &tp->TxPhyAddr);
       
  3289 	if (!tp->TxDescArray)
       
  3290 		goto out;
       
  3291 
       
  3292 	tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
       
  3293 					       &tp->RxPhyAddr);
       
  3294 	if (!tp->RxDescArray)
       
  3295 		goto err_free_tx_0;
       
  3296 
       
  3297 	retval = rtl8169_init_ring(dev);
       
  3298 	if (retval < 0)
       
  3299 		goto err_free_rx_1;
       
  3300 
       
  3301 	INIT_DELAYED_WORK(&tp->task, NULL);
       
  3302 
       
  3303 	smp_mb();
       
  3304 
       
  3305 	retval = request_irq(dev->irq, rtl8169_interrupt,
       
  3306 			     (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
       
  3307 			     dev->name, dev);
       
  3308 	if (retval < 0)
       
  3309 		goto err_release_ring_2;
       
  3310 
       
  3311 	napi_enable(&tp->napi);
       
  3312 
       
  3313 	rtl_hw_start(dev);
       
  3314 
       
  3315 	rtl8169_request_timer(dev);
       
  3316 
       
  3317 	rtl8169_check_link_status(dev, tp, tp->mmio_addr);
       
  3318 out:
       
  3319 	return retval;
       
  3320 
       
  3321 err_release_ring_2:
       
  3322 	rtl8169_rx_clear(tp);
       
  3323 err_free_rx_1:
       
  3324 	pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
       
  3325 			    tp->RxPhyAddr);
       
  3326 err_free_tx_0:
       
  3327 	pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
       
  3328 			    tp->TxPhyAddr);
       
  3329 	goto out;
       
  3330 }
       
  3331 
       
  3332 static void rtl8169_hw_reset(void __iomem *ioaddr)
       
  3333 {
       
  3334 	/* Disable interrupts */
       
  3335 	rtl8169_irq_mask_and_ack(ioaddr);
       
  3336 
       
  3337 	/* Reset the chipset */
       
  3338 	RTL_W8(ChipCmd, CmdReset);
       
  3339 
       
  3340 	/* PCI commit */
       
  3341 	RTL_R8(ChipCmd);
       
  3342 }
       
  3343 
       
  3344 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
       
  3345 {
       
  3346 	void __iomem *ioaddr = tp->mmio_addr;
       
  3347 	u32 cfg = rtl8169_rx_config;
       
  3348 
       
  3349 	cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
       
  3350 	RTL_W32(RxConfig, cfg);
       
  3351 
       
  3352 	/* Set DMA burst size and Interframe Gap Time */
       
  3353 	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
       
  3354 		(InterFrameGap << TxInterFrameGapShift));
       
  3355 }
       
  3356 
       
  3357 static void rtl_hw_start(struct net_device *dev)
       
  3358 {
       
  3359 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3360 	void __iomem *ioaddr = tp->mmio_addr;
       
  3361 	unsigned int i;
       
  3362 
       
  3363 	/* Soft reset the chip. */
       
  3364 	RTL_W8(ChipCmd, CmdReset);
       
  3365 
       
  3366 	/* Check that the chip has finished the reset. */
       
  3367 	for (i = 0; i < 100; i++) {
       
  3368 		if ((RTL_R8(ChipCmd) & CmdReset) == 0)
       
  3369 			break;
       
  3370 		msleep_interruptible(1);
       
  3371 	}
       
  3372 
       
  3373 	tp->hw_start(dev);
       
  3374 
       
  3375 	netif_start_queue(dev);
       
  3376 }
       
  3377 
       
  3378 
       
  3379 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
       
  3380 					 void __iomem *ioaddr)
       
  3381 {
       
  3382 	/*
       
  3383 	 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
       
  3384 	 * register to be written before TxDescAddrLow to work.
       
  3385 	 * Switching from MMIO to I/O access fixes the issue as well.
       
  3386 	 */
       
  3387 	RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
       
  3388 	RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
       
  3389 	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
       
  3390 	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
       
  3391 }
       
  3392 
       
  3393 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
       
  3394 {
       
  3395 	u16 cmd;
       
  3396 
       
  3397 	cmd = RTL_R16(CPlusCmd);
       
  3398 	RTL_W16(CPlusCmd, cmd);
       
  3399 	return cmd;
       
  3400 }
       
  3401 
       
  3402 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
       
  3403 {
       
  3404 	/* Low hurts. Let's disable the filtering. */
       
  3405 	RTL_W16(RxMaxSize, rx_buf_sz + 1);
       
  3406 }
       
  3407 
       
  3408 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
       
  3409 {
       
  3410 	static const struct {
       
  3411 		u32 mac_version;
       
  3412 		u32 clk;
       
  3413 		u32 val;
       
  3414 	} cfg2_info [] = {
       
  3415 		{ RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
       
  3416 		{ RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
       
  3417 		{ RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
       
  3418 		{ RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
       
  3419 	}, *p = cfg2_info;
       
  3420 	unsigned int i;
       
  3421 	u32 clk;
       
  3422 
       
  3423 	clk = RTL_R8(Config2) & PCI_Clock_66MHz;
       
  3424 	for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
       
  3425 		if ((p->mac_version == mac_version) && (p->clk == clk)) {
       
  3426 			RTL_W32(0x7c, p->val);
       
  3427 			break;
       
  3428 		}
       
  3429 	}
       
  3430 }
       
  3431 
       
  3432 static void rtl_hw_start_8169(struct net_device *dev)
       
  3433 {
       
  3434 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3435 	void __iomem *ioaddr = tp->mmio_addr;
       
  3436 	struct pci_dev *pdev = tp->pci_dev;
       
  3437 
       
  3438 	if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
       
  3439 		RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
       
  3440 		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
       
  3441 	}
       
  3442 
       
  3443 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  3444 	if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
       
  3445 	    (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
       
  3446 	    (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
       
  3447 	    (tp->mac_version == RTL_GIGA_MAC_VER_04))
       
  3448 		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
       
  3449 
       
  3450 	RTL_W8(EarlyTxThres, EarlyTxThld);
       
  3451 
       
  3452 	rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
       
  3453 
       
  3454 	if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
       
  3455 	    (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
       
  3456 	    (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
       
  3457 	    (tp->mac_version == RTL_GIGA_MAC_VER_04))
       
  3458 		rtl_set_rx_tx_config_registers(tp);
       
  3459 
       
  3460 	tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
       
  3461 
       
  3462 	if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
       
  3463 	    (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
       
  3464 		dprintk("Set MAC Reg C+CR Offset 0xE0. "
       
  3465 			"Bit-3 and bit-14 MUST be 1\n");
       
  3466 		tp->cp_cmd |= (1 << 14);
       
  3467 	}
       
  3468 
       
  3469 	RTL_W16(CPlusCmd, tp->cp_cmd);
       
  3470 
       
  3471 	rtl8169_set_magic_reg(ioaddr, tp->mac_version);
       
  3472 
       
  3473 	/*
       
  3474 	 * Undocumented corner. Supposedly:
       
  3475 	 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
       
  3476 	 */
       
  3477 	RTL_W16(IntrMitigate, 0x0000);
       
  3478 
       
  3479 	rtl_set_rx_tx_desc_registers(tp, ioaddr);
       
  3480 
       
  3481 	if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
       
  3482 	    (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
       
  3483 	    (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
       
  3484 	    (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
       
  3485 		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
       
  3486 		rtl_set_rx_tx_config_registers(tp);
       
  3487 	}
       
  3488 
       
  3489 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  3490 
       
  3491 	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
       
  3492 	RTL_R8(IntrMask);
       
  3493 
       
  3494 	RTL_W32(RxMissed, 0);
       
  3495 
       
  3496 	rtl_set_rx_mode(dev);
       
  3497 
       
  3498 	/* no early-rx interrupts */
       
  3499 	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
       
  3500 
       
  3501 	/* Enable all known interrupts by setting the interrupt mask. */
       
  3502 	RTL_W16(IntrMask, tp->intr_event);
       
  3503 }
       
  3504 
       
  3505 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
       
  3506 {
       
  3507 	struct net_device *dev = pci_get_drvdata(pdev);
       
  3508 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3509 	int cap = tp->pcie_cap;
       
  3510 
       
  3511 	if (cap) {
       
  3512 		u16 ctl;
       
  3513 
       
  3514 		pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
       
  3515 		ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
       
  3516 		pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
       
  3517 	}
       
  3518 }
       
  3519 
       
  3520 static void rtl_csi_access_enable(void __iomem *ioaddr)
       
  3521 {
       
  3522 	u32 csi;
       
  3523 
       
  3524 	csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
       
  3525 	rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
       
  3526 }
       
  3527 
       
  3528 struct ephy_info {
       
  3529 	unsigned int offset;
       
  3530 	u16 mask;
       
  3531 	u16 bits;
       
  3532 };
       
  3533 
       
  3534 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
       
  3535 {
       
  3536 	u16 w;
       
  3537 
       
  3538 	while (len-- > 0) {
       
  3539 		w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
       
  3540 		rtl_ephy_write(ioaddr, e->offset, w);
       
  3541 		e++;
       
  3542 	}
       
  3543 }
       
  3544 
       
  3545 static void rtl_disable_clock_request(struct pci_dev *pdev)
       
  3546 {
       
  3547 	struct net_device *dev = pci_get_drvdata(pdev);
       
  3548 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3549 	int cap = tp->pcie_cap;
       
  3550 
       
  3551 	if (cap) {
       
  3552 		u16 ctl;
       
  3553 
       
  3554 		pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
       
  3555 		ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
       
  3556 		pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
       
  3557 	}
       
  3558 }
       
  3559 
       
  3560 #define R8168_CPCMD_QUIRK_MASK (\
       
  3561 	EnableBist | \
       
  3562 	Mac_dbgo_oe | \
       
  3563 	Force_half_dup | \
       
  3564 	Force_rxflow_en | \
       
  3565 	Force_txflow_en | \
       
  3566 	Cxpl_dbg_sel | \
       
  3567 	ASF | \
       
  3568 	PktCntrDisable | \
       
  3569 	Mac_dbgo_sel)
       
  3570 
       
  3571 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3572 {
       
  3573 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  3574 
       
  3575 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
       
  3576 
       
  3577 	rtl_tx_performance_tweak(pdev,
       
  3578 		(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
       
  3579 }
       
  3580 
       
  3581 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3582 {
       
  3583 	rtl_hw_start_8168bb(ioaddr, pdev);
       
  3584 
       
  3585 	RTL_W8(EarlyTxThres, EarlyTxThld);
       
  3586 
       
  3587 	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
       
  3588 }
       
  3589 
       
  3590 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3591 {
       
  3592 	RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
       
  3593 
       
  3594 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  3595 
       
  3596 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  3597 
       
  3598 	rtl_disable_clock_request(pdev);
       
  3599 
       
  3600 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
       
  3601 }
       
  3602 
       
  3603 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3604 {
       
  3605 	static const struct ephy_info e_info_8168cp[] = {
       
  3606 		{ 0x01, 0,	0x0001 },
       
  3607 		{ 0x02, 0x0800,	0x1000 },
       
  3608 		{ 0x03, 0,	0x0042 },
       
  3609 		{ 0x06, 0x0080,	0x0000 },
       
  3610 		{ 0x07, 0,	0x2000 }
       
  3611 	};
       
  3612 
       
  3613 	rtl_csi_access_enable(ioaddr);
       
  3614 
       
  3615 	rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
       
  3616 
       
  3617 	__rtl_hw_start_8168cp(ioaddr, pdev);
       
  3618 }
       
  3619 
       
  3620 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3621 {
       
  3622 	rtl_csi_access_enable(ioaddr);
       
  3623 
       
  3624 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  3625 
       
  3626 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  3627 
       
  3628 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
       
  3629 }
       
  3630 
       
  3631 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3632 {
       
  3633 	rtl_csi_access_enable(ioaddr);
       
  3634 
       
  3635 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  3636 
       
  3637 	/* Magic. */
       
  3638 	RTL_W8(DBG_REG, 0x20);
       
  3639 
       
  3640 	RTL_W8(EarlyTxThres, EarlyTxThld);
       
  3641 
       
  3642 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  3643 
       
  3644 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
       
  3645 }
       
  3646 
       
  3647 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3648 {
       
  3649 	static const struct ephy_info e_info_8168c_1[] = {
       
  3650 		{ 0x02, 0x0800,	0x1000 },
       
  3651 		{ 0x03, 0,	0x0002 },
       
  3652 		{ 0x06, 0x0080,	0x0000 }
       
  3653 	};
       
  3654 
       
  3655 	rtl_csi_access_enable(ioaddr);
       
  3656 
       
  3657 	RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
       
  3658 
       
  3659 	rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
       
  3660 
       
  3661 	__rtl_hw_start_8168cp(ioaddr, pdev);
       
  3662 }
       
  3663 
       
  3664 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3665 {
       
  3666 	static const struct ephy_info e_info_8168c_2[] = {
       
  3667 		{ 0x01, 0,	0x0001 },
       
  3668 		{ 0x03, 0x0400,	0x0220 }
       
  3669 	};
       
  3670 
       
  3671 	rtl_csi_access_enable(ioaddr);
       
  3672 
       
  3673 	rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
       
  3674 
       
  3675 	__rtl_hw_start_8168cp(ioaddr, pdev);
       
  3676 }
       
  3677 
       
  3678 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3679 {
       
  3680 	rtl_hw_start_8168c_2(ioaddr, pdev);
       
  3681 }
       
  3682 
       
  3683 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3684 {
       
  3685 	rtl_csi_access_enable(ioaddr);
       
  3686 
       
  3687 	__rtl_hw_start_8168cp(ioaddr, pdev);
       
  3688 }
       
  3689 
       
  3690 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3691 {
       
  3692 	rtl_csi_access_enable(ioaddr);
       
  3693 
       
  3694 	rtl_disable_clock_request(pdev);
       
  3695 
       
  3696 	RTL_W8(EarlyTxThres, EarlyTxThld);
       
  3697 
       
  3698 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  3699 
       
  3700 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
       
  3701 }
       
  3702 
       
  3703 static void rtl_hw_start_8168(struct net_device *dev)
       
  3704 {
       
  3705 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3706 	void __iomem *ioaddr = tp->mmio_addr;
       
  3707 	struct pci_dev *pdev = tp->pci_dev;
       
  3708 
       
  3709 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  3710 
       
  3711 	RTL_W8(EarlyTxThres, EarlyTxThld);
       
  3712 
       
  3713 	rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
       
  3714 
       
  3715 	tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
       
  3716 
       
  3717 	RTL_W16(CPlusCmd, tp->cp_cmd);
       
  3718 
       
  3719 	RTL_W16(IntrMitigate, 0x5151);
       
  3720 
       
  3721 	/* Work around for RxFIFO overflow. */
       
  3722 	if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
       
  3723 		tp->intr_event |= RxFIFOOver | PCSTimeout;
       
  3724 		tp->intr_event &= ~RxOverflow;
       
  3725 	}
       
  3726 
       
  3727 	rtl_set_rx_tx_desc_registers(tp, ioaddr);
       
  3728 
       
  3729 	rtl_set_rx_mode(dev);
       
  3730 
       
  3731 	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
       
  3732 		(InterFrameGap << TxInterFrameGapShift));
       
  3733 
       
  3734 	RTL_R8(IntrMask);
       
  3735 
       
  3736 	switch (tp->mac_version) {
       
  3737 	case RTL_GIGA_MAC_VER_11:
       
  3738 		rtl_hw_start_8168bb(ioaddr, pdev);
       
  3739 	break;
       
  3740 
       
  3741 	case RTL_GIGA_MAC_VER_12:
       
  3742 	case RTL_GIGA_MAC_VER_17:
       
  3743 		rtl_hw_start_8168bef(ioaddr, pdev);
       
  3744 	break;
       
  3745 
       
  3746 	case RTL_GIGA_MAC_VER_18:
       
  3747 		rtl_hw_start_8168cp_1(ioaddr, pdev);
       
  3748 	break;
       
  3749 
       
  3750 	case RTL_GIGA_MAC_VER_19:
       
  3751 		rtl_hw_start_8168c_1(ioaddr, pdev);
       
  3752 	break;
       
  3753 
       
  3754 	case RTL_GIGA_MAC_VER_20:
       
  3755 		rtl_hw_start_8168c_2(ioaddr, pdev);
       
  3756 	break;
       
  3757 
       
  3758 	case RTL_GIGA_MAC_VER_21:
       
  3759 		rtl_hw_start_8168c_3(ioaddr, pdev);
       
  3760 	break;
       
  3761 
       
  3762 	case RTL_GIGA_MAC_VER_22:
       
  3763 		rtl_hw_start_8168c_4(ioaddr, pdev);
       
  3764 	break;
       
  3765 
       
  3766 	case RTL_GIGA_MAC_VER_23:
       
  3767 		rtl_hw_start_8168cp_2(ioaddr, pdev);
       
  3768 	break;
       
  3769 
       
  3770 	case RTL_GIGA_MAC_VER_24:
       
  3771 		rtl_hw_start_8168cp_3(ioaddr, pdev);
       
  3772 	break;
       
  3773 
       
  3774 	case RTL_GIGA_MAC_VER_25:
       
  3775 	case RTL_GIGA_MAC_VER_26:
       
  3776 	case RTL_GIGA_MAC_VER_27:
       
  3777 		rtl_hw_start_8168d(ioaddr, pdev);
       
  3778 	break;
       
  3779 
       
  3780 	default:
       
  3781 		printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
       
  3782 			dev->name, tp->mac_version);
       
  3783 	break;
       
  3784 	}
       
  3785 
       
  3786 	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
       
  3787 
       
  3788 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  3789 
       
  3790 	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
       
  3791 
       
  3792 	RTL_W16(IntrMask, tp->intr_event);
       
  3793 }
       
  3794 
       
  3795 #define R810X_CPCMD_QUIRK_MASK (\
       
  3796 	EnableBist | \
       
  3797 	Mac_dbgo_oe | \
       
  3798 	Force_half_dup | \
       
  3799 	Force_rxflow_en | \
       
  3800 	Force_txflow_en | \
       
  3801 	Cxpl_dbg_sel | \
       
  3802 	ASF | \
       
  3803 	PktCntrDisable | \
       
  3804 	PCIDAC | \
       
  3805 	PCIMulRW)
       
  3806 
       
  3807 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3808 {
       
  3809 	static const struct ephy_info e_info_8102e_1[] = {
       
  3810 		{ 0x01,	0, 0x6e65 },
       
  3811 		{ 0x02,	0, 0x091f },
       
  3812 		{ 0x03,	0, 0xc2f9 },
       
  3813 		{ 0x06,	0, 0xafb5 },
       
  3814 		{ 0x07,	0, 0x0e00 },
       
  3815 		{ 0x19,	0, 0xec80 },
       
  3816 		{ 0x01,	0, 0x2e65 },
       
  3817 		{ 0x01,	0, 0x6e65 }
       
  3818 	};
       
  3819 	u8 cfg1;
       
  3820 
       
  3821 	rtl_csi_access_enable(ioaddr);
       
  3822 
       
  3823 	RTL_W8(DBG_REG, FIX_NAK_1);
       
  3824 
       
  3825 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  3826 
       
  3827 	RTL_W8(Config1,
       
  3828 	       LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
       
  3829 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  3830 
       
  3831 	cfg1 = RTL_R8(Config1);
       
  3832 	if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
       
  3833 		RTL_W8(Config1, cfg1 & ~LEDS0);
       
  3834 
       
  3835 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
       
  3836 
       
  3837 	rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
       
  3838 }
       
  3839 
       
  3840 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3841 {
       
  3842 	rtl_csi_access_enable(ioaddr);
       
  3843 
       
  3844 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  3845 
       
  3846 	RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
       
  3847 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  3848 
       
  3849 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
       
  3850 }
       
  3851 
       
  3852 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
       
  3853 {
       
  3854 	rtl_hw_start_8102e_2(ioaddr, pdev);
       
  3855 
       
  3856 	rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
       
  3857 }
       
  3858 
       
  3859 static void rtl_hw_start_8101(struct net_device *dev)
       
  3860 {
       
  3861 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3862 	void __iomem *ioaddr = tp->mmio_addr;
       
  3863 	struct pci_dev *pdev = tp->pci_dev;
       
  3864 
       
  3865 	if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
       
  3866 	    (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
       
  3867 		int cap = tp->pcie_cap;
       
  3868 
       
  3869 		if (cap) {
       
  3870 			pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
       
  3871 					      PCI_EXP_DEVCTL_NOSNOOP_EN);
       
  3872 		}
       
  3873 	}
       
  3874 
       
  3875 	switch (tp->mac_version) {
       
  3876 	case RTL_GIGA_MAC_VER_07:
       
  3877 		rtl_hw_start_8102e_1(ioaddr, pdev);
       
  3878 		break;
       
  3879 
       
  3880 	case RTL_GIGA_MAC_VER_08:
       
  3881 		rtl_hw_start_8102e_3(ioaddr, pdev);
       
  3882 		break;
       
  3883 
       
  3884 	case RTL_GIGA_MAC_VER_09:
       
  3885 		rtl_hw_start_8102e_2(ioaddr, pdev);
       
  3886 		break;
       
  3887 	}
       
  3888 
       
  3889 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  3890 
       
  3891 	RTL_W8(EarlyTxThres, EarlyTxThld);
       
  3892 
       
  3893 	rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
       
  3894 
       
  3895 	tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
       
  3896 
       
  3897 	RTL_W16(CPlusCmd, tp->cp_cmd);
       
  3898 
       
  3899 	RTL_W16(IntrMitigate, 0x0000);
       
  3900 
       
  3901 	rtl_set_rx_tx_desc_registers(tp, ioaddr);
       
  3902 
       
  3903 	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
       
  3904 	rtl_set_rx_tx_config_registers(tp);
       
  3905 
       
  3906 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  3907 
       
  3908 	RTL_R8(IntrMask);
       
  3909 
       
  3910 	rtl_set_rx_mode(dev);
       
  3911 
       
  3912 	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
       
  3913 
       
  3914 	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
       
  3915 
       
  3916 	RTL_W16(IntrMask, tp->intr_event);
       
  3917 }
       
  3918 
       
  3919 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
       
  3920 {
       
  3921 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3922 	int ret = 0;
       
  3923 
       
  3924 	if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
       
  3925 		return -EINVAL;
       
  3926 
       
  3927 	dev->mtu = new_mtu;
       
  3928 
       
  3929 	if (!netif_running(dev))
       
  3930 		goto out;
       
  3931 
       
  3932 	rtl8169_down(dev);
       
  3933 
       
  3934 	rtl8169_set_rxbufsize(tp, dev->mtu);
       
  3935 
       
  3936 	ret = rtl8169_init_ring(dev);
       
  3937 	if (ret < 0)
       
  3938 		goto out;
       
  3939 
       
  3940 	napi_enable(&tp->napi);
       
  3941 
       
  3942 	rtl_hw_start(dev);
       
  3943 
       
  3944 	rtl8169_request_timer(dev);
       
  3945 
       
  3946 out:
       
  3947 	return ret;
       
  3948 }
       
  3949 
       
  3950 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
       
  3951 {
       
  3952 	desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
       
  3953 	desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
       
  3954 }
       
  3955 
       
  3956 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
       
  3957 				struct sk_buff **sk_buff, struct RxDesc *desc)
       
  3958 {
       
  3959 	struct pci_dev *pdev = tp->pci_dev;
       
  3960 
       
  3961 	pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
       
  3962 			 PCI_DMA_FROMDEVICE);
       
  3963 	dev_kfree_skb(*sk_buff);
       
  3964 	*sk_buff = NULL;
       
  3965 	rtl8169_make_unusable_by_asic(desc);
       
  3966 }
       
  3967 
       
  3968 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
       
  3969 {
       
  3970 	u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
       
  3971 
       
  3972 	desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
       
  3973 }
       
  3974 
       
  3975 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
       
  3976 				       u32 rx_buf_sz)
       
  3977 {
       
  3978 	desc->addr = cpu_to_le64(mapping);
       
  3979 	wmb();
       
  3980 	rtl8169_mark_to_asic(desc, rx_buf_sz);
       
  3981 }
       
  3982 
       
  3983 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
       
  3984 					    struct net_device *dev,
       
  3985 					    struct RxDesc *desc, int rx_buf_sz,
       
  3986 					    unsigned int align)
       
  3987 {
       
  3988 	struct sk_buff *skb;
       
  3989 	dma_addr_t mapping;
       
  3990 	unsigned int pad;
       
  3991 
       
  3992 	pad = align ? align : NET_IP_ALIGN;
       
  3993 
       
  3994 	skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
       
  3995 	if (!skb)
       
  3996 		goto err_out;
       
  3997 
       
  3998 	skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
       
  3999 
       
  4000 	mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
       
  4001 				 PCI_DMA_FROMDEVICE);
       
  4002 
       
  4003 	rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
       
  4004 out:
       
  4005 	return skb;
       
  4006 
       
  4007 err_out:
       
  4008 	rtl8169_make_unusable_by_asic(desc);
       
  4009 	goto out;
       
  4010 }
       
  4011 
       
  4012 static void rtl8169_rx_clear(struct rtl8169_private *tp)
       
  4013 {
       
  4014 	unsigned int i;
       
  4015 
       
  4016 	for (i = 0; i < NUM_RX_DESC; i++) {
       
  4017 		if (tp->Rx_skbuff[i]) {
       
  4018 			rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
       
  4019 					    tp->RxDescArray + i);
       
  4020 		}
       
  4021 	}
       
  4022 }
       
  4023 
       
  4024 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
       
  4025 			   u32 start, u32 end)
       
  4026 {
       
  4027 	u32 cur;
       
  4028 
       
  4029 	for (cur = start; end - cur != 0; cur++) {
       
  4030 		struct sk_buff *skb;
       
  4031 		unsigned int i = cur % NUM_RX_DESC;
       
  4032 
       
  4033 		WARN_ON((s32)(end - cur) < 0);
       
  4034 
       
  4035 		if (tp->Rx_skbuff[i])
       
  4036 			continue;
       
  4037 
       
  4038 		skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
       
  4039 					   tp->RxDescArray + i,
       
  4040 					   tp->rx_buf_sz, tp->align);
       
  4041 		if (!skb)
       
  4042 			break;
       
  4043 
       
  4044 		tp->Rx_skbuff[i] = skb;
       
  4045 	}
       
  4046 	return cur - start;
       
  4047 }
       
  4048 
       
  4049 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
       
  4050 {
       
  4051 	desc->opts1 |= cpu_to_le32(RingEnd);
       
  4052 }
       
  4053 
       
  4054 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
       
  4055 {
       
  4056 	tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
       
  4057 }
       
  4058 
       
  4059 static int rtl8169_init_ring(struct net_device *dev)
       
  4060 {
       
  4061 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4062 
       
  4063 	rtl8169_init_ring_indexes(tp);
       
  4064 
       
  4065 	memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
       
  4066 	memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
       
  4067 
       
  4068 	if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
       
  4069 		goto err_out;
       
  4070 
       
  4071 	rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
       
  4072 
       
  4073 	return 0;
       
  4074 
       
  4075 err_out:
       
  4076 	rtl8169_rx_clear(tp);
       
  4077 	return -ENOMEM;
       
  4078 }
       
  4079 
       
  4080 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
       
  4081 				 struct TxDesc *desc)
       
  4082 {
       
  4083 	unsigned int len = tx_skb->len;
       
  4084 
       
  4085 	pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
       
  4086 	desc->opts1 = 0x00;
       
  4087 	desc->opts2 = 0x00;
       
  4088 	desc->addr = 0x00;
       
  4089 	tx_skb->len = 0;
       
  4090 }
       
  4091 
       
  4092 static void rtl8169_tx_clear(struct rtl8169_private *tp)
       
  4093 {
       
  4094 	unsigned int i;
       
  4095 
       
  4096 	for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
       
  4097 		unsigned int entry = i % NUM_TX_DESC;
       
  4098 		struct ring_info *tx_skb = tp->tx_skb + entry;
       
  4099 		unsigned int len = tx_skb->len;
       
  4100 
       
  4101 		if (len) {
       
  4102 			struct sk_buff *skb = tx_skb->skb;
       
  4103 
       
  4104 			rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
       
  4105 					     tp->TxDescArray + entry);
       
  4106 			if (skb) {
       
  4107 				dev_kfree_skb(skb);
       
  4108 				tx_skb->skb = NULL;
       
  4109 			}
       
  4110 			tp->dev->stats.tx_dropped++;
       
  4111 		}
       
  4112 	}
       
  4113 	tp->cur_tx = tp->dirty_tx = 0;
       
  4114 }
       
  4115 
       
  4116 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
       
  4117 {
       
  4118 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4119 
       
  4120 	PREPARE_DELAYED_WORK(&tp->task, task);
       
  4121 	schedule_delayed_work(&tp->task, 4);
       
  4122 }
       
  4123 
       
  4124 static void rtl8169_wait_for_quiescence(struct net_device *dev)
       
  4125 {
       
  4126 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4127 	void __iomem *ioaddr = tp->mmio_addr;
       
  4128 
       
  4129 	synchronize_irq(dev->irq);
       
  4130 
       
  4131 	/* Wait for any pending NAPI task to complete */
       
  4132 	napi_disable(&tp->napi);
       
  4133 
       
  4134 	rtl8169_irq_mask_and_ack(ioaddr);
       
  4135 
       
  4136 	tp->intr_mask = 0xffff;
       
  4137 	RTL_W16(IntrMask, tp->intr_event);
       
  4138 	napi_enable(&tp->napi);
       
  4139 }
       
  4140 
       
  4141 static void rtl8169_reinit_task(struct work_struct *work)
       
  4142 {
       
  4143 	struct rtl8169_private *tp =
       
  4144 		container_of(work, struct rtl8169_private, task.work);
       
  4145 	struct net_device *dev = tp->dev;
       
  4146 	int ret;
       
  4147 
       
  4148 	rtnl_lock();
       
  4149 
       
  4150 	if (!netif_running(dev))
       
  4151 		goto out_unlock;
       
  4152 
       
  4153 	rtl8169_wait_for_quiescence(dev);
       
  4154 	rtl8169_close(dev);
       
  4155 
       
  4156 	ret = rtl8169_open(dev);
       
  4157 	if (unlikely(ret < 0)) {
       
  4158 		if (net_ratelimit() && netif_msg_drv(tp)) {
       
  4159 			printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
       
  4160 			       " Rescheduling.\n", dev->name, ret);
       
  4161 		}
       
  4162 		rtl8169_schedule_work(dev, rtl8169_reinit_task);
       
  4163 	}
       
  4164 
       
  4165 out_unlock:
       
  4166 	rtnl_unlock();
       
  4167 }
       
  4168 
       
  4169 static void rtl8169_reset_task(struct work_struct *work)
       
  4170 {
       
  4171 	struct rtl8169_private *tp =
       
  4172 		container_of(work, struct rtl8169_private, task.work);
       
  4173 	struct net_device *dev = tp->dev;
       
  4174 
       
  4175 	rtnl_lock();
       
  4176 
       
  4177 	if (!netif_running(dev))
       
  4178 		goto out_unlock;
       
  4179 
       
  4180 	rtl8169_wait_for_quiescence(dev);
       
  4181 
       
  4182 	rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
       
  4183 	rtl8169_tx_clear(tp);
       
  4184 
       
  4185 	if (tp->dirty_rx == tp->cur_rx) {
       
  4186 		rtl8169_init_ring_indexes(tp);
       
  4187 		rtl_hw_start(dev);
       
  4188 		netif_wake_queue(dev);
       
  4189 		rtl8169_check_link_status(dev, tp, tp->mmio_addr);
       
  4190 	} else {
       
  4191 		if (net_ratelimit() && netif_msg_intr(tp)) {
       
  4192 			printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
       
  4193 			       dev->name);
       
  4194 		}
       
  4195 		rtl8169_schedule_work(dev, rtl8169_reset_task);
       
  4196 	}
       
  4197 
       
  4198 out_unlock:
       
  4199 	rtnl_unlock();
       
  4200 }
       
  4201 
       
  4202 static void rtl8169_tx_timeout(struct net_device *dev)
       
  4203 {
       
  4204 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4205 
       
  4206 	rtl8169_hw_reset(tp->mmio_addr);
       
  4207 
       
  4208 	/* Let's wait a bit while any (async) irq lands on */
       
  4209 	rtl8169_schedule_work(dev, rtl8169_reset_task);
       
  4210 }
       
  4211 
       
  4212 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
       
  4213 			      u32 opts1)
       
  4214 {
       
  4215 	struct skb_shared_info *info = skb_shinfo(skb);
       
  4216 	unsigned int cur_frag, entry;
       
  4217 	struct TxDesc * uninitialized_var(txd);
       
  4218 
       
  4219 	entry = tp->cur_tx;
       
  4220 	for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
       
  4221 		skb_frag_t *frag = info->frags + cur_frag;
       
  4222 		dma_addr_t mapping;
       
  4223 		u32 status, len;
       
  4224 		void *addr;
       
  4225 
       
  4226 		entry = (entry + 1) % NUM_TX_DESC;
       
  4227 
       
  4228 		txd = tp->TxDescArray + entry;
       
  4229 		len = frag->size;
       
  4230 		addr = ((void *) page_address(frag->page)) + frag->page_offset;
       
  4231 		mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
       
  4232 
       
  4233 		/* anti gcc 2.95.3 bugware (sic) */
       
  4234 		status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
       
  4235 
       
  4236 		txd->opts1 = cpu_to_le32(status);
       
  4237 		txd->addr = cpu_to_le64(mapping);
       
  4238 
       
  4239 		tp->tx_skb[entry].len = len;
       
  4240 	}
       
  4241 
       
  4242 	if (cur_frag) {
       
  4243 		tp->tx_skb[entry].skb = skb;
       
  4244 		txd->opts1 |= cpu_to_le32(LastFrag);
       
  4245 	}
       
  4246 
       
  4247 	return cur_frag;
       
  4248 }
       
  4249 
       
  4250 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
       
  4251 {
       
  4252 	if (dev->features & NETIF_F_TSO) {
       
  4253 		u32 mss = skb_shinfo(skb)->gso_size;
       
  4254 
       
  4255 		if (mss)
       
  4256 			return LargeSend | ((mss & MSSMask) << MSSShift);
       
  4257 	}
       
  4258 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
       
  4259 		const struct iphdr *ip = ip_hdr(skb);
       
  4260 
       
  4261 		if (ip->protocol == IPPROTO_TCP)
       
  4262 			return IPCS | TCPCS;
       
  4263 		else if (ip->protocol == IPPROTO_UDP)
       
  4264 			return IPCS | UDPCS;
       
  4265 		WARN_ON(1);	/* we need a WARN() */
       
  4266 	}
       
  4267 	return 0;
       
  4268 }
       
  4269 
       
  4270 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
       
  4271 				      struct net_device *dev)
       
  4272 {
       
  4273 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4274 	unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
       
  4275 	struct TxDesc *txd = tp->TxDescArray + entry;
       
  4276 	void __iomem *ioaddr = tp->mmio_addr;
       
  4277 	dma_addr_t mapping;
       
  4278 	u32 status, len;
       
  4279 	u32 opts1;
       
  4280 
       
  4281 	if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
       
  4282 		if (netif_msg_drv(tp)) {
       
  4283 			printk(KERN_ERR
       
  4284 			       "%s: BUG! Tx Ring full when queue awake!\n",
       
  4285 			       dev->name);
       
  4286 		}
       
  4287 		goto err_stop;
       
  4288 	}
       
  4289 
       
  4290 	if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
       
  4291 		goto err_stop;
       
  4292 
       
  4293 	opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
       
  4294 
       
  4295 	frags = rtl8169_xmit_frags(tp, skb, opts1);
       
  4296 	if (frags) {
       
  4297 		len = skb_headlen(skb);
       
  4298 		opts1 |= FirstFrag;
       
  4299 	} else {
       
  4300 		len = skb->len;
       
  4301 		opts1 |= FirstFrag | LastFrag;
       
  4302 		tp->tx_skb[entry].skb = skb;
       
  4303 	}
       
  4304 
       
  4305 	mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
       
  4306 
       
  4307 	tp->tx_skb[entry].len = len;
       
  4308 	txd->addr = cpu_to_le64(mapping);
       
  4309 	txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
       
  4310 
       
  4311 	wmb();
       
  4312 
       
  4313 	/* anti gcc 2.95.3 bugware (sic) */
       
  4314 	status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
       
  4315 	txd->opts1 = cpu_to_le32(status);
       
  4316 
       
  4317 	tp->cur_tx += frags + 1;
       
  4318 
       
  4319 	smp_wmb();
       
  4320 
       
  4321 	RTL_W8(TxPoll, NPQ);	/* set polling bit */
       
  4322 
       
  4323 	if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
       
  4324 		netif_stop_queue(dev);
       
  4325 		smp_rmb();
       
  4326 		if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
       
  4327 			netif_wake_queue(dev);
       
  4328 	}
       
  4329 
       
  4330 	return NETDEV_TX_OK;
       
  4331 
       
  4332 err_stop:
       
  4333 	netif_stop_queue(dev);
       
  4334 	dev->stats.tx_dropped++;
       
  4335 	return NETDEV_TX_BUSY;
       
  4336 }
       
  4337 
       
  4338 static void rtl8169_pcierr_interrupt(struct net_device *dev)
       
  4339 {
       
  4340 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4341 	struct pci_dev *pdev = tp->pci_dev;
       
  4342 	void __iomem *ioaddr = tp->mmio_addr;
       
  4343 	u16 pci_status, pci_cmd;
       
  4344 
       
  4345 	pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
       
  4346 	pci_read_config_word(pdev, PCI_STATUS, &pci_status);
       
  4347 
       
  4348 	if (netif_msg_intr(tp)) {
       
  4349 		printk(KERN_ERR
       
  4350 		       "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
       
  4351 		       dev->name, pci_cmd, pci_status);
       
  4352 	}
       
  4353 
       
  4354 	/*
       
  4355 	 * The recovery sequence below admits a very elaborated explanation:
       
  4356 	 * - it seems to work;
       
  4357 	 * - I did not see what else could be done;
       
  4358 	 * - it makes iop3xx happy.
       
  4359 	 *
       
  4360 	 * Feel free to adjust to your needs.
       
  4361 	 */
       
  4362 	if (pdev->broken_parity_status)
       
  4363 		pci_cmd &= ~PCI_COMMAND_PARITY;
       
  4364 	else
       
  4365 		pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
       
  4366 
       
  4367 	pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
       
  4368 
       
  4369 	pci_write_config_word(pdev, PCI_STATUS,
       
  4370 		pci_status & (PCI_STATUS_DETECTED_PARITY |
       
  4371 		PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
       
  4372 		PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
       
  4373 
       
  4374 	/* The infamous DAC f*ckup only happens at boot time */
       
  4375 	if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
       
  4376 		if (netif_msg_intr(tp))
       
  4377 			printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
       
  4378 		tp->cp_cmd &= ~PCIDAC;
       
  4379 		RTL_W16(CPlusCmd, tp->cp_cmd);
       
  4380 		dev->features &= ~NETIF_F_HIGHDMA;
       
  4381 	}
       
  4382 
       
  4383 	rtl8169_hw_reset(ioaddr);
       
  4384 
       
  4385 	rtl8169_schedule_work(dev, rtl8169_reinit_task);
       
  4386 }
       
  4387 
       
  4388 static void rtl8169_tx_interrupt(struct net_device *dev,
       
  4389 				 struct rtl8169_private *tp,
       
  4390 				 void __iomem *ioaddr)
       
  4391 {
       
  4392 	unsigned int dirty_tx, tx_left;
       
  4393 
       
  4394 	dirty_tx = tp->dirty_tx;
       
  4395 	smp_rmb();
       
  4396 	tx_left = tp->cur_tx - dirty_tx;
       
  4397 
       
  4398 	while (tx_left > 0) {
       
  4399 		unsigned int entry = dirty_tx % NUM_TX_DESC;
       
  4400 		struct ring_info *tx_skb = tp->tx_skb + entry;
       
  4401 		u32 len = tx_skb->len;
       
  4402 		u32 status;
       
  4403 
       
  4404 		rmb();
       
  4405 		status = le32_to_cpu(tp->TxDescArray[entry].opts1);
       
  4406 		if (status & DescOwn)
       
  4407 			break;
       
  4408 
       
  4409 		dev->stats.tx_bytes += len;
       
  4410 		dev->stats.tx_packets++;
       
  4411 
       
  4412 		rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
       
  4413 
       
  4414 		if (status & LastFrag) {
       
  4415 			dev_kfree_skb(tx_skb->skb);
       
  4416 			tx_skb->skb = NULL;
       
  4417 		}
       
  4418 		dirty_tx++;
       
  4419 		tx_left--;
       
  4420 	}
       
  4421 
       
  4422 	if (tp->dirty_tx != dirty_tx) {
       
  4423 		tp->dirty_tx = dirty_tx;
       
  4424 		smp_wmb();
       
  4425 		if (netif_queue_stopped(dev) &&
       
  4426 		    (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
       
  4427 			netif_wake_queue(dev);
       
  4428 		}
       
  4429 		/*
       
  4430 		 * 8168 hack: TxPoll requests are lost when the Tx packets are
       
  4431 		 * too close. Let's kick an extra TxPoll request when a burst
       
  4432 		 * of start_xmit activity is detected (if it is not detected,
       
  4433 		 * it is slow enough). -- FR
       
  4434 		 */
       
  4435 		smp_rmb();
       
  4436 		if (tp->cur_tx != dirty_tx)
       
  4437 			RTL_W8(TxPoll, NPQ);
       
  4438 	}
       
  4439 }
       
  4440 
       
  4441 static inline int rtl8169_fragmented_frame(u32 status)
       
  4442 {
       
  4443 	return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
       
  4444 }
       
  4445 
       
  4446 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
       
  4447 {
       
  4448 	u32 opts1 = le32_to_cpu(desc->opts1);
       
  4449 	u32 status = opts1 & RxProtoMask;
       
  4450 
       
  4451 	if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
       
  4452 	    ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
       
  4453 	    ((status == RxProtoIP) && !(opts1 & IPFail)))
       
  4454 		skb->ip_summed = CHECKSUM_UNNECESSARY;
       
  4455 	else
       
  4456 		skb->ip_summed = CHECKSUM_NONE;
       
  4457 }
       
  4458 
       
  4459 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
       
  4460 				       struct rtl8169_private *tp, int pkt_size,
       
  4461 				       dma_addr_t addr)
       
  4462 {
       
  4463 	struct sk_buff *skb;
       
  4464 	bool done = false;
       
  4465 
       
  4466 	if (pkt_size >= rx_copybreak)
       
  4467 		goto out;
       
  4468 
       
  4469 	skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
       
  4470 	if (!skb)
       
  4471 		goto out;
       
  4472 
       
  4473 	pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
       
  4474 				    PCI_DMA_FROMDEVICE);
       
  4475 	skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
       
  4476 	*sk_buff = skb;
       
  4477 	done = true;
       
  4478 out:
       
  4479 	return done;
       
  4480 }
       
  4481 
       
  4482 static int rtl8169_rx_interrupt(struct net_device *dev,
       
  4483 				struct rtl8169_private *tp,
       
  4484 				void __iomem *ioaddr, u32 budget)
       
  4485 {
       
  4486 	unsigned int cur_rx, rx_left;
       
  4487 	unsigned int delta, count;
       
  4488 
       
  4489 	cur_rx = tp->cur_rx;
       
  4490 	rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
       
  4491 	rx_left = min(rx_left, budget);
       
  4492 
       
  4493 	for (; rx_left > 0; rx_left--, cur_rx++) {
       
  4494 		unsigned int entry = cur_rx % NUM_RX_DESC;
       
  4495 		struct RxDesc *desc = tp->RxDescArray + entry;
       
  4496 		u32 status;
       
  4497 
       
  4498 		rmb();
       
  4499 		status = le32_to_cpu(desc->opts1);
       
  4500 
       
  4501 		if (status & DescOwn)
       
  4502 			break;
       
  4503 		if (unlikely(status & RxRES)) {
       
  4504 			if (netif_msg_rx_err(tp)) {
       
  4505 				printk(KERN_INFO
       
  4506 				       "%s: Rx ERROR. status = %08x\n",
       
  4507 				       dev->name, status);
       
  4508 			}
       
  4509 			dev->stats.rx_errors++;
       
  4510 			if (status & (RxRWT | RxRUNT))
       
  4511 				dev->stats.rx_length_errors++;
       
  4512 			if (status & RxCRC)
       
  4513 				dev->stats.rx_crc_errors++;
       
  4514 			if (status & RxFOVF) {
       
  4515 				rtl8169_schedule_work(dev, rtl8169_reset_task);
       
  4516 				dev->stats.rx_fifo_errors++;
       
  4517 			}
       
  4518 			rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
       
  4519 		} else {
       
  4520 			struct sk_buff *skb = tp->Rx_skbuff[entry];
       
  4521 			dma_addr_t addr = le64_to_cpu(desc->addr);
       
  4522 			int pkt_size = (status & 0x00001FFF) - 4;
       
  4523 			struct pci_dev *pdev = tp->pci_dev;
       
  4524 
       
  4525 			/*
       
  4526 			 * The driver does not support incoming fragmented
       
  4527 			 * frames. They are seen as a symptom of over-mtu
       
  4528 			 * sized frames.
       
  4529 			 */
       
  4530 			if (unlikely(rtl8169_fragmented_frame(status))) {
       
  4531 				dev->stats.rx_dropped++;
       
  4532 				dev->stats.rx_length_errors++;
       
  4533 				rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
       
  4534 				continue;
       
  4535 			}
       
  4536 
       
  4537 			rtl8169_rx_csum(skb, desc);
       
  4538 
       
  4539 			if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
       
  4540 				pci_dma_sync_single_for_device(pdev, addr,
       
  4541 					pkt_size, PCI_DMA_FROMDEVICE);
       
  4542 				rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
       
  4543 			} else {
       
  4544 				pci_unmap_single(pdev, addr, tp->rx_buf_sz,
       
  4545 						 PCI_DMA_FROMDEVICE);
       
  4546 				tp->Rx_skbuff[entry] = NULL;
       
  4547 			}
       
  4548 
       
  4549 			skb_put(skb, pkt_size);
       
  4550 			skb->protocol = eth_type_trans(skb, dev);
       
  4551 
       
  4552 			if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
       
  4553 				netif_receive_skb(skb);
       
  4554 
       
  4555 			dev->stats.rx_bytes += pkt_size;
       
  4556 			dev->stats.rx_packets++;
       
  4557 		}
       
  4558 
       
  4559 		/* Work around for AMD plateform. */
       
  4560 		if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
       
  4561 		    (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
       
  4562 			desc->opts2 = 0;
       
  4563 			cur_rx++;
       
  4564 		}
       
  4565 	}
       
  4566 
       
  4567 	count = cur_rx - tp->cur_rx;
       
  4568 	tp->cur_rx = cur_rx;
       
  4569 
       
  4570 	delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
       
  4571 	if (!delta && count && netif_msg_intr(tp))
       
  4572 		printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
       
  4573 	tp->dirty_rx += delta;
       
  4574 
       
  4575 	/*
       
  4576 	 * FIXME: until there is periodic timer to try and refill the ring,
       
  4577 	 * a temporary shortage may definitely kill the Rx process.
       
  4578 	 * - disable the asic to try and avoid an overflow and kick it again
       
  4579 	 *   after refill ?
       
  4580 	 * - how do others driver handle this condition (Uh oh...).
       
  4581 	 */
       
  4582 	if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
       
  4583 		printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
       
  4584 
       
  4585 	return count;
       
  4586 }
       
  4587 
       
  4588 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
       
  4589 {
       
  4590 	struct net_device *dev = dev_instance;
       
  4591 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4592 	void __iomem *ioaddr = tp->mmio_addr;
       
  4593 	int handled = 0;
       
  4594 	int status;
       
  4595 
       
  4596 	/* loop handling interrupts until we have no new ones or
       
  4597 	 * we hit a invalid/hotplug case.
       
  4598 	 */
       
  4599 	status = RTL_R16(IntrStatus);
       
  4600 	while (status && status != 0xffff) {
       
  4601 		handled = 1;
       
  4602 
       
  4603 		/* Handle all of the error cases first. These will reset
       
  4604 		 * the chip, so just exit the loop.
       
  4605 		 */
       
  4606 		if (unlikely(!netif_running(dev))) {
       
  4607 			rtl8169_asic_down(ioaddr);
       
  4608 			break;
       
  4609 		}
       
  4610 
       
  4611 		/* Work around for rx fifo overflow */
       
  4612 		if (unlikely(status & RxFIFOOver) &&
       
  4613 		(tp->mac_version == RTL_GIGA_MAC_VER_11)) {
       
  4614 			netif_stop_queue(dev);
       
  4615 			rtl8169_tx_timeout(dev);
       
  4616 			break;
       
  4617 		}
       
  4618 
       
  4619 		if (unlikely(status & SYSErr)) {
       
  4620 			rtl8169_pcierr_interrupt(dev);
       
  4621 			break;
       
  4622 		}
       
  4623 
       
  4624 		if (status & LinkChg)
       
  4625 			rtl8169_check_link_status(dev, tp, ioaddr);
       
  4626 
       
  4627 		/* We need to see the lastest version of tp->intr_mask to
       
  4628 		 * avoid ignoring an MSI interrupt and having to wait for
       
  4629 		 * another event which may never come.
       
  4630 		 */
       
  4631 		smp_rmb();
       
  4632 		if (status & tp->intr_mask & tp->napi_event) {
       
  4633 			RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
       
  4634 			tp->intr_mask = ~tp->napi_event;
       
  4635 
       
  4636 			if (likely(napi_schedule_prep(&tp->napi)))
       
  4637 				__napi_schedule(&tp->napi);
       
  4638 			else if (netif_msg_intr(tp)) {
       
  4639 				printk(KERN_INFO "%s: interrupt %04x in poll\n",
       
  4640 				dev->name, status);
       
  4641 			}
       
  4642 		}
       
  4643 
       
  4644 		/* We only get a new MSI interrupt when all active irq
       
  4645 		 * sources on the chip have been acknowledged. So, ack
       
  4646 		 * everything we've seen and check if new sources have become
       
  4647 		 * active to avoid blocking all interrupts from the chip.
       
  4648 		 */
       
  4649 		RTL_W16(IntrStatus,
       
  4650 			(status & RxFIFOOver) ? (status | RxOverflow) : status);
       
  4651 		status = RTL_R16(IntrStatus);
       
  4652 	}
       
  4653 
       
  4654 	return IRQ_RETVAL(handled);
       
  4655 }
       
  4656 
       
  4657 static int rtl8169_poll(struct napi_struct *napi, int budget)
       
  4658 {
       
  4659 	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
       
  4660 	struct net_device *dev = tp->dev;
       
  4661 	void __iomem *ioaddr = tp->mmio_addr;
       
  4662 	int work_done;
       
  4663 
       
  4664 	work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
       
  4665 	rtl8169_tx_interrupt(dev, tp, ioaddr);
       
  4666 
       
  4667 	if (work_done < budget) {
       
  4668 		napi_complete(napi);
       
  4669 
       
  4670 		/* We need for force the visibility of tp->intr_mask
       
  4671 		 * for other CPUs, as we can loose an MSI interrupt
       
  4672 		 * and potentially wait for a retransmit timeout if we don't.
       
  4673 		 * The posted write to IntrMask is safe, as it will
       
  4674 		 * eventually make it to the chip and we won't loose anything
       
  4675 		 * until it does.
       
  4676 		 */
       
  4677 		tp->intr_mask = 0xffff;
       
  4678 		smp_wmb();
       
  4679 		RTL_W16(IntrMask, tp->intr_event);
       
  4680 	}
       
  4681 
       
  4682 	return work_done;
       
  4683 }
       
  4684 
       
  4685 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
       
  4686 {
       
  4687 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4688 
       
  4689 	if (tp->mac_version > RTL_GIGA_MAC_VER_06)
       
  4690 		return;
       
  4691 
       
  4692 	dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
       
  4693 	RTL_W32(RxMissed, 0);
       
  4694 }
       
  4695 
       
  4696 static void rtl8169_down(struct net_device *dev)
       
  4697 {
       
  4698 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4699 	void __iomem *ioaddr = tp->mmio_addr;
       
  4700 	unsigned int intrmask;
       
  4701 
       
  4702 	rtl8169_delete_timer(dev);
       
  4703 
       
  4704 	netif_stop_queue(dev);
       
  4705 
       
  4706 	napi_disable(&tp->napi);
       
  4707 
       
  4708 core_down:
       
  4709 	spin_lock_irq(&tp->lock);
       
  4710 
       
  4711 	rtl8169_asic_down(ioaddr);
       
  4712 
       
  4713 	rtl8169_rx_missed(dev, ioaddr);
       
  4714 
       
  4715 	spin_unlock_irq(&tp->lock);
       
  4716 
       
  4717 	synchronize_irq(dev->irq);
       
  4718 
       
  4719 	/* Give a racing hard_start_xmit a few cycles to complete. */
       
  4720 	synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
       
  4721 
       
  4722 	/*
       
  4723 	 * And now for the 50k$ question: are IRQ disabled or not ?
       
  4724 	 *
       
  4725 	 * Two paths lead here:
       
  4726 	 * 1) dev->close
       
  4727 	 *    -> netif_running() is available to sync the current code and the
       
  4728 	 *       IRQ handler. See rtl8169_interrupt for details.
       
  4729 	 * 2) dev->change_mtu
       
  4730 	 *    -> rtl8169_poll can not be issued again and re-enable the
       
  4731 	 *       interruptions. Let's simply issue the IRQ down sequence again.
       
  4732 	 *
       
  4733 	 * No loop if hotpluged or major error (0xffff).
       
  4734 	 */
       
  4735 	intrmask = RTL_R16(IntrMask);
       
  4736 	if (intrmask && (intrmask != 0xffff))
       
  4737 		goto core_down;
       
  4738 
       
  4739 	rtl8169_tx_clear(tp);
       
  4740 
       
  4741 	rtl8169_rx_clear(tp);
       
  4742 }
       
  4743 
       
  4744 static int rtl8169_close(struct net_device *dev)
       
  4745 {
       
  4746 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4747 	struct pci_dev *pdev = tp->pci_dev;
       
  4748 
       
  4749 	/* update counters before going down */
       
  4750 	rtl8169_update_counters(dev);
       
  4751 
       
  4752 	rtl8169_down(dev);
       
  4753 
       
  4754 	free_irq(dev->irq, dev);
       
  4755 
       
  4756 	pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
       
  4757 			    tp->RxPhyAddr);
       
  4758 	pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
       
  4759 			    tp->TxPhyAddr);
       
  4760 	tp->TxDescArray = NULL;
       
  4761 	tp->RxDescArray = NULL;
       
  4762 
       
  4763 	return 0;
       
  4764 }
       
  4765 
       
  4766 static void rtl_set_rx_mode(struct net_device *dev)
       
  4767 {
       
  4768 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4769 	void __iomem *ioaddr = tp->mmio_addr;
       
  4770 	unsigned long flags;
       
  4771 	u32 mc_filter[2];	/* Multicast hash filter */
       
  4772 	int rx_mode;
       
  4773 	u32 tmp = 0;
       
  4774 
       
  4775 	if (dev->flags & IFF_PROMISC) {
       
  4776 		/* Unconditionally log net taps. */
       
  4777 		if (netif_msg_link(tp)) {
       
  4778 			printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
       
  4779 			       dev->name);
       
  4780 		}
       
  4781 		rx_mode =
       
  4782 		    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
       
  4783 		    AcceptAllPhys;
       
  4784 		mc_filter[1] = mc_filter[0] = 0xffffffff;
       
  4785 	} else if ((dev->mc_count > multicast_filter_limit) ||
       
  4786 		   (dev->flags & IFF_ALLMULTI)) {
       
  4787 		/* Too many to filter perfectly -- accept all multicasts. */
       
  4788 		rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
       
  4789 		mc_filter[1] = mc_filter[0] = 0xffffffff;
       
  4790 	} else {
       
  4791 		struct dev_mc_list *mclist;
       
  4792 		unsigned int i;
       
  4793 
       
  4794 		rx_mode = AcceptBroadcast | AcceptMyPhys;
       
  4795 		mc_filter[1] = mc_filter[0] = 0;
       
  4796 		for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
       
  4797 		     i++, mclist = mclist->next) {
       
  4798 			int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
       
  4799 			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
       
  4800 			rx_mode |= AcceptMulticast;
       
  4801 		}
       
  4802 	}
       
  4803 
       
  4804 	spin_lock_irqsave(&tp->lock, flags);
       
  4805 
       
  4806 	tmp = rtl8169_rx_config | rx_mode |
       
  4807 	      (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
       
  4808 
       
  4809 	if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
       
  4810 		u32 data = mc_filter[0];
       
  4811 
       
  4812 		mc_filter[0] = swab32(mc_filter[1]);
       
  4813 		mc_filter[1] = swab32(data);
       
  4814 	}
       
  4815 
       
  4816 	RTL_W32(MAR0 + 0, mc_filter[0]);
       
  4817 	RTL_W32(MAR0 + 4, mc_filter[1]);
       
  4818 
       
  4819 	RTL_W32(RxConfig, tmp);
       
  4820 
       
  4821 	spin_unlock_irqrestore(&tp->lock, flags);
       
  4822 }
       
  4823 
       
  4824 /**
       
  4825  *  rtl8169_get_stats - Get rtl8169 read/write statistics
       
  4826  *  @dev: The Ethernet Device to get statistics for
       
  4827  *
       
  4828  *  Get TX/RX statistics for rtl8169
       
  4829  */
       
  4830 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
       
  4831 {
       
  4832 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4833 	void __iomem *ioaddr = tp->mmio_addr;
       
  4834 	unsigned long flags;
       
  4835 
       
  4836 	if (netif_running(dev)) {
       
  4837 		spin_lock_irqsave(&tp->lock, flags);
       
  4838 		rtl8169_rx_missed(dev, ioaddr);
       
  4839 		spin_unlock_irqrestore(&tp->lock, flags);
       
  4840 	}
       
  4841 
       
  4842 	return &dev->stats;
       
  4843 }
       
  4844 
       
  4845 static void rtl8169_net_suspend(struct net_device *dev)
       
  4846 {
       
  4847 	if (!netif_running(dev))
       
  4848 		return;
       
  4849 
       
  4850 	netif_device_detach(dev);
       
  4851 	netif_stop_queue(dev);
       
  4852 }
       
  4853 
       
  4854 #ifdef CONFIG_PM
       
  4855 
       
  4856 static int rtl8169_suspend(struct device *device)
       
  4857 {
       
  4858 	struct pci_dev *pdev = to_pci_dev(device);
       
  4859 	struct net_device *dev = pci_get_drvdata(pdev);
       
  4860 
       
  4861 	rtl8169_net_suspend(dev);
       
  4862 
       
  4863 	return 0;
       
  4864 }
       
  4865 
       
  4866 static int rtl8169_resume(struct device *device)
       
  4867 {
       
  4868 	struct pci_dev *pdev = to_pci_dev(device);
       
  4869 	struct net_device *dev = pci_get_drvdata(pdev);
       
  4870 
       
  4871 	if (!netif_running(dev))
       
  4872 		goto out;
       
  4873 
       
  4874 	netif_device_attach(dev);
       
  4875 
       
  4876 	rtl8169_schedule_work(dev, rtl8169_reset_task);
       
  4877 out:
       
  4878 	return 0;
       
  4879 }
       
  4880 
       
  4881 static const struct dev_pm_ops rtl8169_pm_ops = {
       
  4882 	.suspend = rtl8169_suspend,
       
  4883 	.resume = rtl8169_resume,
       
  4884 	.freeze = rtl8169_suspend,
       
  4885 	.thaw = rtl8169_resume,
       
  4886 	.poweroff = rtl8169_suspend,
       
  4887 	.restore = rtl8169_resume,
       
  4888 };
       
  4889 
       
  4890 #define RTL8169_PM_OPS	(&rtl8169_pm_ops)
       
  4891 
       
  4892 #else /* !CONFIG_PM */
       
  4893 
       
  4894 #define RTL8169_PM_OPS	NULL
       
  4895 
       
  4896 #endif /* !CONFIG_PM */
       
  4897 
       
  4898 static void rtl_shutdown(struct pci_dev *pdev)
       
  4899 {
       
  4900 	struct net_device *dev = pci_get_drvdata(pdev);
       
  4901 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4902 	void __iomem *ioaddr = tp->mmio_addr;
       
  4903 
       
  4904 	rtl8169_net_suspend(dev);
       
  4905 
       
  4906 	/* restore original MAC address */
       
  4907 	rtl_rar_set(tp, dev->perm_addr);
       
  4908 
       
  4909 	spin_lock_irq(&tp->lock);
       
  4910 
       
  4911 	rtl8169_asic_down(ioaddr);
       
  4912 
       
  4913 	spin_unlock_irq(&tp->lock);
       
  4914 
       
  4915 	if (system_state == SYSTEM_POWER_OFF) {
       
  4916 		/* WoL fails with some 8168 when the receiver is disabled. */
       
  4917 		if (tp->features & RTL_FEATURE_WOL) {
       
  4918 			pci_clear_master(pdev);
       
  4919 
       
  4920 			RTL_W8(ChipCmd, CmdRxEnb);
       
  4921 			/* PCI commit */
       
  4922 			RTL_R8(ChipCmd);
       
  4923 		}
       
  4924 
       
  4925 		pci_wake_from_d3(pdev, true);
       
  4926 		pci_set_power_state(pdev, PCI_D3hot);
       
  4927 	}
       
  4928 }
       
  4929 
       
  4930 static struct pci_driver rtl8169_pci_driver = {
       
  4931 	.name		= MODULENAME,
       
  4932 	.id_table	= rtl8169_pci_tbl,
       
  4933 	.probe		= rtl8169_init_one,
       
  4934 	.remove		= __devexit_p(rtl8169_remove_one),
       
  4935 	.shutdown	= rtl_shutdown,
       
  4936 	.driver.pm	= RTL8169_PM_OPS,
       
  4937 };
       
  4938 
       
  4939 static int __init rtl8169_init_module(void)
       
  4940 {
       
  4941 	return pci_register_driver(&rtl8169_pci_driver);
       
  4942 }
       
  4943 
       
  4944 static void __exit rtl8169_cleanup_module(void)
       
  4945 {
       
  4946 	pci_unregister_driver(&rtl8169_pci_driver);
       
  4947 }
       
  4948 
       
  4949 module_init(rtl8169_init_module);
       
  4950 module_exit(rtl8169_cleanup_module);