1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2006 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /* e1000_hw.c

    30  * Shared functions for accessing and configuring the MAC

    31  */

    32 

    33 

    34 #include "e1000_hw-2.6.31-ethercat.h"

    35 

    36 static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);

    37 static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);

    38 static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);

    39 static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);

    40 static s32 e1000_get_software_semaphore(struct e1000_hw *hw);

    41 static void e1000_release_software_semaphore(struct e1000_hw *hw);

    42 

    43 static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);

    44 static s32 e1000_check_downshift(struct e1000_hw *hw);

    45 static s32 e1000_check_polarity(struct e1000_hw *hw,

    46 				e1000_rev_polarity *polarity);

    47 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    48 static void e1000_clear_vfta(struct e1000_hw *hw);

    49 static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);

    50 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    51 					      bool link_up);

    52 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    53 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    54 static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);

    55 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    56 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    57 				  u16 *max_length);

    58 static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);

    59 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    60 static s32 e1000_get_software_flag(struct e1000_hw *hw);

    61 static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);

    62 static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);

    63 static s32 e1000_id_led_init(struct e1000_hw *hw);

    64 static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,

    65 						 u32 cnf_base_addr,

    66 						 u32 cnf_size);

    67 static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);

    68 static void e1000_init_rx_addrs(struct e1000_hw *hw);

    69 static void e1000_initialize_hardware_bits(struct e1000_hw *hw);

    70 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);

    71 static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);

    72 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);

    73 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,

    74 				   u16 offset, u8 *sum);

    75 static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw,

    76 				      struct e1000_host_mng_command_header

    77 				      *hdr);

    78 static s32 e1000_mng_write_commit(struct e1000_hw *hw);

    79 static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,

    80 				  struct e1000_phy_info *phy_info);

    81 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    82 				  struct e1000_phy_info *phy_info);

    83 static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,

    84 				  u16 *data);

    85 static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,

    86 				   u16 *data);

    87 static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);

    88 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    89 				  struct e1000_phy_info *phy_info);

    90 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);

    91 static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);

    92 static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index,

    93 					u8 byte);

    94 static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);

    95 static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);

    96 static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,

    97 				u16 *data);

    98 static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,

    99 				 u16 data);

   100 static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,

   101 				  u16 *data);

   102 static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,

   103 				   u16 *data);

   104 static void e1000_release_software_flag(struct e1000_hw *hw);

   105 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

   106 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);

   107 static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);

   108 static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);

   109 static s32 e1000_wait_autoneg(struct e1000_hw *hw);

   110 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

   111 static s32 e1000_set_phy_type(struct e1000_hw *hw);

   112 static void e1000_phy_init_script(struct e1000_hw *hw);

   113 static s32 e1000_setup_copper_link(struct e1000_hw *hw);

   114 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

   115 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

   116 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

   117 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

   118 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

   119 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

   120 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,

   121 				     u16 count);

   122 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

   123 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

   124 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

   125                                       u16 words, u16 *data);

   126 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

   127 					u16 words, u16 *data);

   128 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

   129 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

   130 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

   131 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

   132 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

   133 				  u16 phy_data);

   134 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,

   135 				 u16 *phy_data);

   136 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

   137 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

   138 static void e1000_release_eeprom(struct e1000_hw *hw);

   139 static void e1000_standby_eeprom(struct e1000_hw *hw);

   140 static s32 e1000_set_vco_speed(struct e1000_hw *hw);

   141 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

   142 static s32 e1000_set_phy_mode(struct e1000_hw *hw);

   143 static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);

   144 static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);

   145 static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex);

   146 static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);

   147 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);

   148 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);

   149 

   150 /* IGP cable length table */

   151 static const

   152 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =

   153     { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

   154       5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

   155       25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

   156       40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   157       60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   158       90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   159       100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   160       110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};

   161 

   162 static const

   163 u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =

   164     { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,

   165       0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,

   166       6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,

   167       21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,

   168       40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,

   169       60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,

   170       83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,

   171       104, 109, 114, 118, 121, 124};

   172 

   173 static DEFINE_SPINLOCK(e1000_eeprom_lock);

   174 

   175 /******************************************************************************

   176  * Set the phy type member in the hw struct.

   177  *

   178  * hw - Struct containing variables accessed by shared code

   179  *****************************************************************************/

   180 static s32 e1000_set_phy_type(struct e1000_hw *hw)

   181 {

   182     DEBUGFUNC("e1000_set_phy_type");

   183 

   184     if (hw->mac_type == e1000_undefined)

   185         return -E1000_ERR_PHY_TYPE;

   186 

   187     switch (hw->phy_id) {

   188     case M88E1000_E_PHY_ID:

   189     case M88E1000_I_PHY_ID:

   190     case M88E1011_I_PHY_ID:

   191     case M88E1111_I_PHY_ID:

   192         hw->phy_type = e1000_phy_m88;

   193         break;

   194     case IGP01E1000_I_PHY_ID:

   195         if (hw->mac_type == e1000_82541 ||

   196             hw->mac_type == e1000_82541_rev_2 ||

   197             hw->mac_type == e1000_82547 ||

   198             hw->mac_type == e1000_82547_rev_2) {

   199             hw->phy_type = e1000_phy_igp;

   200             break;

   201         }

   202     case IGP03E1000_E_PHY_ID:

   203         hw->phy_type = e1000_phy_igp_3;

   204         break;

   205     case IFE_E_PHY_ID:

   206     case IFE_PLUS_E_PHY_ID:

   207     case IFE_C_E_PHY_ID:

   208         hw->phy_type = e1000_phy_ife;

   209         break;

   210     case GG82563_E_PHY_ID:

   211         if (hw->mac_type == e1000_80003es2lan) {

   212             hw->phy_type = e1000_phy_gg82563;

   213             break;

   214         }

   215         /* Fall Through */

   216     default:

   217         /* Should never have loaded on this device */

   218         hw->phy_type = e1000_phy_undefined;

   219         return -E1000_ERR_PHY_TYPE;

   220     }

   221 

   222     return E1000_SUCCESS;

   223 }

   224 

   225 /******************************************************************************

   226  * IGP phy init script - initializes the GbE PHY

   227  *

   228  * hw - Struct containing variables accessed by shared code

   229  *****************************************************************************/

   230 static void e1000_phy_init_script(struct e1000_hw *hw)

   231 {

   232     u32 ret_val;

   233     u16 phy_saved_data;

   234 

   235     DEBUGFUNC("e1000_phy_init_script");

   236 

   237     if (hw->phy_init_script) {

   238         msleep(20);

   239 

   240         /* Save off the current value of register 0x2F5B to be restored at

   241          * the end of this routine. */

   242         ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   243 

   244         /* Disabled the PHY transmitter */

   245         e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   246 

   247         msleep(20);

   248 

   249         e1000_write_phy_reg(hw,0x0000,0x0140);

   250 

   251         msleep(5);

   252 

   253         switch (hw->mac_type) {

   254         case e1000_82541:

   255         case e1000_82547:

   256             e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   257 

   258             e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   259 

   260             e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   261 

   262             e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   263 

   264             e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   265 

   266             e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   267 

   268             e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   269 

   270             e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   271 

   272             e1000_write_phy_reg(hw, 0x2010, 0x0008);

   273             break;

   274 

   275         case e1000_82541_rev_2:

   276         case e1000_82547_rev_2:

   277             e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   278             break;

   279         default:

   280             break;

   281         }

   282 

   283         e1000_write_phy_reg(hw, 0x0000, 0x3300);

   284 

   285         msleep(20);

   286 

   287         /* Now enable the transmitter */

   288         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   289 

   290         if (hw->mac_type == e1000_82547) {

   291             u16 fused, fine, coarse;

   292 

   293             /* Move to analog registers page */

   294             e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);

   295 

   296             if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   297                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);

   298 

   299                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   300                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   301 

   302                 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   303                     coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;

   304                     fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   305                 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   306                     fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   307 

   308                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   309                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   310                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   311 

   312                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);

   313                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,

   314                                     IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   315             }

   316         }

   317     }

   318 }

   319 

   320 /******************************************************************************

   321  * Set the mac type member in the hw struct.

   322  *

   323  * hw - Struct containing variables accessed by shared code

   324  *****************************************************************************/

   325 s32 e1000_set_mac_type(struct e1000_hw *hw)

   326 {

   327 	DEBUGFUNC("e1000_set_mac_type");

   328 

   329 	switch (hw->device_id) {

   330 	case E1000_DEV_ID_82542:

   331 		switch (hw->revision_id) {

   332 		case E1000_82542_2_0_REV_ID:

   333 			hw->mac_type = e1000_82542_rev2_0;

   334 			break;

   335 		case E1000_82542_2_1_REV_ID:

   336 			hw->mac_type = e1000_82542_rev2_1;

   337 			break;

   338 		default:

   339 			/* Invalid 82542 revision ID */

   340 			return -E1000_ERR_MAC_TYPE;

   341 		}

   342 		break;

   343 	case E1000_DEV_ID_82543GC_FIBER:

   344 	case E1000_DEV_ID_82543GC_COPPER:

   345 		hw->mac_type = e1000_82543;

   346 		break;

   347 	case E1000_DEV_ID_82544EI_COPPER:

   348 	case E1000_DEV_ID_82544EI_FIBER:

   349 	case E1000_DEV_ID_82544GC_COPPER:

   350 	case E1000_DEV_ID_82544GC_LOM:

   351 		hw->mac_type = e1000_82544;

   352 		break;

   353 	case E1000_DEV_ID_82540EM:

   354 	case E1000_DEV_ID_82540EM_LOM:

   355 	case E1000_DEV_ID_82540EP:

   356 	case E1000_DEV_ID_82540EP_LOM:

   357 	case E1000_DEV_ID_82540EP_LP:

   358 		hw->mac_type = e1000_82540;

   359 		break;

   360 	case E1000_DEV_ID_82545EM_COPPER:

   361 	case E1000_DEV_ID_82545EM_FIBER:

   362 		hw->mac_type = e1000_82545;

   363 		break;

   364 	case E1000_DEV_ID_82545GM_COPPER:

   365 	case E1000_DEV_ID_82545GM_FIBER:

   366 	case E1000_DEV_ID_82545GM_SERDES:

   367 		hw->mac_type = e1000_82545_rev_3;

   368 		break;

   369 	case E1000_DEV_ID_82546EB_COPPER:

   370 	case E1000_DEV_ID_82546EB_FIBER:

   371 	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   372 		hw->mac_type = e1000_82546;

   373 		break;

   374 	case E1000_DEV_ID_82546GB_COPPER:

   375 	case E1000_DEV_ID_82546GB_FIBER:

   376 	case E1000_DEV_ID_82546GB_SERDES:

   377 	case E1000_DEV_ID_82546GB_PCIE:

   378 	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   379 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   380 		hw->mac_type = e1000_82546_rev_3;

   381 		break;

   382 	case E1000_DEV_ID_82541EI:

   383 	case E1000_DEV_ID_82541EI_MOBILE:

   384 	case E1000_DEV_ID_82541ER_LOM:

   385 		hw->mac_type = e1000_82541;

   386 		break;

   387 	case E1000_DEV_ID_82541ER:

   388 	case E1000_DEV_ID_82541GI:

   389 	case E1000_DEV_ID_82541GI_LF:

   390 	case E1000_DEV_ID_82541GI_MOBILE:

   391 		hw->mac_type = e1000_82541_rev_2;

   392 		break;

   393 	case E1000_DEV_ID_82547EI:

   394 	case E1000_DEV_ID_82547EI_MOBILE:

   395 		hw->mac_type = e1000_82547;

   396 		break;

   397 	case E1000_DEV_ID_82547GI:

   398 		hw->mac_type = e1000_82547_rev_2;

   399 		break;

   400 	case E1000_DEV_ID_82571EB_COPPER:

   401 	case E1000_DEV_ID_82571EB_FIBER:

   402 	case E1000_DEV_ID_82571EB_SERDES:

   403 	case E1000_DEV_ID_82571EB_SERDES_DUAL:

   404 	case E1000_DEV_ID_82571EB_SERDES_QUAD:

   405 	case E1000_DEV_ID_82571EB_QUAD_COPPER:

   406 	case E1000_DEV_ID_82571PT_QUAD_COPPER:

   407 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   408 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:

   409 		hw->mac_type = e1000_82571;

   410 		break;

   411 	case E1000_DEV_ID_82572EI_COPPER:

   412 	case E1000_DEV_ID_82572EI_FIBER:

   413 	case E1000_DEV_ID_82572EI_SERDES:

   414 	case E1000_DEV_ID_82572EI:

   415 		hw->mac_type = e1000_82572;

   416 		break;

   417 	case E1000_DEV_ID_82573E:

   418 	case E1000_DEV_ID_82573E_IAMT:

   419 	case E1000_DEV_ID_82573L:

   420 		hw->mac_type = e1000_82573;

   421 		break;

   422 	case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:

   423 	case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:

   424 	case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:

   425 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   426 		hw->mac_type = e1000_80003es2lan;

   427 		break;

   428 	case E1000_DEV_ID_ICH8_IGP_M_AMT:

   429 	case E1000_DEV_ID_ICH8_IGP_AMT:

   430 	case E1000_DEV_ID_ICH8_IGP_C:

   431 	case E1000_DEV_ID_ICH8_IFE:

   432 	case E1000_DEV_ID_ICH8_IFE_GT:

   433 	case E1000_DEV_ID_ICH8_IFE_G:

   434 	case E1000_DEV_ID_ICH8_IGP_M:

   435 		hw->mac_type = e1000_ich8lan;

   436 		break;

   437 	default:

   438 		/* Should never have loaded on this device */

   439 		return -E1000_ERR_MAC_TYPE;

   440 	}

   441 

   442 	switch (hw->mac_type) {

   443 	case e1000_ich8lan:

   444 		hw->swfwhw_semaphore_present = true;

   445 		hw->asf_firmware_present = true;

   446 		break;

   447 	case e1000_80003es2lan:

   448 		hw->swfw_sync_present = true;

   449 		/* fall through */

   450 	case e1000_82571:

   451 	case e1000_82572:

   452 	case e1000_82573:

   453 		hw->eeprom_semaphore_present = true;

   454 		/* fall through */

   455 	case e1000_82541:

   456 	case e1000_82547:

   457 	case e1000_82541_rev_2:

   458 	case e1000_82547_rev_2:

   459 		hw->asf_firmware_present = true;

   460 		break;

   461 	default:

   462 		break;

   463 	}

   464 

   465 	/* The 82543 chip does not count tx_carrier_errors properly in

   466 	 * FD mode

   467 	 */

   468 	if (hw->mac_type == e1000_82543)

   469 		hw->bad_tx_carr_stats_fd = true;

   470 

   471 	/* capable of receiving management packets to the host */

   472 	if (hw->mac_type >= e1000_82571)

   473 		hw->has_manc2h = true;

   474 

   475 	/* In rare occasions, ESB2 systems would end up started without

   476 	 * the RX unit being turned on.

   477 	 */

   478 	if (hw->mac_type == e1000_80003es2lan)

   479 		hw->rx_needs_kicking = true;

   480 

   481 	if (hw->mac_type > e1000_82544)

   482 		hw->has_smbus = true;

   483 

   484 	return E1000_SUCCESS;

   485 }

   486 

   487 /*****************************************************************************

   488  * Set media type and TBI compatibility.

   489  *

   490  * hw - Struct containing variables accessed by shared code

   491  * **************************************************************************/

   492 void e1000_set_media_type(struct e1000_hw *hw)

   493 {

   494     u32 status;

   495 

   496     DEBUGFUNC("e1000_set_media_type");

   497 

   498     if (hw->mac_type != e1000_82543) {

   499         /* tbi_compatibility is only valid on 82543 */

   500         hw->tbi_compatibility_en = false;

   501     }

   502 

   503     switch (hw->device_id) {

   504     case E1000_DEV_ID_82545GM_SERDES:

   505     case E1000_DEV_ID_82546GB_SERDES:

   506     case E1000_DEV_ID_82571EB_SERDES:

   507     case E1000_DEV_ID_82571EB_SERDES_DUAL:

   508     case E1000_DEV_ID_82571EB_SERDES_QUAD:

   509     case E1000_DEV_ID_82572EI_SERDES:

   510     case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   511         hw->media_type = e1000_media_type_internal_serdes;

   512         break;

   513     default:

   514         switch (hw->mac_type) {

   515         case e1000_82542_rev2_0:

   516         case e1000_82542_rev2_1:

   517             hw->media_type = e1000_media_type_fiber;

   518             break;

   519         case e1000_ich8lan:

   520         case e1000_82573:

   521             /* The STATUS_TBIMODE bit is reserved or reused for the this

   522              * device.

   523              */

   524             hw->media_type = e1000_media_type_copper;

   525             break;

   526         default:

   527             status = er32(STATUS);

   528             if (status & E1000_STATUS_TBIMODE) {

   529                 hw->media_type = e1000_media_type_fiber;

   530                 /* tbi_compatibility not valid on fiber */

   531                 hw->tbi_compatibility_en = false;

   532             } else {

   533                 hw->media_type = e1000_media_type_copper;

   534             }

   535             break;

   536         }

   537     }

   538 }

   539 

   540 /******************************************************************************

   541  * Reset the transmit and receive units; mask and clear all interrupts.

   542  *

   543  * hw - Struct containing variables accessed by shared code

   544  *****************************************************************************/

   545 s32 e1000_reset_hw(struct e1000_hw *hw)

   546 {

   547     u32 ctrl;

   548     u32 ctrl_ext;

   549     u32 icr;

   550     u32 manc;

   551     u32 led_ctrl;

   552     u32 timeout;

   553     u32 extcnf_ctrl;

   554     s32 ret_val;

   555 

   556     DEBUGFUNC("e1000_reset_hw");

   557 

   558     /* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   559     if (hw->mac_type == e1000_82542_rev2_0) {

   560         DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");

   561         e1000_pci_clear_mwi(hw);

   562     }

   563 

   564     if (hw->bus_type == e1000_bus_type_pci_express) {

   565         /* Prevent the PCI-E bus from sticking if there is no TLP connection

   566          * on the last TLP read/write transaction when MAC is reset.

   567          */

   568         if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {

   569             DEBUGOUT("PCI-E Master disable polling has failed.\n");

   570         }

   571     }

   572 

   573     /* Clear interrupt mask to stop board from generating interrupts */

   574     DEBUGOUT("Masking off all interrupts\n");

   575     ew32(IMC, 0xffffffff);

   576 

   577     /* Disable the Transmit and Receive units.  Then delay to allow

   578      * any pending transactions to complete before we hit the MAC with

   579      * the global reset.

   580      */

   581     ew32(RCTL, 0);

   582     ew32(TCTL, E1000_TCTL_PSP);

   583     E1000_WRITE_FLUSH();

   584 

   585     /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   586     hw->tbi_compatibility_on = false;

   587 

   588     /* Delay to allow any outstanding PCI transactions to complete before

   589      * resetting the device

   590      */

   591     msleep(10);

   592 

   593     ctrl = er32(CTRL);

   594 

   595     /* Must reset the PHY before resetting the MAC */

   596     if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   597         ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   598         msleep(5);

   599     }

   600 

   601     /* Must acquire the MDIO ownership before MAC reset.

   602      * Ownership defaults to firmware after a reset. */

   603     if (hw->mac_type == e1000_82573) {

   604         timeout = 10;

   605 

   606         extcnf_ctrl = er32(EXTCNF_CTRL);

   607         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   608 

   609         do {

   610             ew32(EXTCNF_CTRL, extcnf_ctrl);

   611             extcnf_ctrl = er32(EXTCNF_CTRL);

   612 

   613             if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

   614                 break;

   615             else

   616                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   617 

   618             msleep(2);

   619             timeout--;

   620         } while (timeout);

   621     }

   622 

   623     /* Workaround for ICH8 bit corruption issue in FIFO memory */

   624     if (hw->mac_type == e1000_ich8lan) {

   625         /* Set Tx and Rx buffer allocation to 8k apiece. */

   626         ew32(PBA, E1000_PBA_8K);

   627         /* Set Packet Buffer Size to 16k. */

   628         ew32(PBS, E1000_PBS_16K);

   629     }

   630 

   631     /* Issue a global reset to the MAC.  This will reset the chip's

   632      * transmit, receive, DMA, and link units.  It will not effect

   633      * the current PCI configuration.  The global reset bit is self-

   634      * clearing, and should clear within a microsecond.

   635      */

   636     DEBUGOUT("Issuing a global reset to MAC\n");

   637 

   638     switch (hw->mac_type) {

   639         case e1000_82544:

   640         case e1000_82540:

   641         case e1000_82545:

   642         case e1000_82546:

   643         case e1000_82541:

   644         case e1000_82541_rev_2:

   645             /* These controllers can't ack the 64-bit write when issuing the

   646              * reset, so use IO-mapping as a workaround to issue the reset */

   647             E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   648             break;

   649         case e1000_82545_rev_3:

   650         case e1000_82546_rev_3:

   651             /* Reset is performed on a shadow of the control register */

   652             ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   653             break;

   654         case e1000_ich8lan:

   655             if (!hw->phy_reset_disable &&

   656                 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {

   657                 /* e1000_ich8lan PHY HW reset requires MAC CORE reset

   658                  * at the same time to make sure the interface between

   659                  * MAC and the external PHY is reset.

   660                  */

   661                 ctrl |= E1000_CTRL_PHY_RST;

   662             }

   663 

   664             e1000_get_software_flag(hw);

   665             ew32(CTRL, (ctrl | E1000_CTRL_RST));

   666             msleep(5);

   667             break;

   668         default:

   669             ew32(CTRL, (ctrl | E1000_CTRL_RST));

   670             break;

   671     }

   672 

   673     /* After MAC reset, force reload of EEPROM to restore power-on settings to

   674      * device.  Later controllers reload the EEPROM automatically, so just wait

   675      * for reload to complete.

   676      */

   677     switch (hw->mac_type) {

   678         case e1000_82542_rev2_0:

   679         case e1000_82542_rev2_1:

   680         case e1000_82543:

   681         case e1000_82544:

   682             /* Wait for reset to complete */

   683             udelay(10);

   684             ctrl_ext = er32(CTRL_EXT);

   685             ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   686             ew32(CTRL_EXT, ctrl_ext);

   687             E1000_WRITE_FLUSH();

   688             /* Wait for EEPROM reload */

   689             msleep(2);

   690             break;

   691         case e1000_82541:

   692         case e1000_82541_rev_2:

   693         case e1000_82547:

   694         case e1000_82547_rev_2:

   695             /* Wait for EEPROM reload */

   696             msleep(20);

   697             break;

   698         case e1000_82573:

   699             if (!e1000_is_onboard_nvm_eeprom(hw)) {

   700                 udelay(10);

   701                 ctrl_ext = er32(CTRL_EXT);

   702                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   703                 ew32(CTRL_EXT, ctrl_ext);

   704                 E1000_WRITE_FLUSH();

   705             }

   706             /* fall through */

   707         default:

   708             /* Auto read done will delay 5ms or poll based on mac type */

   709             ret_val = e1000_get_auto_rd_done(hw);

   710             if (ret_val)

   711                 return ret_val;

   712             break;

   713     }

   714 

   715     /* Disable HW ARPs on ASF enabled adapters */

   716     if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {

   717         manc = er32(MANC);

   718         manc &= ~(E1000_MANC_ARP_EN);

   719         ew32(MANC, manc);

   720     }

   721 

   722     if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   723         e1000_phy_init_script(hw);

   724 

   725         /* Configure activity LED after PHY reset */

   726         led_ctrl = er32(LEDCTL);

   727         led_ctrl &= IGP_ACTIVITY_LED_MASK;

   728         led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   729         ew32(LEDCTL, led_ctrl);

   730     }

   731 

   732     /* Clear interrupt mask to stop board from generating interrupts */

   733     DEBUGOUT("Masking off all interrupts\n");

   734     ew32(IMC, 0xffffffff);

   735 

   736     /* Clear any pending interrupt events. */

   737     icr = er32(ICR);

   738 

   739     /* If MWI was previously enabled, reenable it. */

   740     if (hw->mac_type == e1000_82542_rev2_0) {

   741         if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   742             e1000_pci_set_mwi(hw);

   743     }

   744 

   745     if (hw->mac_type == e1000_ich8lan) {

   746         u32 kab = er32(KABGTXD);

   747         kab |= E1000_KABGTXD_BGSQLBIAS;

   748         ew32(KABGTXD, kab);

   749     }

   750 

   751     return E1000_SUCCESS;

   752 }

   753 

   754 /******************************************************************************

   755  *

   756  * Initialize a number of hardware-dependent bits

   757  *

   758  * hw: Struct containing variables accessed by shared code

   759  *

   760  * This function contains hardware limitation workarounds for PCI-E adapters

   761  *

   762  *****************************************************************************/

   763 static void e1000_initialize_hardware_bits(struct e1000_hw *hw)

   764 {

   765     if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {

   766         /* Settings common to all PCI-express silicon */

   767         u32 reg_ctrl, reg_ctrl_ext;

   768         u32 reg_tarc0, reg_tarc1;

   769         u32 reg_tctl;

   770         u32 reg_txdctl, reg_txdctl1;

   771 

   772         /* link autonegotiation/sync workarounds */

   773         reg_tarc0 = er32(TARC0);

   774         reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));

   775 

   776         /* Enable not-done TX descriptor counting */

   777         reg_txdctl = er32(TXDCTL);

   778         reg_txdctl |= E1000_TXDCTL_COUNT_DESC;

   779         ew32(TXDCTL, reg_txdctl);

   780         reg_txdctl1 = er32(TXDCTL1);

   781         reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;

   782         ew32(TXDCTL1, reg_txdctl1);

   783 

   784         switch (hw->mac_type) {

   785             case e1000_82571:

   786             case e1000_82572:

   787                 /* Clear PHY TX compatible mode bits */

   788                 reg_tarc1 = er32(TARC1);

   789                 reg_tarc1 &= ~((1 << 30)|(1 << 29));

   790 

   791                 /* link autonegotiation/sync workarounds */

   792                 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));

   793 

   794                 /* TX ring control fixes */

   795                 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));

   796 

   797                 /* Multiple read bit is reversed polarity */

   798                 reg_tctl = er32(TCTL);

   799                 if (reg_tctl & E1000_TCTL_MULR)

   800                     reg_tarc1 &= ~(1 << 28);

   801                 else

   802                     reg_tarc1 |= (1 << 28);

   803 

   804                 ew32(TARC1, reg_tarc1);

   805                 break;

   806             case e1000_82573:

   807                 reg_ctrl_ext = er32(CTRL_EXT);

   808                 reg_ctrl_ext &= ~(1 << 23);

   809                 reg_ctrl_ext |= (1 << 22);

   810 

   811                 /* TX byte count fix */

   812                 reg_ctrl = er32(CTRL);

   813                 reg_ctrl &= ~(1 << 29);

   814 

   815                 ew32(CTRL_EXT, reg_ctrl_ext);

   816                 ew32(CTRL, reg_ctrl);

   817                 break;

   818             case e1000_80003es2lan:

   819                 /* improve small packet performace for fiber/serdes */

   820                 if ((hw->media_type == e1000_media_type_fiber) ||

   821                     (hw->media_type == e1000_media_type_internal_serdes)) {

   822                     reg_tarc0 &= ~(1 << 20);

   823                 }

   824 

   825                 /* Multiple read bit is reversed polarity */

   826                 reg_tctl = er32(TCTL);

   827                 reg_tarc1 = er32(TARC1);

   828                 if (reg_tctl & E1000_TCTL_MULR)

   829                     reg_tarc1 &= ~(1 << 28);

   830                 else

   831                     reg_tarc1 |= (1 << 28);

   832 

   833                 ew32(TARC1, reg_tarc1);

   834                 break;

   835             case e1000_ich8lan:

   836                 /* Reduce concurrent DMA requests to 3 from 4 */

   837                 if ((hw->revision_id < 3) ||

   838                     ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&

   839                      (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))

   840                     reg_tarc0 |= ((1 << 29)|(1 << 28));

   841 

   842                 reg_ctrl_ext = er32(CTRL_EXT);

   843                 reg_ctrl_ext |= (1 << 22);

   844                 ew32(CTRL_EXT, reg_ctrl_ext);

   845 

   846                 /* workaround TX hang with TSO=on */

   847                 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));

   848 

   849                 /* Multiple read bit is reversed polarity */

   850                 reg_tctl = er32(TCTL);

   851                 reg_tarc1 = er32(TARC1);

   852                 if (reg_tctl & E1000_TCTL_MULR)

   853                     reg_tarc1 &= ~(1 << 28);

   854                 else

   855                     reg_tarc1 |= (1 << 28);

   856 

   857                 /* workaround TX hang with TSO=on */

   858                 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));

   859 

   860                 ew32(TARC1, reg_tarc1);

   861                 break;

   862             default:

   863                 break;

   864         }

   865 

   866         ew32(TARC0, reg_tarc0);

   867     }

   868 }

   869 

   870 /******************************************************************************

   871  * Performs basic configuration of the adapter.

   872  *

   873  * hw - Struct containing variables accessed by shared code

   874  *

   875  * Assumes that the controller has previously been reset and is in a

   876  * post-reset uninitialized state. Initializes the receive address registers,

   877  * multicast table, and VLAN filter table. Calls routines to setup link

   878  * configuration and flow control settings. Clears all on-chip counters. Leaves

   879  * the transmit and receive units disabled and uninitialized.

   880  *****************************************************************************/

   881 s32 e1000_init_hw(struct e1000_hw *hw)

   882 {

   883     u32 ctrl;

   884     u32 i;

   885     s32 ret_val;

   886     u32 mta_size;

   887     u32 reg_data;

   888     u32 ctrl_ext;

   889 

   890     DEBUGFUNC("e1000_init_hw");

   891 

   892     /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */

   893     if ((hw->mac_type == e1000_ich8lan) &&

   894         ((hw->revision_id < 3) ||

   895          ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&

   896           (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {

   897             reg_data = er32(STATUS);

   898             reg_data &= ~0x80000000;

   899             ew32(STATUS, reg_data);

   900     }

   901 

   902     /* Initialize Identification LED */

   903     ret_val = e1000_id_led_init(hw);

   904     if (ret_val) {

   905         DEBUGOUT("Error Initializing Identification LED\n");

   906         return ret_val;

   907     }

   908 

   909     /* Set the media type and TBI compatibility */

   910     e1000_set_media_type(hw);

   911 

   912     /* Must be called after e1000_set_media_type because media_type is used */

   913     e1000_initialize_hardware_bits(hw);

   914 

   915     /* Disabling VLAN filtering. */

   916     DEBUGOUT("Initializing the IEEE VLAN\n");

   917     /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */

   918     if (hw->mac_type != e1000_ich8lan) {

   919         if (hw->mac_type < e1000_82545_rev_3)

   920             ew32(VET, 0);

   921         e1000_clear_vfta(hw);

   922     }

   923 

   924     /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */

   925     if (hw->mac_type == e1000_82542_rev2_0) {

   926         DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");

   927         e1000_pci_clear_mwi(hw);

   928         ew32(RCTL, E1000_RCTL_RST);

   929         E1000_WRITE_FLUSH();

   930         msleep(5);

   931     }

   932 

   933     /* Setup the receive address. This involves initializing all of the Receive

   934      * Address Registers (RARs 0 - 15).

   935      */

   936     e1000_init_rx_addrs(hw);

   937 

   938     /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */

   939     if (hw->mac_type == e1000_82542_rev2_0) {

   940         ew32(RCTL, 0);

   941         E1000_WRITE_FLUSH();

   942         msleep(1);

   943         if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   944             e1000_pci_set_mwi(hw);

   945     }

   946 

   947     /* Zero out the Multicast HASH table */

   948     DEBUGOUT("Zeroing the MTA\n");

   949     mta_size = E1000_MC_TBL_SIZE;

   950     if (hw->mac_type == e1000_ich8lan)

   951         mta_size = E1000_MC_TBL_SIZE_ICH8LAN;

   952     for (i = 0; i < mta_size; i++) {

   953         E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);

   954         /* use write flush to prevent Memory Write Block (MWB) from

   955          * occuring when accessing our register space */

   956         E1000_WRITE_FLUSH();

   957     }

   958 

   959     /* Set the PCI priority bit correctly in the CTRL register.  This

   960      * determines if the adapter gives priority to receives, or if it

   961      * gives equal priority to transmits and receives.  Valid only on

   962      * 82542 and 82543 silicon.

   963      */

   964     if (hw->dma_fairness && hw->mac_type <= e1000_82543) {

   965         ctrl = er32(CTRL);

   966         ew32(CTRL, ctrl | E1000_CTRL_PRIOR);

   967     }

   968 

   969     switch (hw->mac_type) {

   970     case e1000_82545_rev_3:

   971     case e1000_82546_rev_3:

   972         break;

   973     default:

   974         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */

   975 	if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048)

   976 		e1000_pcix_set_mmrbc(hw, 2048);

   977 	break;

   978     }

   979 

   980     /* More time needed for PHY to initialize */

   981     if (hw->mac_type == e1000_ich8lan)

   982         msleep(15);

   983 

   984     /* Call a subroutine to configure the link and setup flow control. */

   985     ret_val = e1000_setup_link(hw);

   986 

   987     /* Set the transmit descriptor write-back policy */

   988     if (hw->mac_type > e1000_82544) {

   989         ctrl = er32(TXDCTL);

   990         ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;

   991         ew32(TXDCTL, ctrl);

   992     }

   993 

   994     if (hw->mac_type == e1000_82573) {

   995         e1000_enable_tx_pkt_filtering(hw);

   996     }

   997 

   998     switch (hw->mac_type) {

   999     default:

  1000         break;

  1001     case e1000_80003es2lan:

  1002         /* Enable retransmit on late collisions */

  1003         reg_data = er32(TCTL);

  1004         reg_data |= E1000_TCTL_RTLC;

  1005         ew32(TCTL, reg_data);

  1006 

  1007         /* Configure Gigabit Carry Extend Padding */

  1008         reg_data = er32(TCTL_EXT);

  1009         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;

  1010         reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;

  1011         ew32(TCTL_EXT, reg_data);

  1012 

  1013         /* Configure Transmit Inter-Packet Gap */

  1014         reg_data = er32(TIPG);

  1015         reg_data &= ~E1000_TIPG_IPGT_MASK;

  1016         reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;

  1017         ew32(TIPG, reg_data);

  1018 

  1019         reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);

  1020         reg_data &= ~0x00100000;

  1021         E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);

  1022         /* Fall through */

  1023     case e1000_82571:

  1024     case e1000_82572:

  1025     case e1000_ich8lan:

  1026         ctrl = er32(TXDCTL1);

  1027         ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;

  1028         ew32(TXDCTL1, ctrl);

  1029         break;

  1030     }

  1031 

  1032 

  1033     if (hw->mac_type == e1000_82573) {

  1034         u32 gcr = er32(GCR);

  1035         gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;

  1036         ew32(GCR, gcr);

  1037     }

  1038 

  1039     /* Clear all of the statistics registers (clear on read).  It is

  1040      * important that we do this after we have tried to establish link

  1041      * because the symbol error count will increment wildly if there

  1042      * is no link.

  1043      */

  1044     e1000_clear_hw_cntrs(hw);

  1045 

  1046     /* ICH8 No-snoop bits are opposite polarity.

  1047      * Set to snoop by default after reset. */

  1048     if (hw->mac_type == e1000_ich8lan)

  1049         e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);

  1050 

  1051     if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||

  1052         hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {

  1053         ctrl_ext = er32(CTRL_EXT);

  1054         /* Relaxed ordering must be disabled to avoid a parity

  1055          * error crash in a PCI slot. */

  1056         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;

  1057         ew32(CTRL_EXT, ctrl_ext);

  1058     }

  1059 

  1060     return ret_val;

  1061 }

  1062 

  1063 /******************************************************************************

  1064  * Adjust SERDES output amplitude based on EEPROM setting.

  1065  *

  1066  * hw - Struct containing variables accessed by shared code.

  1067  *****************************************************************************/

  1068 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)

  1069 {

  1070     u16 eeprom_data;

  1071     s32  ret_val;

  1072 

  1073     DEBUGFUNC("e1000_adjust_serdes_amplitude");

  1074 

  1075     if (hw->media_type != e1000_media_type_internal_serdes)

  1076         return E1000_SUCCESS;

  1077 

  1078     switch (hw->mac_type) {

  1079     case e1000_82545_rev_3:

  1080     case e1000_82546_rev_3:

  1081         break;

  1082     default:

  1083         return E1000_SUCCESS;

  1084     }

  1085 

  1086     ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);

  1087     if (ret_val) {

  1088         return ret_val;

  1089     }

  1090 

  1091     if (eeprom_data != EEPROM_RESERVED_WORD) {

  1092         /* Adjust SERDES output amplitude only. */

  1093         eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;

  1094         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);

  1095         if (ret_val)

  1096             return ret_val;

  1097     }

  1098 

  1099     return E1000_SUCCESS;

  1100 }

  1101 

  1102 /******************************************************************************

  1103  * Configures flow control and link settings.

  1104  *

  1105  * hw - Struct containing variables accessed by shared code

  1106  *

  1107  * Determines which flow control settings to use. Calls the apropriate media-

  1108  * specific link configuration function. Configures the flow control settings.

  1109  * Assuming the adapter has a valid link partner, a valid link should be

  1110  * established. Assumes the hardware has previously been reset and the

  1111  * transmitter and receiver are not enabled.

  1112  *****************************************************************************/

  1113 s32 e1000_setup_link(struct e1000_hw *hw)

  1114 {

  1115     u32 ctrl_ext;

  1116     s32 ret_val;

  1117     u16 eeprom_data;

  1118 

  1119     DEBUGFUNC("e1000_setup_link");

  1120 

  1121     /* In the case of the phy reset being blocked, we already have a link.

  1122      * We do not have to set it up again. */

  1123     if (e1000_check_phy_reset_block(hw))

  1124         return E1000_SUCCESS;

  1125 

  1126     /* Read and store word 0x0F of the EEPROM. This word contains bits

  1127      * that determine the hardware's default PAUSE (flow control) mode,

  1128      * a bit that determines whether the HW defaults to enabling or

  1129      * disabling auto-negotiation, and the direction of the

  1130      * SW defined pins. If there is no SW over-ride of the flow

  1131      * control setting, then the variable hw->fc will

  1132      * be initialized based on a value in the EEPROM.

  1133      */

  1134     if (hw->fc == E1000_FC_DEFAULT) {

  1135         switch (hw->mac_type) {

  1136         case e1000_ich8lan: