1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2006 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /* e1000_hw.c

    30  * Shared functions for accessing and configuring the MAC

    31  */

    32 

    33 

    34 #include "e1000_hw.h"

    35 

    36 static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);

    37 static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);

    38 static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);

    39 static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);

    40 static s32 e1000_get_software_semaphore(struct e1000_hw *hw);

    41 static void e1000_release_software_semaphore(struct e1000_hw *hw);

    42 

    43 static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);

    44 static s32 e1000_check_downshift(struct e1000_hw *hw);

    45 static s32 e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);

    46 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    47 static void e1000_clear_vfta(struct e1000_hw *hw);

    48 static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);

    49 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    50 						  bool link_up);

    51 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    52 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    53 static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);

    54 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    55 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, u16 *max_length);

    56 static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);

    57 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    58 static s32 e1000_get_software_flag(struct e1000_hw *hw);

    59 static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);

    60 static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);

    61 static s32 e1000_id_led_init(struct e1000_hw *hw);

    62 static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, u32 cnf_base_addr, u32 cnf_size);

    63 static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);

    64 static void e1000_init_rx_addrs(struct e1000_hw *hw);

    65 static void e1000_initialize_hardware_bits(struct e1000_hw *hw);

    66 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);

    67 static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);

    68 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);

    69 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, u16 offset, u8 *sum);

    70 static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);

    71 static s32 e1000_mng_write_commit(struct e1000_hw *hw);

    72 static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);

    73 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);

    74 static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);

    75 static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);

    76 static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);

    77 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);

    78 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);

    79 static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);

    80 static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);

    81 static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);

    82 static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);

    83 static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 *data);

    84 static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 data);

    85 static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);

    86 static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);

    87 static void e1000_release_software_flag(struct e1000_hw *hw);

    88 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    89 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);

    90 static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);

    91 static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);

    92 static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    93 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    94 static s32 e1000_set_phy_type(struct e1000_hw *hw);

    95 static void e1000_phy_init_script(struct e1000_hw *hw);

    96 static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    97 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    98 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    99 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

   100 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

   101 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

   102 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

   103 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,

   104                                      u16 count);

   105 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

   106 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

   107 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

   108                                       u16 words, u16 *data);

   109 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw,

   110                                             u16 offset, u16 words,

   111                                             u16 *data);

   112 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

   113 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

   114 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

   115 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data,

   116                                     u16 count);

   117 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

   118                                       u16 phy_data);

   119 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,

   120                                      u16 *phy_data);

   121 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

   122 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

   123 static void e1000_release_eeprom(struct e1000_hw *hw);

   124 static void e1000_standby_eeprom(struct e1000_hw *hw);

   125 static s32 e1000_set_vco_speed(struct e1000_hw *hw);

   126 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

   127 static s32 e1000_set_phy_mode(struct e1000_hw *hw);

   128 static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);

   129 static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);

   130 static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,

   131                                                u16 duplex);

   132 static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);

   133 

   134 /* IGP cable length table */

   135 static const

   136 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =

   137     { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

   138       5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

   139       25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

   140       40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   141       60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   142       90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   143       100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   144       110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};

   145 

   146 static const

   147 u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =

   148     { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,

   149       0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,

   150       6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,

   151       21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,

   152       40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,

   153       60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,

   154       83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,

   155       104, 109, 114, 118, 121, 124};

   156 

   157 /******************************************************************************

   158  * Set the phy type member in the hw struct.

   159  *

   160  * hw - Struct containing variables accessed by shared code

   161  *****************************************************************************/

   162 static s32

   163 e1000_set_phy_type(struct e1000_hw *hw)

   164 {

   165     DEBUGFUNC("e1000_set_phy_type");

   166 

   167     if (hw->mac_type == e1000_undefined)

   168         return -E1000_ERR_PHY_TYPE;

   169 

   170     switch (hw->phy_id) {

   171     case M88E1000_E_PHY_ID:

   172     case M88E1000_I_PHY_ID:

   173     case M88E1011_I_PHY_ID:

   174     case M88E1111_I_PHY_ID:

   175         hw->phy_type = e1000_phy_m88;

   176         break;

   177     case IGP01E1000_I_PHY_ID:

   178         if (hw->mac_type == e1000_82541 ||

   179             hw->mac_type == e1000_82541_rev_2 ||

   180             hw->mac_type == e1000_82547 ||

   181             hw->mac_type == e1000_82547_rev_2) {

   182             hw->phy_type = e1000_phy_igp;

   183             break;

   184         }

   185     case IGP03E1000_E_PHY_ID:

   186         hw->phy_type = e1000_phy_igp_3;

   187         break;

   188     case IFE_E_PHY_ID:

   189     case IFE_PLUS_E_PHY_ID:

   190     case IFE_C_E_PHY_ID:

   191         hw->phy_type = e1000_phy_ife;

   192         break;

   193     case GG82563_E_PHY_ID:

   194         if (hw->mac_type == e1000_80003es2lan) {

   195             hw->phy_type = e1000_phy_gg82563;

   196             break;

   197         }

   198         /* Fall Through */

   199     default:

   200         /* Should never have loaded on this device */

   201         hw->phy_type = e1000_phy_undefined;

   202         return -E1000_ERR_PHY_TYPE;

   203     }

   204 

   205     return E1000_SUCCESS;

   206 }

   207 

   208 /******************************************************************************

   209  * IGP phy init script - initializes the GbE PHY

   210  *

   211  * hw - Struct containing variables accessed by shared code

   212  *****************************************************************************/

   213 static void

   214 e1000_phy_init_script(struct e1000_hw *hw)

   215 {

   216     u32 ret_val;

   217     u16 phy_saved_data;

   218 

   219     DEBUGFUNC("e1000_phy_init_script");

   220 

   221     if (hw->phy_init_script) {

   222         msleep(20);

   223 

   224         /* Save off the current value of register 0x2F5B to be restored at

   225          * the end of this routine. */

   226         ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   227 

   228         /* Disabled the PHY transmitter */

   229         e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   230 

   231         msleep(20);

   232 

   233         e1000_write_phy_reg(hw,0x0000,0x0140);

   234 

   235         msleep(5);

   236 

   237         switch (hw->mac_type) {

   238         case e1000_82541:

   239         case e1000_82547:

   240             e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   241 

   242             e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   243 

   244             e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   245 

   246             e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   247 

   248             e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   249 

   250             e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   251 

   252             e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   253 

   254             e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   255 

   256             e1000_write_phy_reg(hw, 0x2010, 0x0008);

   257             break;

   258 

   259         case e1000_82541_rev_2:

   260         case e1000_82547_rev_2:

   261             e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   262             break;

   263         default:

   264             break;

   265         }

   266 

   267         e1000_write_phy_reg(hw, 0x0000, 0x3300);

   268 

   269         msleep(20);

   270 

   271         /* Now enable the transmitter */

   272         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   273 

   274         if (hw->mac_type == e1000_82547) {

   275             u16 fused, fine, coarse;

   276 

   277             /* Move to analog registers page */

   278             e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);

   279 

   280             if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   281                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);

   282 

   283                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   284                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   285 

   286                 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   287                     coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;

   288                     fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   289                 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   290                     fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   291 

   292                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   293                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   294                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   295 

   296                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);

   297                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,

   298                                     IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   299             }

   300         }

   301     }

   302 }

   303 

   304 /******************************************************************************

   305  * Set the mac type member in the hw struct.

   306  *

   307  * hw - Struct containing variables accessed by shared code

   308  *****************************************************************************/

   309 s32

   310 e1000_set_mac_type(struct e1000_hw *hw)

   311 {

   312 	DEBUGFUNC("e1000_set_mac_type");

   313 

   314 	switch (hw->device_id) {

   315 	case E1000_DEV_ID_82542:

   316 		switch (hw->revision_id) {

   317 		case E1000_82542_2_0_REV_ID:

   318 			hw->mac_type = e1000_82542_rev2_0;

   319 			break;

   320 		case E1000_82542_2_1_REV_ID:

   321 			hw->mac_type = e1000_82542_rev2_1;

   322 			break;

   323 		default:

   324 			/* Invalid 82542 revision ID */

   325 			return -E1000_ERR_MAC_TYPE;

   326 		}

   327 		break;

   328 	case E1000_DEV_ID_82543GC_FIBER:

   329 	case E1000_DEV_ID_82543GC_COPPER:

   330 		hw->mac_type = e1000_82543;

   331 		break;

   332 	case E1000_DEV_ID_82544EI_COPPER:

   333 	case E1000_DEV_ID_82544EI_FIBER:

   334 	case E1000_DEV_ID_82544GC_COPPER:

   335 	case E1000_DEV_ID_82544GC_LOM:

   336 		hw->mac_type = e1000_82544;

   337 		break;

   338 	case E1000_DEV_ID_82540EM:

   339 	case E1000_DEV_ID_82540EM_LOM:

   340 	case E1000_DEV_ID_82540EP:

   341 	case E1000_DEV_ID_82540EP_LOM:

   342 	case E1000_DEV_ID_82540EP_LP:

   343 		hw->mac_type = e1000_82540;

   344 		break;

   345 	case E1000_DEV_ID_82545EM_COPPER:

   346 	case E1000_DEV_ID_82545EM_FIBER:

   347 		hw->mac_type = e1000_82545;

   348 		break;

   349 	case E1000_DEV_ID_82545GM_COPPER:

   350 	case E1000_DEV_ID_82545GM_FIBER:

   351 	case E1000_DEV_ID_82545GM_SERDES:

   352 		hw->mac_type = e1000_82545_rev_3;

   353 		break;

   354 	case E1000_DEV_ID_82546EB_COPPER:

   355 	case E1000_DEV_ID_82546EB_FIBER:

   356 	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   357 		hw->mac_type = e1000_82546;

   358 		break;

   359 	case E1000_DEV_ID_82546GB_COPPER:

   360 	case E1000_DEV_ID_82546GB_FIBER:

   361 	case E1000_DEV_ID_82546GB_SERDES:

   362 	case E1000_DEV_ID_82546GB_PCIE:

   363 	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   364 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   365 		hw->mac_type = e1000_82546_rev_3;

   366 		break;

   367 	case E1000_DEV_ID_82541EI:

   368 	case E1000_DEV_ID_82541EI_MOBILE:

   369 	case E1000_DEV_ID_82541ER_LOM:

   370 		hw->mac_type = e1000_82541;

   371 		break;

   372 	case E1000_DEV_ID_82541ER:

   373 	case E1000_DEV_ID_82541GI:

   374 	case E1000_DEV_ID_82541GI_LF:

   375 	case E1000_DEV_ID_82541GI_MOBILE:

   376 		hw->mac_type = e1000_82541_rev_2;

   377 		break;

   378 	case E1000_DEV_ID_82547EI:

   379 	case E1000_DEV_ID_82547EI_MOBILE:

   380 		hw->mac_type = e1000_82547;

   381 		break;

   382 	case E1000_DEV_ID_82547GI:

   383 		hw->mac_type = e1000_82547_rev_2;

   384 		break;

   385 	case E1000_DEV_ID_82571EB_COPPER:

   386 	case E1000_DEV_ID_82571EB_FIBER:

   387 	case E1000_DEV_ID_82571EB_SERDES:

   388 	case E1000_DEV_ID_82571EB_SERDES_DUAL:

   389 	case E1000_DEV_ID_82571EB_SERDES_QUAD:

   390 	case E1000_DEV_ID_82571EB_QUAD_COPPER:

   391 	case E1000_DEV_ID_82571PT_QUAD_COPPER:

   392 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   393 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:

   394 		hw->mac_type = e1000_82571;

   395 		break;

   396 	case E1000_DEV_ID_82572EI_COPPER:

   397 	case E1000_DEV_ID_82572EI_FIBER:

   398 	case E1000_DEV_ID_82572EI_SERDES:

   399 	case E1000_DEV_ID_82572EI:

   400 		hw->mac_type = e1000_82572;

   401 		break;

   402 	case E1000_DEV_ID_82573E:

   403 	case E1000_DEV_ID_82573E_IAMT:

   404 	case E1000_DEV_ID_82573L:

   405 		hw->mac_type = e1000_82573;

   406 		break;

   407 	case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:

   408 	case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:

   409 	case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:

   410 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   411 		hw->mac_type = e1000_80003es2lan;

   412 		break;

   413 	case E1000_DEV_ID_ICH8_IGP_M_AMT:

   414 	case E1000_DEV_ID_ICH8_IGP_AMT:

   415 	case E1000_DEV_ID_ICH8_IGP_C:

   416 	case E1000_DEV_ID_ICH8_IFE:

   417 	case E1000_DEV_ID_ICH8_IFE_GT:

   418 	case E1000_DEV_ID_ICH8_IFE_G:

   419 	case E1000_DEV_ID_ICH8_IGP_M:

   420 		hw->mac_type = e1000_ich8lan;

   421 		break;

   422 	default:

   423 		/* Should never have loaded on this device */

   424 		return -E1000_ERR_MAC_TYPE;

   425 	}

   426 

   427 	switch (hw->mac_type) {

   428 	case e1000_ich8lan:

   429 		hw->swfwhw_semaphore_present = true;

   430 		hw->asf_firmware_present = true;

   431 		break;

   432 	case e1000_80003es2lan:

   433 		hw->swfw_sync_present = true;

   434 		/* fall through */

   435 	case e1000_82571:

   436 	case e1000_82572:

   437 	case e1000_82573:

   438 		hw->eeprom_semaphore_present = true;

   439 		/* fall through */

   440 	case e1000_82541:

   441 	case e1000_82547:

   442 	case e1000_82541_rev_2:

   443 	case e1000_82547_rev_2:

   444 		hw->asf_firmware_present = true;

   445 		break;

   446 	default:

   447 		break;

   448 	}

   449 

   450 	/* The 82543 chip does not count tx_carrier_errors properly in

   451 	 * FD mode

   452 	 */

   453 	if (hw->mac_type == e1000_82543)

   454 		hw->bad_tx_carr_stats_fd = true;

   455 

   456 	/* capable of receiving management packets to the host */

   457 	if (hw->mac_type >= e1000_82571)

   458 		hw->has_manc2h = true;

   459 

   460 	/* In rare occasions, ESB2 systems would end up started without

   461 	 * the RX unit being turned on.

   462 	 */

   463 	if (hw->mac_type == e1000_80003es2lan)

   464 		hw->rx_needs_kicking = true;

   465 

   466 	if (hw->mac_type > e1000_82544)

   467 		hw->has_smbus = true;

   468 

   469 	return E1000_SUCCESS;

   470 }

   471 

   472 /*****************************************************************************

   473  * Set media type and TBI compatibility.

   474  *

   475  * hw - Struct containing variables accessed by shared code

   476  * **************************************************************************/

   477 void

   478 e1000_set_media_type(struct e1000_hw *hw)

   479 {

   480     u32 status;

   481 

   482     DEBUGFUNC("e1000_set_media_type");

   483 

   484     if (hw->mac_type != e1000_82543) {

   485         /* tbi_compatibility is only valid on 82543 */

   486         hw->tbi_compatibility_en = false;

   487     }

   488 

   489     switch (hw->device_id) {

   490     case E1000_DEV_ID_82545GM_SERDES:

   491     case E1000_DEV_ID_82546GB_SERDES:

   492     case E1000_DEV_ID_82571EB_SERDES:

   493     case E1000_DEV_ID_82571EB_SERDES_DUAL:

   494     case E1000_DEV_ID_82571EB_SERDES_QUAD:

   495     case E1000_DEV_ID_82572EI_SERDES:

   496     case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   497         hw->media_type = e1000_media_type_internal_serdes;

   498         break;

   499     default:

   500         switch (hw->mac_type) {

   501         case e1000_82542_rev2_0:

   502         case e1000_82542_rev2_1:

   503             hw->media_type = e1000_media_type_fiber;

   504             break;

   505         case e1000_ich8lan:

   506         case e1000_82573:

   507             /* The STATUS_TBIMODE bit is reserved or reused for the this

   508              * device.

   509              */

   510             hw->media_type = e1000_media_type_copper;

   511             break;

   512         default:

   513             status = E1000_READ_REG(hw, STATUS);

   514             if (status & E1000_STATUS_TBIMODE) {

   515                 hw->media_type = e1000_media_type_fiber;

   516                 /* tbi_compatibility not valid on fiber */

   517                 hw->tbi_compatibility_en = false;

   518             } else {

   519                 hw->media_type = e1000_media_type_copper;

   520             }

   521             break;

   522         }

   523     }

   524 }

   525 

   526 /******************************************************************************

   527  * Reset the transmit and receive units; mask and clear all interrupts.

   528  *

   529  * hw - Struct containing variables accessed by shared code

   530  *****************************************************************************/

   531 s32

   532 e1000_reset_hw(struct e1000_hw *hw)

   533 {

   534     u32 ctrl;

   535     u32 ctrl_ext;

   536     u32 icr;

   537     u32 manc;

   538     u32 led_ctrl;

   539     u32 timeout;

   540     u32 extcnf_ctrl;

   541     s32 ret_val;

   542 

   543     DEBUGFUNC("e1000_reset_hw");

   544 

   545     /* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   546     if (hw->mac_type == e1000_82542_rev2_0) {

   547         DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");

   548         e1000_pci_clear_mwi(hw);

   549     }

   550 

   551     if (hw->bus_type == e1000_bus_type_pci_express) {

   552         /* Prevent the PCI-E bus from sticking if there is no TLP connection

   553          * on the last TLP read/write transaction when MAC is reset.

   554          */

   555         if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {

   556             DEBUGOUT("PCI-E Master disable polling has failed.\n");

   557         }

   558     }

   559 

   560     /* Clear interrupt mask to stop board from generating interrupts */

   561     DEBUGOUT("Masking off all interrupts\n");

   562     E1000_WRITE_REG(hw, IMC, 0xffffffff);

   563 

   564     /* Disable the Transmit and Receive units.  Then delay to allow

   565      * any pending transactions to complete before we hit the MAC with

   566      * the global reset.

   567      */

   568     E1000_WRITE_REG(hw, RCTL, 0);

   569     E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);

   570     E1000_WRITE_FLUSH(hw);

   571 

   572     /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   573     hw->tbi_compatibility_on = false;

   574 

   575     /* Delay to allow any outstanding PCI transactions to complete before

   576      * resetting the device

   577      */

   578     msleep(10);

   579 

   580     ctrl = E1000_READ_REG(hw, CTRL);

   581 

   582     /* Must reset the PHY before resetting the MAC */

   583     if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   584         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));

   585         msleep(5);

   586     }

   587 

   588     /* Must acquire the MDIO ownership before MAC reset.

   589      * Ownership defaults to firmware after a reset. */

   590     if (hw->mac_type == e1000_82573) {

   591         timeout = 10;

   592 

   593         extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);

   594         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   595 

   596         do {

   597             E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);

   598             extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);

   599 

   600             if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

   601                 break;

   602             else

   603                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   604 

   605             msleep(2);

   606             timeout--;

   607         } while (timeout);

   608     }

   609 

   610     /* Workaround for ICH8 bit corruption issue in FIFO memory */

   611     if (hw->mac_type == e1000_ich8lan) {

   612         /* Set Tx and Rx buffer allocation to 8k apiece. */

   613         E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);

   614         /* Set Packet Buffer Size to 16k. */

   615         E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);

   616     }

   617 

   618     /* Issue a global reset to the MAC.  This will reset the chip's

   619      * transmit, receive, DMA, and link units.  It will not effect

   620      * the current PCI configuration.  The global reset bit is self-

   621      * clearing, and should clear within a microsecond.

   622      */

   623     DEBUGOUT("Issuing a global reset to MAC\n");

   624 

   625     switch (hw->mac_type) {

   626         case e1000_82544:

   627         case e1000_82540:

   628         case e1000_82545:

   629         case e1000_82546:

   630         case e1000_82541:

   631         case e1000_82541_rev_2:

   632             /* These controllers can't ack the 64-bit write when issuing the

   633              * reset, so use IO-mapping as a workaround to issue the reset */

   634             E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   635             break;

   636         case e1000_82545_rev_3:

   637         case e1000_82546_rev_3:

   638             /* Reset is performed on a shadow of the control register */

   639             E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));

   640             break;

   641         case e1000_ich8lan:

   642             if (!hw->phy_reset_disable &&

   643                 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {

   644                 /* e1000_ich8lan PHY HW reset requires MAC CORE reset

   645                  * at the same time to make sure the interface between

   646                  * MAC and the external PHY is reset.

   647                  */

   648                 ctrl |= E1000_CTRL_PHY_RST;

   649             }

   650 

   651             e1000_get_software_flag(hw);

   652             E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));

   653             msleep(5);

   654             break;

   655         default:

   656             E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));

   657             break;

   658     }

   659 

   660     /* After MAC reset, force reload of EEPROM to restore power-on settings to

   661      * device.  Later controllers reload the EEPROM automatically, so just wait

   662      * for reload to complete.

   663      */

   664     switch (hw->mac_type) {

   665         case e1000_82542_rev2_0:

   666         case e1000_82542_rev2_1:

   667         case e1000_82543:

   668         case e1000_82544:

   669             /* Wait for reset to complete */

   670             udelay(10);

   671             ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   672             ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   673             E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

   674             E1000_WRITE_FLUSH(hw);

   675             /* Wait for EEPROM reload */

   676             msleep(2);

   677             break;

   678         case e1000_82541:

   679         case e1000_82541_rev_2:

   680         case e1000_82547:

   681         case e1000_82547_rev_2:

   682             /* Wait for EEPROM reload */

   683             msleep(20);

   684             break;

   685         case e1000_82573:

   686             if (!e1000_is_onboard_nvm_eeprom(hw)) {

   687                 udelay(10);

   688                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   689                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   690                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

   691                 E1000_WRITE_FLUSH(hw);

   692             }

   693             /* fall through */

   694         default:

   695             /* Auto read done will delay 5ms or poll based on mac type */

   696             ret_val = e1000_get_auto_rd_done(hw);

   697             if (ret_val)

   698                 return ret_val;

   699             break;

   700     }

   701 

   702     /* Disable HW ARPs on ASF enabled adapters */

   703     if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {

   704         manc = E1000_READ_REG(hw, MANC);

   705         manc &= ~(E1000_MANC_ARP_EN);

   706         E1000_WRITE_REG(hw, MANC, manc);

   707     }

   708 

   709     if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   710         e1000_phy_init_script(hw);

   711 

   712         /* Configure activity LED after PHY reset */

   713         led_ctrl = E1000_READ_REG(hw, LEDCTL);

   714         led_ctrl &= IGP_ACTIVITY_LED_MASK;

   715         led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   716         E1000_WRITE_REG(hw, LEDCTL, led_ctrl);

   717     }

   718 

   719     /* Clear interrupt mask to stop board from generating interrupts */

   720     DEBUGOUT("Masking off all interrupts\n");

   721     E1000_WRITE_REG(hw, IMC, 0xffffffff);

   722 

   723     /* Clear any pending interrupt events. */

   724     icr = E1000_READ_REG(hw, ICR);

   725 

   726     /* If MWI was previously enabled, reenable it. */

   727     if (hw->mac_type == e1000_82542_rev2_0) {

   728         if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   729             e1000_pci_set_mwi(hw);

   730     }

   731 

   732     if (hw->mac_type == e1000_ich8lan) {

   733         u32 kab = E1000_READ_REG(hw, KABGTXD);

   734         kab |= E1000_KABGTXD_BGSQLBIAS;

   735         E1000_WRITE_REG(hw, KABGTXD, kab);

   736     }

   737 

   738     return E1000_SUCCESS;

   739 }

   740 

   741 /******************************************************************************

   742  *

   743  * Initialize a number of hardware-dependent bits

   744  *

   745  * hw: Struct containing variables accessed by shared code

   746  *

   747  * This function contains hardware limitation workarounds for PCI-E adapters

   748  *

   749  *****************************************************************************/

   750 static void

   751 e1000_initialize_hardware_bits(struct e1000_hw *hw)

   752 {

   753     if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {

   754         /* Settings common to all PCI-express silicon */

   755         u32 reg_ctrl, reg_ctrl_ext;

   756         u32 reg_tarc0, reg_tarc1;

   757         u32 reg_tctl;

   758         u32 reg_txdctl, reg_txdctl1;

   759 

   760         /* link autonegotiation/sync workarounds */

   761         reg_tarc0 = E1000_READ_REG(hw, TARC0);

   762         reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));

   763 

   764         /* Enable not-done TX descriptor counting */

   765         reg_txdctl = E1000_READ_REG(hw, TXDCTL);

   766         reg_txdctl |= E1000_TXDCTL_COUNT_DESC;

   767         E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);

   768         reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);

   769         reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;

   770         E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);

   771 

   772         switch (hw->mac_type) {

   773             case e1000_82571:

   774             case e1000_82572:

   775                 /* Clear PHY TX compatible mode bits */

   776                 reg_tarc1 = E1000_READ_REG(hw, TARC1);

   777                 reg_tarc1 &= ~((1 << 30)|(1 << 29));

   778 

   779                 /* link autonegotiation/sync workarounds */

   780                 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));

   781 

   782                 /* TX ring control fixes */

   783                 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));

   784 

   785                 /* Multiple read bit is reversed polarity */

   786                 reg_tctl = E1000_READ_REG(hw, TCTL);

   787                 if (reg_tctl & E1000_TCTL_MULR)

   788                     reg_tarc1 &= ~(1 << 28);

   789                 else

   790                     reg_tarc1 |= (1 << 28);

   791 

   792                 E1000_WRITE_REG(hw, TARC1, reg_tarc1);

   793                 break;

   794             case e1000_82573:

   795                 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   796                 reg_ctrl_ext &= ~(1 << 23);

   797                 reg_ctrl_ext |= (1 << 22);

   798 

   799                 /* TX byte count fix */

   800                 reg_ctrl = E1000_READ_REG(hw, CTRL);

   801                 reg_ctrl &= ~(1 << 29);

   802 

   803                 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);

   804                 E1000_WRITE_REG(hw, CTRL, reg_ctrl);

   805                 break;

   806             case e1000_80003es2lan:

   807                 /* improve small packet performace for fiber/serdes */

   808                 if ((hw->media_type == e1000_media_type_fiber) ||

   809                     (hw->media_type == e1000_media_type_internal_serdes)) {

   810                     reg_tarc0 &= ~(1 << 20);

   811                 }

   812 

   813                 /* Multiple read bit is reversed polarity */

   814                 reg_tctl = E1000_READ_REG(hw, TCTL);

   815                 reg_tarc1 = E1000_READ_REG(hw, TARC1);

   816                 if (reg_tctl & E1000_TCTL_MULR)

   817                     reg_tarc1 &= ~(1 << 28);

   818                 else

   819                     reg_tarc1 |= (1 << 28);

   820 

   821                 E1000_WRITE_REG(hw, TARC1, reg_tarc1);

   822                 break;

   823             case e1000_ich8lan:

   824                 /* Reduce concurrent DMA requests to 3 from 4 */

   825                 if ((hw->revision_id < 3) ||

   826                     ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&

   827                      (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))

   828                     reg_tarc0 |= ((1 << 29)|(1 << 28));

   829 

   830                 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   831                 reg_ctrl_ext |= (1 << 22);

   832                 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);

   833 

   834                 /* workaround TX hang with TSO=on */

   835                 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));

   836 

   837                 /* Multiple read bit is reversed polarity */

   838                 reg_tctl = E1000_READ_REG(hw, TCTL);

   839                 reg_tarc1 = E1000_READ_REG(hw, TARC1);

   840                 if (reg_tctl & E1000_TCTL_MULR)

   841                     reg_tarc1 &= ~(1 << 28);

   842                 else

   843                     reg_tarc1 |= (1 << 28);

   844 

   845                 /* workaround TX hang with TSO=on */

   846                 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));

   847 

   848                 E1000_WRITE_REG(hw, TARC1, reg_tarc1);

   849                 break;

   850             default:

   851                 break;

   852         }

   853 

   854         E1000_WRITE_REG(hw, TARC0, reg_tarc0);

   855     }

   856 }

   857 

   858 /******************************************************************************

   859  * Performs basic configuration of the adapter.

   860  *

   861  * hw - Struct containing variables accessed by shared code

   862  *

   863  * Assumes that the controller has previously been reset and is in a

   864  * post-reset uninitialized state. Initializes the receive address registers,

   865  * multicast table, and VLAN filter table. Calls routines to setup link

   866  * configuration and flow control settings. Clears all on-chip counters. Leaves

   867  * the transmit and receive units disabled and uninitialized.

   868  *****************************************************************************/

   869 s32

   870 e1000_init_hw(struct e1000_hw *hw)

   871 {

   872     u32 ctrl;

   873     u32 i;

   874     s32 ret_val;

   875     u32 mta_size;

   876     u32 reg_data;

   877     u32 ctrl_ext;

   878 

   879     DEBUGFUNC("e1000_init_hw");

   880 

   881     /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */

   882     if ((hw->mac_type == e1000_ich8lan) &&

   883         ((hw->revision_id < 3) ||

   884          ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&

   885           (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {

   886             reg_data = E1000_READ_REG(hw, STATUS);

   887             reg_data &= ~0x80000000;

   888             E1000_WRITE_REG(hw, STATUS, reg_data);

   889     }

   890 

   891     /* Initialize Identification LED */

   892     ret_val = e1000_id_led_init(hw);

   893     if (ret_val) {

   894         DEBUGOUT("Error Initializing Identification LED\n");

   895         return ret_val;

   896     }

   897 

   898     /* Set the media type and TBI compatibility */

   899     e1000_set_media_type(hw);

   900 

   901     /* Must be called after e1000_set_media_type because media_type is used */

   902     e1000_initialize_hardware_bits(hw);

   903 

   904     /* Disabling VLAN filtering. */

   905     DEBUGOUT("Initializing the IEEE VLAN\n");

   906     /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */

   907     if (hw->mac_type != e1000_ich8lan) {

   908         if (hw->mac_type < e1000_82545_rev_3)

   909             E1000_WRITE_REG(hw, VET, 0);

   910         e1000_clear_vfta(hw);

   911     }

   912 

   913     /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */

   914     if (hw->mac_type == e1000_82542_rev2_0) {

   915         DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");

   916         e1000_pci_clear_mwi(hw);

   917         E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);

   918         E1000_WRITE_FLUSH(hw);

   919         msleep(5);

   920     }

   921 

   922     /* Setup the receive address. This involves initializing all of the Receive

   923      * Address Registers (RARs 0 - 15).

   924      */

   925     e1000_init_rx_addrs(hw);

   926 

   927     /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */

   928     if (hw->mac_type == e1000_82542_rev2_0) {

   929         E1000_WRITE_REG(hw, RCTL, 0);

   930         E1000_WRITE_FLUSH(hw);

   931         msleep(1);

   932         if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   933             e1000_pci_set_mwi(hw);

   934     }

   935 

   936     /* Zero out the Multicast HASH table */

   937     DEBUGOUT("Zeroing the MTA\n");

   938     mta_size = E1000_MC_TBL_SIZE;

   939     if (hw->mac_type == e1000_ich8lan)

   940         mta_size = E1000_MC_TBL_SIZE_ICH8LAN;

   941     for (i = 0; i < mta_size; i++) {

   942         E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);

   943         /* use write flush to prevent Memory Write Block (MWB) from

   944          * occuring when accessing our register space */

   945         E1000_WRITE_FLUSH(hw);

   946     }

   947 

   948     /* Set the PCI priority bit correctly in the CTRL register.  This

   949      * determines if the adapter gives priority to receives, or if it

   950      * gives equal priority to transmits and receives.  Valid only on

   951      * 82542 and 82543 silicon.

   952      */

   953     if (hw->dma_fairness && hw->mac_type <= e1000_82543) {

   954         ctrl = E1000_READ_REG(hw, CTRL);

   955         E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);

   956     }

   957 

   958     switch (hw->mac_type) {

   959     case e1000_82545_rev_3:

   960     case e1000_82546_rev_3:

   961         break;

   962     default:

   963         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */

   964 	if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048)

   965 		e1000_pcix_set_mmrbc(hw, 2048);

   966 	break;

   967     }

   968 

   969     /* More time needed for PHY to initialize */

   970     if (hw->mac_type == e1000_ich8lan)

   971         msleep(15);

   972 

   973     /* Call a subroutine to configure the link and setup flow control. */

   974     ret_val = e1000_setup_link(hw);

   975 

   976     /* Set the transmit descriptor write-back policy */

   977     if (hw->mac_type > e1000_82544) {

   978         ctrl = E1000_READ_REG(hw, TXDCTL);

   979         ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;

   980         E1000_WRITE_REG(hw, TXDCTL, ctrl);

   981     }

   982 

   983     if (hw->mac_type == e1000_82573) {

   984         e1000_enable_tx_pkt_filtering(hw);

   985     }

   986 

   987     switch (hw->mac_type) {

   988     default:

   989         break;

   990     case e1000_80003es2lan:

   991         /* Enable retransmit on late collisions */

   992         reg_data = E1000_READ_REG(hw, TCTL);

   993         reg_data |= E1000_TCTL_RTLC;

   994         E1000_WRITE_REG(hw, TCTL, reg_data);

   995 

   996         /* Configure Gigabit Carry Extend Padding */

   997         reg_data = E1000_READ_REG(hw, TCTL_EXT);

   998         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;

   999         reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;

  1000         E1000_WRITE_REG(hw, TCTL_EXT, reg_data);

  1001 

  1002         /* Configure Transmit Inter-Packet Gap */

  1003         reg_data = E1000_READ_REG(hw, TIPG);

  1004         reg_data &= ~E1000_TIPG_IPGT_MASK;

  1005         reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;

  1006         E1000_WRITE_REG(hw, TIPG, reg_data);

  1007 

  1008         reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);

  1009         reg_data &= ~0x00100000;

  1010         E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);

  1011         /* Fall through */

  1012     case e1000_82571:

  1013     case e1000_82572:

  1014     case e1000_ich8lan:

  1015         ctrl = E1000_READ_REG(hw, TXDCTL1);

  1016         ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;

  1017         E1000_WRITE_REG(hw, TXDCTL1, ctrl);

  1018         break;

  1019     }

  1020 

  1021 

  1022     if (hw->mac_type == e1000_82573) {

  1023         u32 gcr = E1000_READ_REG(hw, GCR);

  1024         gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;

  1025         E1000_WRITE_REG(hw, GCR, gcr);

  1026     }

  1027 

  1028     /* Clear all of the statistics registers (clear on read).  It is

  1029      * important that we do this after we have tried to establish link

  1030      * because the symbol error count will increment wildly if there

  1031      * is no link.

  1032      */

  1033     e1000_clear_hw_cntrs(hw);

  1034 

  1035     /* ICH8 No-snoop bits are opposite polarity.

  1036      * Set to snoop by default after reset. */

  1037     if (hw->mac_type == e1000_ich8lan)

  1038         e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);

  1039 

  1040     if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||

  1041         hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {

  1042         ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

  1043         /* Relaxed ordering must be disabled to avoid a parity

  1044          * error crash in a PCI slot. */

  1045         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;

  1046         E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

  1047     }

  1048 

  1049     return ret_val;

  1050 }

  1051 

  1052 /******************************************************************************

  1053  * Adjust SERDES output amplitude based on EEPROM setting.

  1054  *

  1055  * hw - Struct containing variables accessed by shared code.

  1056  *****************************************************************************/

  1057 static s32

  1058 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)

  1059 {

  1060     u16 eeprom_data;

  1061     s32  ret_val;

  1062 

  1063     DEBUGFUNC("e1000_adjust_serdes_amplitude");

  1064 

  1065     if (hw->media_type != e1000_media_type_internal_serdes)

  1066         return E1000_SUCCESS;

  1067 

  1068     switch (hw->mac_type) {

  1069     case e1000_82545_rev_3:

  1070     case e1000_82546_rev_3:

  1071         break;

  1072     default:

  1073         return E1000_SUCCESS;

  1074     }

  1075 

  1076     ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);

  1077     if (ret_val) {

  1078         return ret_val;

  1079     }

  1080 

  1081     if (eeprom_data != EEPROM_RESERVED_WORD) {

  1082         /* Adjust SERDES output amplitude only. */

  1083         eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;

  1084         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);

  1085         if (ret_val)

  1086             return ret_val;

  1087     }

  1088 

  1089     return E1000_SUCCESS;

  1090 }

  1091 

  1092 /******************************************************************************

  1093  * Configures flow control and link settings.

  1094  *

  1095  * hw - Struct containing variables accessed by shared code

  1096  *

  1097  * Determines which flow control settings to use. Calls the apropriate media-

  1098  * specific link configuration function. Configures the flow control settings.

  1099  * Assuming the adapter has a valid link partner, a valid link should be

  1100  * established. Assumes the hardware has previously been reset and the

  1101  * transmitter and receiver are not enabled.

  1102  *****************************************************************************/

  1103 s32

  1104 e1000_setup_link(struct e1000_hw *hw)

  1105 {

  1106     u32 ctrl_ext;

  1107     s32 ret_val;

  1108     u16 eeprom_data;

  1109 

  1110     DEBUGFUNC("e1000_setup_link");

  1111 

  1112     /* In the case of the phy reset being blocked, we already have a link.

  1113      * We do not have to set it up again. */

  1114     if (e1000_check_phy_reset_block(hw))

  1115         return E1000_SUCCESS;

  1116 

  1117     /* Read and store word 0x0F of the EEPROM. This word contains bits

  1118      * that determine the hardware's default PAUSE (flow control) mode,

  1119      * a bit that determines whether the HW defaults to enabling or

  1120      * disabling auto-negotiation, and the direction of the

  1121      * SW defined pins. If there is no SW over-ride of the flow

  1122      * control setting, then the variable hw->fc will

  1123      * be initialized based on a value in the EEPROM.

  1124      */

  1125     if (hw->fc == E1000_FC_DEFAULT) {

  1126         switch (hw->mac_type) {

  1127         case e1000_ich8lan:

  1128         case e1000_82573:

  1129             hw->fc = E1000_FC_FULL;

  1130             break;

  1131         default:

  1132             ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

  1133                                         1, &eeprom_data);

  1134             if (ret_val) {

  1135                 DEBUGOUT("EEPROM Read Error\n");

  1136                 return -E1000_ERR_EEPROM;