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1 /* |
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2 * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
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3 * |
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4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> |
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5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> |
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6 * Copyright (c) a lot of people too. Please respect their work. |
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7 * |
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8 * See MAINTAINERS file for support contact information. |
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9 */ |
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10 |
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11 #include <linux/module.h> |
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12 #include <linux/moduleparam.h> |
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13 #include <linux/pci.h> |
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14 #include <linux/netdevice.h> |
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15 #include <linux/etherdevice.h> |
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16 #include <linux/delay.h> |
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17 #include <linux/ethtool.h> |
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18 #include <linux/mii.h> |
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19 #include <linux/if_vlan.h> |
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20 #include <linux/crc32.h> |
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21 #include <linux/in.h> |
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22 #include <linux/ip.h> |
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23 #include <linux/tcp.h> |
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24 #include <linux/init.h> |
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25 #include <linux/dma-mapping.h> |
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26 |
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27 #include <asm/system.h> |
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28 #include <asm/io.h> |
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29 #include <asm/irq.h> |
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30 |
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31 #define RTL8169_VERSION "2.3LK-NAPI" |
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32 #define MODULENAME "r8169" |
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33 #define PFX MODULENAME ": " |
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34 |
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35 #ifdef RTL8169_DEBUG |
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36 #define assert(expr) \ |
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37 if (!(expr)) { \ |
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38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
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39 #expr,__FILE__,__func__,__LINE__); \ |
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40 } |
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41 #define dprintk(fmt, args...) \ |
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42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) |
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43 #else |
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44 #define assert(expr) do {} while (0) |
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45 #define dprintk(fmt, args...) do {} while (0) |
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46 #endif /* RTL8169_DEBUG */ |
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47 |
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48 #define R8169_MSG_DEFAULT \ |
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49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
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50 |
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51 #define TX_BUFFS_AVAIL(tp) \ |
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52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) |
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53 |
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54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
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55 static const int max_interrupt_work = 20; |
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56 |
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57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
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58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
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59 static const int multicast_filter_limit = 32; |
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60 |
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61 /* MAC address length */ |
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62 #define MAC_ADDR_LEN 6 |
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63 |
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64 #define MAX_READ_REQUEST_SHIFT 12 |
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65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
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66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
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69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ |
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70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
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71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
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72 |
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73 #define R8169_REGS_SIZE 256 |
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74 #define R8169_NAPI_WEIGHT 64 |
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75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
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76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
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77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
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78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
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79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
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80 |
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81 #define RTL8169_TX_TIMEOUT (6*HZ) |
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82 #define RTL8169_PHY_TIMEOUT (10*HZ) |
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83 |
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84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
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85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) |
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86 #define RTL_EEPROM_SIG_ADDR 0x0000 |
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87 |
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88 /* write/read MMIO register */ |
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89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
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90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
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91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
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92 #define RTL_R8(reg) readb (ioaddr + (reg)) |
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93 #define RTL_R16(reg) readw (ioaddr + (reg)) |
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94 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) |
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95 |
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96 enum mac_version { |
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97 RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
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98 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S |
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99 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S |
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100 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB |
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101 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd |
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102 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
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103 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e |
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104 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e |
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105 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e |
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106 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e |
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107 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
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108 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
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109 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb |
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110 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? |
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111 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? |
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112 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec |
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113 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf |
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114 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP |
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115 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C |
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116 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C |
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117 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C |
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118 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C |
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119 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP |
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120 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP |
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121 RTL_GIGA_MAC_VER_25 = 0x19 // 8168D |
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122 }; |
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123 |
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124 #define _R(NAME,MAC,MASK) \ |
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125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } |
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126 |
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127 static const struct { |
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128 const char *name; |
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129 u8 mac_version; |
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130 u32 RxConfigMask; /* Clears the bits supported by this chip */ |
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131 } rtl_chip_info[] = { |
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132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
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133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S |
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134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S |
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135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB |
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136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd |
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137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
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138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E |
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139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E |
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140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E |
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141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E |
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142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
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143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E |
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144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 |
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145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 |
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146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 |
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147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E |
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148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E |
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149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E |
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150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E |
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151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E |
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152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E |
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153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E |
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154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E |
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155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E |
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156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E |
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157 }; |
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158 #undef _R |
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159 |
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160 enum cfg_version { |
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161 RTL_CFG_0 = 0x00, |
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162 RTL_CFG_1, |
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163 RTL_CFG_2 |
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164 }; |
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165 |
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166 static void rtl_hw_start_8169(struct net_device *); |
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167 static void rtl_hw_start_8168(struct net_device *); |
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168 static void rtl_hw_start_8101(struct net_device *); |
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169 |
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170 static struct pci_device_id rtl8169_pci_tbl[] = { |
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171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
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172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
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173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
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174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
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175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
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176 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
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177 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
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178 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
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179 { PCI_VENDOR_ID_LINKSYS, 0x1032, |
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180 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
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181 { 0x0001, 0x8168, |
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182 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, |
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183 {0,}, |
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184 }; |
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185 |
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186 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); |
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187 |
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188 static int rx_copybreak = 200; |
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189 static int use_dac; |
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190 static struct { |
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191 u32 msg_enable; |
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192 } debug = { -1 }; |
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193 |
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194 enum rtl_registers { |
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195 MAC0 = 0, /* Ethernet hardware address. */ |
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196 MAC4 = 4, |
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197 MAR0 = 8, /* Multicast filter. */ |
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198 CounterAddrLow = 0x10, |
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199 CounterAddrHigh = 0x14, |
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200 TxDescStartAddrLow = 0x20, |
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201 TxDescStartAddrHigh = 0x24, |
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202 TxHDescStartAddrLow = 0x28, |
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203 TxHDescStartAddrHigh = 0x2c, |
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204 FLASH = 0x30, |
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205 ERSR = 0x36, |
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206 ChipCmd = 0x37, |
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207 TxPoll = 0x38, |
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208 IntrMask = 0x3c, |
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209 IntrStatus = 0x3e, |
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210 TxConfig = 0x40, |
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211 RxConfig = 0x44, |
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212 RxMissed = 0x4c, |
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213 Cfg9346 = 0x50, |
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214 Config0 = 0x51, |
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215 Config1 = 0x52, |
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216 Config2 = 0x53, |
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217 Config3 = 0x54, |
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218 Config4 = 0x55, |
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219 Config5 = 0x56, |
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220 MultiIntr = 0x5c, |
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221 PHYAR = 0x60, |
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222 PHYstatus = 0x6c, |
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223 RxMaxSize = 0xda, |
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224 CPlusCmd = 0xe0, |
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225 IntrMitigate = 0xe2, |
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226 RxDescAddrLow = 0xe4, |
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227 RxDescAddrHigh = 0xe8, |
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228 EarlyTxThres = 0xec, |
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229 FuncEvent = 0xf0, |
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230 FuncEventMask = 0xf4, |
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231 FuncPresetState = 0xf8, |
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232 FuncForceEvent = 0xfc, |
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233 }; |
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234 |
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235 enum rtl8110_registers { |
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236 TBICSR = 0x64, |
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237 TBI_ANAR = 0x68, |
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238 TBI_LPAR = 0x6a, |
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239 }; |
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240 |
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241 enum rtl8168_8101_registers { |
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242 CSIDR = 0x64, |
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243 CSIAR = 0x68, |
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244 #define CSIAR_FLAG 0x80000000 |
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245 #define CSIAR_WRITE_CMD 0x80000000 |
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246 #define CSIAR_BYTE_ENABLE 0x0f |
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247 #define CSIAR_BYTE_ENABLE_SHIFT 12 |
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248 #define CSIAR_ADDR_MASK 0x0fff |
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249 |
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250 EPHYAR = 0x80, |
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251 #define EPHYAR_FLAG 0x80000000 |
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252 #define EPHYAR_WRITE_CMD 0x80000000 |
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253 #define EPHYAR_REG_MASK 0x1f |
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254 #define EPHYAR_REG_SHIFT 16 |
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255 #define EPHYAR_DATA_MASK 0xffff |
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256 DBG_REG = 0xd1, |
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257 #define FIX_NAK_1 (1 << 4) |
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258 #define FIX_NAK_2 (1 << 3) |
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259 }; |
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260 |
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261 enum rtl_register_content { |
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262 /* InterruptStatusBits */ |
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263 SYSErr = 0x8000, |
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264 PCSTimeout = 0x4000, |
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265 SWInt = 0x0100, |
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266 TxDescUnavail = 0x0080, |
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267 RxFIFOOver = 0x0040, |
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268 LinkChg = 0x0020, |
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269 RxOverflow = 0x0010, |
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270 TxErr = 0x0008, |
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271 TxOK = 0x0004, |
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272 RxErr = 0x0002, |
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273 RxOK = 0x0001, |
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274 |
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275 /* RxStatusDesc */ |
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276 RxFOVF = (1 << 23), |
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277 RxRWT = (1 << 22), |
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278 RxRES = (1 << 21), |
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279 RxRUNT = (1 << 20), |
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280 RxCRC = (1 << 19), |
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281 |
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282 /* ChipCmdBits */ |
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283 CmdReset = 0x10, |
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284 CmdRxEnb = 0x08, |
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285 CmdTxEnb = 0x04, |
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286 RxBufEmpty = 0x01, |
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287 |
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288 /* TXPoll register p.5 */ |
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289 HPQ = 0x80, /* Poll cmd on the high prio queue */ |
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290 NPQ = 0x40, /* Poll cmd on the low prio queue */ |
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291 FSWInt = 0x01, /* Forced software interrupt */ |
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292 |
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293 /* Cfg9346Bits */ |
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294 Cfg9346_Lock = 0x00, |
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295 Cfg9346_Unlock = 0xc0, |
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296 |
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297 /* rx_mode_bits */ |
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298 AcceptErr = 0x20, |
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299 AcceptRunt = 0x10, |
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300 AcceptBroadcast = 0x08, |
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301 AcceptMulticast = 0x04, |
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302 AcceptMyPhys = 0x02, |
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303 AcceptAllPhys = 0x01, |
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304 |
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305 /* RxConfigBits */ |
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306 RxCfgFIFOShift = 13, |
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307 RxCfgDMAShift = 8, |
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308 |
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309 /* TxConfigBits */ |
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310 TxInterFrameGapShift = 24, |
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311 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
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312 |
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313 /* Config1 register p.24 */ |
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314 LEDS1 = (1 << 7), |
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315 LEDS0 = (1 << 6), |
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316 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
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317 Speed_down = (1 << 4), |
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318 MEMMAP = (1 << 3), |
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319 IOMAP = (1 << 2), |
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320 VPD = (1 << 1), |
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321 PMEnable = (1 << 0), /* Power Management Enable */ |
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322 |
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323 /* Config2 register p. 25 */ |
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324 PCI_Clock_66MHz = 0x01, |
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325 PCI_Clock_33MHz = 0x00, |
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326 |
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327 /* Config3 register p.25 */ |
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328 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ |
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329 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ |
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330 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
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331 |
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332 /* Config5 register p.27 */ |
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333 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
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334 MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
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335 UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
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336 LanWake = (1 << 1), /* LanWake enable/disable */ |
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337 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
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338 |
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339 /* TBICSR p.28 */ |
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340 TBIReset = 0x80000000, |
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341 TBILoopback = 0x40000000, |
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342 TBINwEnable = 0x20000000, |
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343 TBINwRestart = 0x10000000, |
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344 TBILinkOk = 0x02000000, |
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345 TBINwComplete = 0x01000000, |
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346 |
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347 /* CPlusCmd p.31 */ |
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348 EnableBist = (1 << 15), // 8168 8101 |
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349 Mac_dbgo_oe = (1 << 14), // 8168 8101 |
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350 Normal_mode = (1 << 13), // unused |
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351 Force_half_dup = (1 << 12), // 8168 8101 |
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352 Force_rxflow_en = (1 << 11), // 8168 8101 |
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353 Force_txflow_en = (1 << 10), // 8168 8101 |
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354 Cxpl_dbg_sel = (1 << 9), // 8168 8101 |
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355 ASF = (1 << 8), // 8168 8101 |
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356 PktCntrDisable = (1 << 7), // 8168 8101 |
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357 Mac_dbgo_sel = 0x001c, // 8168 |
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358 RxVlan = (1 << 6), |
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359 RxChkSum = (1 << 5), |
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360 PCIDAC = (1 << 4), |
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361 PCIMulRW = (1 << 3), |
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362 INTT_0 = 0x0000, // 8168 |
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363 INTT_1 = 0x0001, // 8168 |
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364 INTT_2 = 0x0002, // 8168 |
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365 INTT_3 = 0x0003, // 8168 |
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366 |
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367 /* rtl8169_PHYstatus */ |
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368 TBI_Enable = 0x80, |
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369 TxFlowCtrl = 0x40, |
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370 RxFlowCtrl = 0x20, |
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371 _1000bpsF = 0x10, |
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372 _100bps = 0x08, |
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373 _10bps = 0x04, |
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374 LinkStatus = 0x02, |
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375 FullDup = 0x01, |
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376 |
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377 /* _TBICSRBit */ |
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378 TBILinkOK = 0x02000000, |
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379 |
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380 /* DumpCounterCommand */ |
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381 CounterDump = 0x8, |
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382 }; |
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383 |
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384 enum desc_status_bit { |
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385 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
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386 RingEnd = (1 << 30), /* End of descriptor ring */ |
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387 FirstFrag = (1 << 29), /* First segment of a packet */ |
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388 LastFrag = (1 << 28), /* Final segment of a packet */ |
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389 |
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390 /* Tx private */ |
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391 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ |
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392 MSSShift = 16, /* MSS value position */ |
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393 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ |
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394 IPCS = (1 << 18), /* Calculate IP checksum */ |
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395 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ |
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396 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ |
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397 TxVlanTag = (1 << 17), /* Add VLAN tag */ |
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398 |
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399 /* Rx private */ |
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400 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ |
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401 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ |
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402 |
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403 #define RxProtoUDP (PID1) |
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404 #define RxProtoTCP (PID0) |
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405 #define RxProtoIP (PID1 | PID0) |
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406 #define RxProtoMask RxProtoIP |
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407 |
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408 IPFail = (1 << 16), /* IP checksum failed */ |
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409 UDPFail = (1 << 15), /* UDP/IP checksum failed */ |
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410 TCPFail = (1 << 14), /* TCP/IP checksum failed */ |
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411 RxVlanTag = (1 << 16), /* VLAN tag available */ |
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412 }; |
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413 |
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414 #define RsvdMask 0x3fffc000 |
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415 |
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416 struct TxDesc { |
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417 __le32 opts1; |
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418 __le32 opts2; |
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419 __le64 addr; |
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420 }; |
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421 |
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422 struct RxDesc { |
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423 __le32 opts1; |
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424 __le32 opts2; |
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425 __le64 addr; |
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426 }; |
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427 |
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428 struct ring_info { |
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429 struct sk_buff *skb; |
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430 u32 len; |
|
431 u8 __pad[sizeof(void *) - sizeof(u32)]; |
|
432 }; |
|
433 |
|
434 enum features { |
|
435 RTL_FEATURE_WOL = (1 << 0), |
|
436 RTL_FEATURE_MSI = (1 << 1), |
|
437 RTL_FEATURE_GMII = (1 << 2), |
|
438 }; |
|
439 |
|
440 struct rtl8169_private { |
|
441 void __iomem *mmio_addr; /* memory map physical address */ |
|
442 struct pci_dev *pci_dev; /* Index of PCI device */ |
|
443 struct net_device *dev; |
|
444 struct napi_struct napi; |
|
445 spinlock_t lock; /* spin lock flag */ |
|
446 u32 msg_enable; |
|
447 int chipset; |
|
448 int mac_version; |
|
449 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
|
450 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
|
451 u32 dirty_rx; |
|
452 u32 dirty_tx; |
|
453 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
|
454 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ |
|
455 dma_addr_t TxPhyAddr; |
|
456 dma_addr_t RxPhyAddr; |
|
457 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ |
|
458 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
|
459 unsigned align; |
|
460 unsigned rx_buf_sz; |
|
461 struct timer_list timer; |
|
462 u16 cp_cmd; |
|
463 u16 intr_event; |
|
464 u16 napi_event; |
|
465 u16 intr_mask; |
|
466 int phy_auto_nego_reg; |
|
467 int phy_1000_ctrl_reg; |
|
468 #ifdef CONFIG_R8169_VLAN |
|
469 struct vlan_group *vlgrp; |
|
470 #endif |
|
471 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); |
|
472 int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
|
473 void (*phy_reset_enable)(void __iomem *); |
|
474 void (*hw_start)(struct net_device *); |
|
475 unsigned int (*phy_reset_pending)(void __iomem *); |
|
476 unsigned int (*link_ok)(void __iomem *); |
|
477 int pcie_cap; |
|
478 struct delayed_work task; |
|
479 unsigned features; |
|
480 |
|
481 struct mii_if_info mii; |
|
482 }; |
|
483 |
|
484 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
|
485 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
|
486 module_param(rx_copybreak, int, 0); |
|
487 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); |
|
488 module_param(use_dac, int, 0); |
|
489 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
|
490 module_param_named(debug, debug.msg_enable, int, 0); |
|
491 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); |
|
492 MODULE_LICENSE("GPL"); |
|
493 MODULE_VERSION(RTL8169_VERSION); |
|
494 |
|
495 static int rtl8169_open(struct net_device *dev); |
|
496 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev); |
|
497 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
|
498 static int rtl8169_init_ring(struct net_device *dev); |
|
499 static void rtl_hw_start(struct net_device *dev); |
|
500 static int rtl8169_close(struct net_device *dev); |
|
501 static void rtl_set_rx_mode(struct net_device *dev); |
|
502 static void rtl8169_tx_timeout(struct net_device *dev); |
|
503 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
|
504 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
|
505 void __iomem *, u32 budget); |
|
506 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
|
507 static void rtl8169_down(struct net_device *dev); |
|
508 static void rtl8169_rx_clear(struct rtl8169_private *tp); |
|
509 static int rtl8169_poll(struct napi_struct *napi, int budget); |
|
510 |
|
511 static const unsigned int rtl8169_rx_config = |
|
512 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
|
513 |
|
514 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
515 { |
|
516 int i; |
|
517 |
|
518 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
|
519 |
|
520 for (i = 20; i > 0; i--) { |
|
521 /* |
|
522 * Check if the RTL8169 has completed writing to the specified |
|
523 * MII register. |
|
524 */ |
|
525 if (!(RTL_R32(PHYAR) & 0x80000000)) |
|
526 break; |
|
527 udelay(25); |
|
528 } |
|
529 } |
|
530 |
|
531 static int mdio_read(void __iomem *ioaddr, int reg_addr) |
|
532 { |
|
533 int i, value = -1; |
|
534 |
|
535 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
|
536 |
|
537 for (i = 20; i > 0; i--) { |
|
538 /* |
|
539 * Check if the RTL8169 has completed retrieving data from |
|
540 * the specified MII register. |
|
541 */ |
|
542 if (RTL_R32(PHYAR) & 0x80000000) { |
|
543 value = RTL_R32(PHYAR) & 0xffff; |
|
544 break; |
|
545 } |
|
546 udelay(25); |
|
547 } |
|
548 return value; |
|
549 } |
|
550 |
|
551 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) |
|
552 { |
|
553 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); |
|
554 } |
|
555 |
|
556 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
|
557 int val) |
|
558 { |
|
559 struct rtl8169_private *tp = netdev_priv(dev); |
|
560 void __iomem *ioaddr = tp->mmio_addr; |
|
561 |
|
562 mdio_write(ioaddr, location, val); |
|
563 } |
|
564 |
|
565 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) |
|
566 { |
|
567 struct rtl8169_private *tp = netdev_priv(dev); |
|
568 void __iomem *ioaddr = tp->mmio_addr; |
|
569 |
|
570 return mdio_read(ioaddr, location); |
|
571 } |
|
572 |
|
573 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
|
574 { |
|
575 unsigned int i; |
|
576 |
|
577 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | |
|
578 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
579 |
|
580 for (i = 0; i < 100; i++) { |
|
581 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) |
|
582 break; |
|
583 udelay(10); |
|
584 } |
|
585 } |
|
586 |
|
587 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) |
|
588 { |
|
589 u16 value = 0xffff; |
|
590 unsigned int i; |
|
591 |
|
592 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
593 |
|
594 for (i = 0; i < 100; i++) { |
|
595 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { |
|
596 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; |
|
597 break; |
|
598 } |
|
599 udelay(10); |
|
600 } |
|
601 |
|
602 return value; |
|
603 } |
|
604 |
|
605 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) |
|
606 { |
|
607 unsigned int i; |
|
608 |
|
609 RTL_W32(CSIDR, value); |
|
610 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | |
|
611 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
612 |
|
613 for (i = 0; i < 100; i++) { |
|
614 if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) |
|
615 break; |
|
616 udelay(10); |
|
617 } |
|
618 } |
|
619 |
|
620 static u32 rtl_csi_read(void __iomem *ioaddr, int addr) |
|
621 { |
|
622 u32 value = ~0x00; |
|
623 unsigned int i; |
|
624 |
|
625 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | |
|
626 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
627 |
|
628 for (i = 0; i < 100; i++) { |
|
629 if (RTL_R32(CSIAR) & CSIAR_FLAG) { |
|
630 value = RTL_R32(CSIDR); |
|
631 break; |
|
632 } |
|
633 udelay(10); |
|
634 } |
|
635 |
|
636 return value; |
|
637 } |
|
638 |
|
639 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
|
640 { |
|
641 RTL_W16(IntrMask, 0x0000); |
|
642 |
|
643 RTL_W16(IntrStatus, 0xffff); |
|
644 } |
|
645 |
|
646 static void rtl8169_asic_down(void __iomem *ioaddr) |
|
647 { |
|
648 RTL_W8(ChipCmd, 0x00); |
|
649 rtl8169_irq_mask_and_ack(ioaddr); |
|
650 RTL_R16(CPlusCmd); |
|
651 } |
|
652 |
|
653 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) |
|
654 { |
|
655 return RTL_R32(TBICSR) & TBIReset; |
|
656 } |
|
657 |
|
658 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) |
|
659 { |
|
660 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; |
|
661 } |
|
662 |
|
663 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) |
|
664 { |
|
665 return RTL_R32(TBICSR) & TBILinkOk; |
|
666 } |
|
667 |
|
668 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) |
|
669 { |
|
670 return RTL_R8(PHYstatus) & LinkStatus; |
|
671 } |
|
672 |
|
673 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) |
|
674 { |
|
675 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
|
676 } |
|
677 |
|
678 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) |
|
679 { |
|
680 unsigned int val; |
|
681 |
|
682 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; |
|
683 mdio_write(ioaddr, MII_BMCR, val & 0xffff); |
|
684 } |
|
685 |
|
686 static void rtl8169_check_link_status(struct net_device *dev, |
|
687 struct rtl8169_private *tp, |
|
688 void __iomem *ioaddr) |
|
689 { |
|
690 unsigned long flags; |
|
691 |
|
692 spin_lock_irqsave(&tp->lock, flags); |
|
693 if (tp->link_ok(ioaddr)) { |
|
694 netif_carrier_on(dev); |
|
695 if (netif_msg_ifup(tp)) |
|
696 printk(KERN_INFO PFX "%s: link up\n", dev->name); |
|
697 } else { |
|
698 if (netif_msg_ifdown(tp)) |
|
699 printk(KERN_INFO PFX "%s: link down\n", dev->name); |
|
700 netif_carrier_off(dev); |
|
701 } |
|
702 spin_unlock_irqrestore(&tp->lock, flags); |
|
703 } |
|
704 |
|
705 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
706 { |
|
707 struct rtl8169_private *tp = netdev_priv(dev); |
|
708 void __iomem *ioaddr = tp->mmio_addr; |
|
709 u8 options; |
|
710 |
|
711 wol->wolopts = 0; |
|
712 |
|
713 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
|
714 wol->supported = WAKE_ANY; |
|
715 |
|
716 spin_lock_irq(&tp->lock); |
|
717 |
|
718 options = RTL_R8(Config1); |
|
719 if (!(options & PMEnable)) |
|
720 goto out_unlock; |
|
721 |
|
722 options = RTL_R8(Config3); |
|
723 if (options & LinkUp) |
|
724 wol->wolopts |= WAKE_PHY; |
|
725 if (options & MagicPacket) |
|
726 wol->wolopts |= WAKE_MAGIC; |
|
727 |
|
728 options = RTL_R8(Config5); |
|
729 if (options & UWF) |
|
730 wol->wolopts |= WAKE_UCAST; |
|
731 if (options & BWF) |
|
732 wol->wolopts |= WAKE_BCAST; |
|
733 if (options & MWF) |
|
734 wol->wolopts |= WAKE_MCAST; |
|
735 |
|
736 out_unlock: |
|
737 spin_unlock_irq(&tp->lock); |
|
738 } |
|
739 |
|
740 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
741 { |
|
742 struct rtl8169_private *tp = netdev_priv(dev); |
|
743 void __iomem *ioaddr = tp->mmio_addr; |
|
744 unsigned int i; |
|
745 static struct { |
|
746 u32 opt; |
|
747 u16 reg; |
|
748 u8 mask; |
|
749 } cfg[] = { |
|
750 { WAKE_ANY, Config1, PMEnable }, |
|
751 { WAKE_PHY, Config3, LinkUp }, |
|
752 { WAKE_MAGIC, Config3, MagicPacket }, |
|
753 { WAKE_UCAST, Config5, UWF }, |
|
754 { WAKE_BCAST, Config5, BWF }, |
|
755 { WAKE_MCAST, Config5, MWF }, |
|
756 { WAKE_ANY, Config5, LanWake } |
|
757 }; |
|
758 |
|
759 spin_lock_irq(&tp->lock); |
|
760 |
|
761 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
762 |
|
763 for (i = 0; i < ARRAY_SIZE(cfg); i++) { |
|
764 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
|
765 if (wol->wolopts & cfg[i].opt) |
|
766 options |= cfg[i].mask; |
|
767 RTL_W8(cfg[i].reg, options); |
|
768 } |
|
769 |
|
770 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
771 |
|
772 if (wol->wolopts) |
|
773 tp->features |= RTL_FEATURE_WOL; |
|
774 else |
|
775 tp->features &= ~RTL_FEATURE_WOL; |
|
776 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
|
777 |
|
778 spin_unlock_irq(&tp->lock); |
|
779 |
|
780 return 0; |
|
781 } |
|
782 |
|
783 static void rtl8169_get_drvinfo(struct net_device *dev, |
|
784 struct ethtool_drvinfo *info) |
|
785 { |
|
786 struct rtl8169_private *tp = netdev_priv(dev); |
|
787 |
|
788 strcpy(info->driver, MODULENAME); |
|
789 strcpy(info->version, RTL8169_VERSION); |
|
790 strcpy(info->bus_info, pci_name(tp->pci_dev)); |
|
791 } |
|
792 |
|
793 static int rtl8169_get_regs_len(struct net_device *dev) |
|
794 { |
|
795 return R8169_REGS_SIZE; |
|
796 } |
|
797 |
|
798 static int rtl8169_set_speed_tbi(struct net_device *dev, |
|
799 u8 autoneg, u16 speed, u8 duplex) |
|
800 { |
|
801 struct rtl8169_private *tp = netdev_priv(dev); |
|
802 void __iomem *ioaddr = tp->mmio_addr; |
|
803 int ret = 0; |
|
804 u32 reg; |
|
805 |
|
806 reg = RTL_R32(TBICSR); |
|
807 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
|
808 (duplex == DUPLEX_FULL)) { |
|
809 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
|
810 } else if (autoneg == AUTONEG_ENABLE) |
|
811 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); |
|
812 else { |
|
813 if (netif_msg_link(tp)) { |
|
814 printk(KERN_WARNING "%s: " |
|
815 "incorrect speed setting refused in TBI mode\n", |
|
816 dev->name); |
|
817 } |
|
818 ret = -EOPNOTSUPP; |
|
819 } |
|
820 |
|
821 return ret; |
|
822 } |
|
823 |
|
824 static int rtl8169_set_speed_xmii(struct net_device *dev, |
|
825 u8 autoneg, u16 speed, u8 duplex) |
|
826 { |
|
827 struct rtl8169_private *tp = netdev_priv(dev); |
|
828 void __iomem *ioaddr = tp->mmio_addr; |
|
829 int auto_nego, giga_ctrl; |
|
830 |
|
831 auto_nego = mdio_read(ioaddr, MII_ADVERTISE); |
|
832 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
833 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
834 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); |
|
835 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
836 |
|
837 if (autoneg == AUTONEG_ENABLE) { |
|
838 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
839 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
840 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
|
841 } else { |
|
842 if (speed == SPEED_10) |
|
843 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
|
844 else if (speed == SPEED_100) |
|
845 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
|
846 else if (speed == SPEED_1000) |
|
847 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
|
848 |
|
849 if (duplex == DUPLEX_HALF) |
|
850 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL); |
|
851 |
|
852 if (duplex == DUPLEX_FULL) |
|
853 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF); |
|
854 |
|
855 /* This tweak comes straight from Realtek's driver. */ |
|
856 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) && |
|
857 ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
858 (tp->mac_version == RTL_GIGA_MAC_VER_16))) { |
|
859 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA; |
|
860 } |
|
861 } |
|
862 |
|
863 /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
|
864 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) || |
|
865 (tp->mac_version == RTL_GIGA_MAC_VER_08) || |
|
866 (tp->mac_version == RTL_GIGA_MAC_VER_09) || |
|
867 (tp->mac_version == RTL_GIGA_MAC_VER_10) || |
|
868 (tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
869 (tp->mac_version == RTL_GIGA_MAC_VER_14) || |
|
870 (tp->mac_version == RTL_GIGA_MAC_VER_15) || |
|
871 (tp->mac_version == RTL_GIGA_MAC_VER_16)) { |
|
872 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) && |
|
873 netif_msg_link(tp)) { |
|
874 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", |
|
875 dev->name); |
|
876 } |
|
877 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
878 } |
|
879 |
|
880 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
881 |
|
882 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
|
883 (tp->mac_version == RTL_GIGA_MAC_VER_12) || |
|
884 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { |
|
885 /* |
|
886 * Wake up the PHY. |
|
887 * Vendor specific (0x1f) and reserved (0x0e) MII registers. |
|
888 */ |
|
889 mdio_write(ioaddr, 0x1f, 0x0000); |
|
890 mdio_write(ioaddr, 0x0e, 0x0000); |
|
891 } |
|
892 |
|
893 tp->phy_auto_nego_reg = auto_nego; |
|
894 tp->phy_1000_ctrl_reg = giga_ctrl; |
|
895 |
|
896 mdio_write(ioaddr, MII_ADVERTISE, auto_nego); |
|
897 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); |
|
898 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); |
|
899 return 0; |
|
900 } |
|
901 |
|
902 static int rtl8169_set_speed(struct net_device *dev, |
|
903 u8 autoneg, u16 speed, u8 duplex) |
|
904 { |
|
905 struct rtl8169_private *tp = netdev_priv(dev); |
|
906 int ret; |
|
907 |
|
908 ret = tp->set_speed(dev, autoneg, speed, duplex); |
|
909 |
|
910 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
911 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
912 |
|
913 return ret; |
|
914 } |
|
915 |
|
916 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
917 { |
|
918 struct rtl8169_private *tp = netdev_priv(dev); |
|
919 unsigned long flags; |
|
920 int ret; |
|
921 |
|
922 spin_lock_irqsave(&tp->lock, flags); |
|
923 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); |
|
924 spin_unlock_irqrestore(&tp->lock, flags); |
|
925 |
|
926 return ret; |
|
927 } |
|
928 |
|
929 static u32 rtl8169_get_rx_csum(struct net_device *dev) |
|
930 { |
|
931 struct rtl8169_private *tp = netdev_priv(dev); |
|
932 |
|
933 return tp->cp_cmd & RxChkSum; |
|
934 } |
|
935 |
|
936 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) |
|
937 { |
|
938 struct rtl8169_private *tp = netdev_priv(dev); |
|
939 void __iomem *ioaddr = tp->mmio_addr; |
|
940 unsigned long flags; |
|
941 |
|
942 spin_lock_irqsave(&tp->lock, flags); |
|
943 |
|
944 if (data) |
|
945 tp->cp_cmd |= RxChkSum; |
|
946 else |
|
947 tp->cp_cmd &= ~RxChkSum; |
|
948 |
|
949 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
950 RTL_R16(CPlusCmd); |
|
951 |
|
952 spin_unlock_irqrestore(&tp->lock, flags); |
|
953 |
|
954 return 0; |
|
955 } |
|
956 |
|
957 #ifdef CONFIG_R8169_VLAN |
|
958 |
|
959 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
960 struct sk_buff *skb) |
|
961 { |
|
962 return (tp->vlgrp && vlan_tx_tag_present(skb)) ? |
|
963 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
|
964 } |
|
965 |
|
966 static void rtl8169_vlan_rx_register(struct net_device *dev, |
|
967 struct vlan_group *grp) |
|
968 { |
|
969 struct rtl8169_private *tp = netdev_priv(dev); |
|
970 void __iomem *ioaddr = tp->mmio_addr; |
|
971 unsigned long flags; |
|
972 |
|
973 spin_lock_irqsave(&tp->lock, flags); |
|
974 tp->vlgrp = grp; |
|
975 if (tp->vlgrp) |
|
976 tp->cp_cmd |= RxVlan; |
|
977 else |
|
978 tp->cp_cmd &= ~RxVlan; |
|
979 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
980 RTL_R16(CPlusCmd); |
|
981 spin_unlock_irqrestore(&tp->lock, flags); |
|
982 } |
|
983 |
|
984 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
985 struct sk_buff *skb) |
|
986 { |
|
987 u32 opts2 = le32_to_cpu(desc->opts2); |
|
988 struct vlan_group *vlgrp = tp->vlgrp; |
|
989 int ret; |
|
990 |
|
991 if (vlgrp && (opts2 & RxVlanTag)) { |
|
992 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff)); |
|
993 ret = 0; |
|
994 } else |
|
995 ret = -1; |
|
996 desc->opts2 = 0; |
|
997 return ret; |
|
998 } |
|
999 |
|
1000 #else /* !CONFIG_R8169_VLAN */ |
|
1001 |
|
1002 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
1003 struct sk_buff *skb) |
|
1004 { |
|
1005 return 0; |
|
1006 } |
|
1007 |
|
1008 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
1009 struct sk_buff *skb) |
|
1010 { |
|
1011 return -1; |
|
1012 } |
|
1013 |
|
1014 #endif |
|
1015 |
|
1016 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1017 { |
|
1018 struct rtl8169_private *tp = netdev_priv(dev); |
|
1019 void __iomem *ioaddr = tp->mmio_addr; |
|
1020 u32 status; |
|
1021 |
|
1022 cmd->supported = |
|
1023 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
|
1024 cmd->port = PORT_FIBRE; |
|
1025 cmd->transceiver = XCVR_INTERNAL; |
|
1026 |
|
1027 status = RTL_R32(TBICSR); |
|
1028 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
|
1029 cmd->autoneg = !!(status & TBINwEnable); |
|
1030 |
|
1031 cmd->speed = SPEED_1000; |
|
1032 cmd->duplex = DUPLEX_FULL; /* Always set */ |
|
1033 |
|
1034 return 0; |
|
1035 } |
|
1036 |
|
1037 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1038 { |
|
1039 struct rtl8169_private *tp = netdev_priv(dev); |
|
1040 |
|
1041 return mii_ethtool_gset(&tp->mii, cmd); |
|
1042 } |
|
1043 |
|
1044 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1045 { |
|
1046 struct rtl8169_private *tp = netdev_priv(dev); |
|
1047 unsigned long flags; |
|
1048 int rc; |
|
1049 |
|
1050 spin_lock_irqsave(&tp->lock, flags); |
|
1051 |
|
1052 rc = tp->get_settings(dev, cmd); |
|
1053 |
|
1054 spin_unlock_irqrestore(&tp->lock, flags); |
|
1055 return rc; |
|
1056 } |
|
1057 |
|
1058 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
|
1059 void *p) |
|
1060 { |
|
1061 struct rtl8169_private *tp = netdev_priv(dev); |
|
1062 unsigned long flags; |
|
1063 |
|
1064 if (regs->len > R8169_REGS_SIZE) |
|
1065 regs->len = R8169_REGS_SIZE; |
|
1066 |
|
1067 spin_lock_irqsave(&tp->lock, flags); |
|
1068 memcpy_fromio(p, tp->mmio_addr, regs->len); |
|
1069 spin_unlock_irqrestore(&tp->lock, flags); |
|
1070 } |
|
1071 |
|
1072 static u32 rtl8169_get_msglevel(struct net_device *dev) |
|
1073 { |
|
1074 struct rtl8169_private *tp = netdev_priv(dev); |
|
1075 |
|
1076 return tp->msg_enable; |
|
1077 } |
|
1078 |
|
1079 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) |
|
1080 { |
|
1081 struct rtl8169_private *tp = netdev_priv(dev); |
|
1082 |
|
1083 tp->msg_enable = value; |
|
1084 } |
|
1085 |
|
1086 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
|
1087 "tx_packets", |
|
1088 "rx_packets", |
|
1089 "tx_errors", |
|
1090 "rx_errors", |
|
1091 "rx_missed", |
|
1092 "align_errors", |
|
1093 "tx_single_collisions", |
|
1094 "tx_multi_collisions", |
|
1095 "unicast", |
|
1096 "broadcast", |
|
1097 "multicast", |
|
1098 "tx_aborted", |
|
1099 "tx_underrun", |
|
1100 }; |
|
1101 |
|
1102 struct rtl8169_counters { |
|
1103 __le64 tx_packets; |
|
1104 __le64 rx_packets; |
|
1105 __le64 tx_errors; |
|
1106 __le32 rx_errors; |
|
1107 __le16 rx_missed; |
|
1108 __le16 align_errors; |
|
1109 __le32 tx_one_collision; |
|
1110 __le32 tx_multi_collision; |
|
1111 __le64 rx_unicast; |
|
1112 __le64 rx_broadcast; |
|
1113 __le32 rx_multicast; |
|
1114 __le16 tx_aborted; |
|
1115 __le16 tx_underun; |
|
1116 }; |
|
1117 |
|
1118 static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
|
1119 { |
|
1120 switch (sset) { |
|
1121 case ETH_SS_STATS: |
|
1122 return ARRAY_SIZE(rtl8169_gstrings); |
|
1123 default: |
|
1124 return -EOPNOTSUPP; |
|
1125 } |
|
1126 } |
|
1127 |
|
1128 static void rtl8169_get_ethtool_stats(struct net_device *dev, |
|
1129 struct ethtool_stats *stats, u64 *data) |
|
1130 { |
|
1131 struct rtl8169_private *tp = netdev_priv(dev); |
|
1132 void __iomem *ioaddr = tp->mmio_addr; |
|
1133 struct rtl8169_counters *counters; |
|
1134 dma_addr_t paddr; |
|
1135 u32 cmd; |
|
1136 |
|
1137 ASSERT_RTNL(); |
|
1138 |
|
1139 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); |
|
1140 if (!counters) |
|
1141 return; |
|
1142 |
|
1143 RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
|
1144 cmd = (u64)paddr & DMA_32BIT_MASK; |
|
1145 RTL_W32(CounterAddrLow, cmd); |
|
1146 RTL_W32(CounterAddrLow, cmd | CounterDump); |
|
1147 |
|
1148 while (RTL_R32(CounterAddrLow) & CounterDump) { |
|
1149 if (msleep_interruptible(1)) |
|
1150 break; |
|
1151 } |
|
1152 |
|
1153 RTL_W32(CounterAddrLow, 0); |
|
1154 RTL_W32(CounterAddrHigh, 0); |
|
1155 |
|
1156 data[0] = le64_to_cpu(counters->tx_packets); |
|
1157 data[1] = le64_to_cpu(counters->rx_packets); |
|
1158 data[2] = le64_to_cpu(counters->tx_errors); |
|
1159 data[3] = le32_to_cpu(counters->rx_errors); |
|
1160 data[4] = le16_to_cpu(counters->rx_missed); |
|
1161 data[5] = le16_to_cpu(counters->align_errors); |
|
1162 data[6] = le32_to_cpu(counters->tx_one_collision); |
|
1163 data[7] = le32_to_cpu(counters->tx_multi_collision); |
|
1164 data[8] = le64_to_cpu(counters->rx_unicast); |
|
1165 data[9] = le64_to_cpu(counters->rx_broadcast); |
|
1166 data[10] = le32_to_cpu(counters->rx_multicast); |
|
1167 data[11] = le16_to_cpu(counters->tx_aborted); |
|
1168 data[12] = le16_to_cpu(counters->tx_underun); |
|
1169 |
|
1170 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); |
|
1171 } |
|
1172 |
|
1173 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
1174 { |
|
1175 switch(stringset) { |
|
1176 case ETH_SS_STATS: |
|
1177 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
|
1178 break; |
|
1179 } |
|
1180 } |
|
1181 |
|
1182 static const struct ethtool_ops rtl8169_ethtool_ops = { |
|
1183 .get_drvinfo = rtl8169_get_drvinfo, |
|
1184 .get_regs_len = rtl8169_get_regs_len, |
|
1185 .get_link = ethtool_op_get_link, |
|
1186 .get_settings = rtl8169_get_settings, |
|
1187 .set_settings = rtl8169_set_settings, |
|
1188 .get_msglevel = rtl8169_get_msglevel, |
|
1189 .set_msglevel = rtl8169_set_msglevel, |
|
1190 .get_rx_csum = rtl8169_get_rx_csum, |
|
1191 .set_rx_csum = rtl8169_set_rx_csum, |
|
1192 .set_tx_csum = ethtool_op_set_tx_csum, |
|
1193 .set_sg = ethtool_op_set_sg, |
|
1194 .set_tso = ethtool_op_set_tso, |
|
1195 .get_regs = rtl8169_get_regs, |
|
1196 .get_wol = rtl8169_get_wol, |
|
1197 .set_wol = rtl8169_set_wol, |
|
1198 .get_strings = rtl8169_get_strings, |
|
1199 .get_sset_count = rtl8169_get_sset_count, |
|
1200 .get_ethtool_stats = rtl8169_get_ethtool_stats, |
|
1201 }; |
|
1202 |
|
1203 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, |
|
1204 int bitnum, int bitval) |
|
1205 { |
|
1206 int val; |
|
1207 |
|
1208 val = mdio_read(ioaddr, reg); |
|
1209 val = (bitval == 1) ? |
|
1210 val | (bitval << bitnum) : val & ~(0x0001 << bitnum); |
|
1211 mdio_write(ioaddr, reg, val & 0xffff); |
|
1212 } |
|
1213 |
|
1214 static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
|
1215 void __iomem *ioaddr) |
|
1216 { |
|
1217 /* |
|
1218 * The driver currently handles the 8168Bf and the 8168Be identically |
|
1219 * but they can be identified more specifically through the test below |
|
1220 * if needed: |
|
1221 * |
|
1222 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
|
1223 * |
|
1224 * Same thing for the 8101Eb and the 8101Ec: |
|
1225 * |
|
1226 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
|
1227 */ |
|
1228 const struct { |
|
1229 u32 mask; |
|
1230 u32 val; |
|
1231 int mac_version; |
|
1232 } mac_info[] = { |
|
1233 /* 8168D family. */ |
|
1234 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 }, |
|
1235 |
|
1236 /* 8168C family. */ |
|
1237 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 }, |
|
1238 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
|
1239 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
|
1240 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
|
1241 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
|
1242 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, |
|
1243 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
|
1244 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
|
1245 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
|
1246 |
|
1247 /* 8168B family. */ |
|
1248 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, |
|
1249 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, |
|
1250 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, |
|
1251 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, |
|
1252 |
|
1253 /* 8101 family. */ |
|
1254 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
|
1255 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, |
|
1256 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, |
|
1257 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, |
|
1258 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, |
|
1259 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, |
|
1260 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
|
1261 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
|
1262 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
|
1263 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
|
1264 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, |
|
1265 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
|
1266 /* FIXME: where did these entries come from ? -- FR */ |
|
1267 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, |
|
1268 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, |
|
1269 |
|
1270 /* 8110 family. */ |
|
1271 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, |
|
1272 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, |
|
1273 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, |
|
1274 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, |
|
1275 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, |
|
1276 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, |
|
1277 |
|
1278 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */ |
|
1279 }, *p = mac_info; |
|
1280 u32 reg; |
|
1281 |
|
1282 reg = RTL_R32(TxConfig); |
|
1283 while ((reg & p->mask) != p->val) |
|
1284 p++; |
|
1285 tp->mac_version = p->mac_version; |
|
1286 |
|
1287 if (p->mask == 0x00000000) { |
|
1288 struct pci_dev *pdev = tp->pci_dev; |
|
1289 |
|
1290 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg); |
|
1291 } |
|
1292 } |
|
1293 |
|
1294 static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
|
1295 { |
|
1296 dprintk("mac_version = 0x%02x\n", tp->mac_version); |
|
1297 } |
|
1298 |
|
1299 struct phy_reg { |
|
1300 u16 reg; |
|
1301 u16 val; |
|
1302 }; |
|
1303 |
|
1304 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len) |
|
1305 { |
|
1306 while (len-- > 0) { |
|
1307 mdio_write(ioaddr, regs->reg, regs->val); |
|
1308 regs++; |
|
1309 } |
|
1310 } |
|
1311 |
|
1312 static void rtl8169s_hw_phy_config(void __iomem *ioaddr) |
|
1313 { |
|
1314 struct { |
|
1315 u16 regs[5]; /* Beware of bit-sign propagation */ |
|
1316 } phy_magic[5] = { { |
|
1317 { 0x0000, //w 4 15 12 0 |
|
1318 0x00a1, //w 3 15 0 00a1 |
|
1319 0x0008, //w 2 15 0 0008 |
|
1320 0x1020, //w 1 15 0 1020 |
|
1321 0x1000 } },{ //w 0 15 0 1000 |
|
1322 { 0x7000, //w 4 15 12 7 |
|
1323 0xff41, //w 3 15 0 ff41 |
|
1324 0xde60, //w 2 15 0 de60 |
|
1325 0x0140, //w 1 15 0 0140 |
|
1326 0x0077 } },{ //w 0 15 0 0077 |
|
1327 { 0xa000, //w 4 15 12 a |
|
1328 0xdf01, //w 3 15 0 df01 |
|
1329 0xdf20, //w 2 15 0 df20 |
|
1330 0xff95, //w 1 15 0 ff95 |
|
1331 0xfa00 } },{ //w 0 15 0 fa00 |
|
1332 { 0xb000, //w 4 15 12 b |
|
1333 0xff41, //w 3 15 0 ff41 |
|
1334 0xde20, //w 2 15 0 de20 |
|
1335 0x0140, //w 1 15 0 0140 |
|
1336 0x00bb } },{ //w 0 15 0 00bb |
|
1337 { 0xf000, //w 4 15 12 f |
|
1338 0xdf01, //w 3 15 0 df01 |
|
1339 0xdf20, //w 2 15 0 df20 |
|
1340 0xff95, //w 1 15 0 ff95 |
|
1341 0xbf00 } //w 0 15 0 bf00 |
|
1342 } |
|
1343 }, *p = phy_magic; |
|
1344 unsigned int i; |
|
1345 |
|
1346 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1 |
|
1347 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000 |
|
1348 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7 |
|
1349 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
|
1350 |
|
1351 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) { |
|
1352 int val, pos = 4; |
|
1353 |
|
1354 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); |
|
1355 mdio_write(ioaddr, pos, val); |
|
1356 while (--pos >= 0) |
|
1357 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); |
|
1358 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 |
|
1359 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
|
1360 } |
|
1361 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0 |
|
1362 } |
|
1363 |
|
1364 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) |
|
1365 { |
|
1366 struct phy_reg phy_reg_init[] = { |
|
1367 { 0x1f, 0x0002 }, |
|
1368 { 0x01, 0x90d0 }, |
|
1369 { 0x1f, 0x0000 } |
|
1370 }; |
|
1371 |
|
1372 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1373 } |
|
1374 |
|
1375 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) |
|
1376 { |
|
1377 struct phy_reg phy_reg_init[] = { |
|
1378 { 0x10, 0xf41b }, |
|
1379 { 0x1f, 0x0000 } |
|
1380 }; |
|
1381 |
|
1382 mdio_write(ioaddr, 0x1f, 0x0001); |
|
1383 mdio_patch(ioaddr, 0x16, 1 << 0); |
|
1384 |
|
1385 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1386 } |
|
1387 |
|
1388 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) |
|
1389 { |
|
1390 struct phy_reg phy_reg_init[] = { |
|
1391 { 0x1f, 0x0001 }, |
|
1392 { 0x10, 0xf41b }, |
|
1393 { 0x1f, 0x0000 } |
|
1394 }; |
|
1395 |
|
1396 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1397 } |
|
1398 |
|
1399 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) |
|
1400 { |
|
1401 struct phy_reg phy_reg_init[] = { |
|
1402 { 0x1f, 0x0000 }, |
|
1403 { 0x1d, 0x0f00 }, |
|
1404 { 0x1f, 0x0002 }, |
|
1405 { 0x0c, 0x1ec8 }, |
|
1406 { 0x1f, 0x0000 } |
|
1407 }; |
|
1408 |
|
1409 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1410 } |
|
1411 |
|
1412 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) |
|
1413 { |
|
1414 struct phy_reg phy_reg_init[] = { |
|
1415 { 0x1f, 0x0001 }, |
|
1416 { 0x1d, 0x3d98 }, |
|
1417 { 0x1f, 0x0000 } |
|
1418 }; |
|
1419 |
|
1420 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1421 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1422 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1423 |
|
1424 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1425 } |
|
1426 |
|
1427 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) |
|
1428 { |
|
1429 struct phy_reg phy_reg_init[] = { |
|
1430 { 0x1f, 0x0001 }, |
|
1431 { 0x12, 0x2300 }, |
|
1432 { 0x1f, 0x0002 }, |
|
1433 { 0x00, 0x88d4 }, |
|
1434 { 0x01, 0x82b1 }, |
|
1435 { 0x03, 0x7002 }, |
|
1436 { 0x08, 0x9e30 }, |
|
1437 { 0x09, 0x01f0 }, |
|
1438 { 0x0a, 0x5500 }, |
|
1439 { 0x0c, 0x00c8 }, |
|
1440 { 0x1f, 0x0003 }, |
|
1441 { 0x12, 0xc096 }, |
|
1442 { 0x16, 0x000a }, |
|
1443 { 0x1f, 0x0000 }, |
|
1444 { 0x1f, 0x0000 }, |
|
1445 { 0x09, 0x2000 }, |
|
1446 { 0x09, 0x0000 } |
|
1447 }; |
|
1448 |
|
1449 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1450 |
|
1451 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1452 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1453 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1454 } |
|
1455 |
|
1456 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) |
|
1457 { |
|
1458 struct phy_reg phy_reg_init[] = { |
|
1459 { 0x1f, 0x0001 }, |
|
1460 { 0x12, 0x2300 }, |
|
1461 { 0x03, 0x802f }, |
|
1462 { 0x02, 0x4f02 }, |
|
1463 { 0x01, 0x0409 }, |
|
1464 { 0x00, 0xf099 }, |
|
1465 { 0x04, 0x9800 }, |
|
1466 { 0x04, 0x9000 }, |
|
1467 { 0x1d, 0x3d98 }, |
|
1468 { 0x1f, 0x0002 }, |
|
1469 { 0x0c, 0x7eb8 }, |
|
1470 { 0x06, 0x0761 }, |
|
1471 { 0x1f, 0x0003 }, |
|
1472 { 0x16, 0x0f0a }, |
|
1473 { 0x1f, 0x0000 } |
|
1474 }; |
|
1475 |
|
1476 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1477 |
|
1478 mdio_patch(ioaddr, 0x16, 1 << 0); |
|
1479 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1480 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1481 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1482 } |
|
1483 |
|
1484 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) |
|
1485 { |
|
1486 struct phy_reg phy_reg_init[] = { |
|
1487 { 0x1f, 0x0001 }, |
|
1488 { 0x12, 0x2300 }, |
|
1489 { 0x1d, 0x3d98 }, |
|
1490 { 0x1f, 0x0002 }, |
|
1491 { 0x0c, 0x7eb8 }, |
|
1492 { 0x06, 0x5461 }, |
|
1493 { 0x1f, 0x0003 }, |
|
1494 { 0x16, 0x0f0a }, |
|
1495 { 0x1f, 0x0000 } |
|
1496 }; |
|
1497 |
|
1498 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1499 |
|
1500 mdio_patch(ioaddr, 0x16, 1 << 0); |
|
1501 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1502 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1503 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1504 } |
|
1505 |
|
1506 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) |
|
1507 { |
|
1508 rtl8168c_3_hw_phy_config(ioaddr); |
|
1509 } |
|
1510 |
|
1511 static void rtl8168d_hw_phy_config(void __iomem *ioaddr) |
|
1512 { |
|
1513 struct phy_reg phy_reg_init_0[] = { |
|
1514 { 0x1f, 0x0001 }, |
|
1515 { 0x09, 0x2770 }, |
|
1516 { 0x08, 0x04d0 }, |
|
1517 { 0x0b, 0xad15 }, |
|
1518 { 0x0c, 0x5bf0 }, |
|
1519 { 0x1c, 0xf101 }, |
|
1520 { 0x1f, 0x0003 }, |
|
1521 { 0x14, 0x94d7 }, |
|
1522 { 0x12, 0xf4d6 }, |
|
1523 { 0x09, 0xca0f }, |
|
1524 { 0x1f, 0x0002 }, |
|
1525 { 0x0b, 0x0b10 }, |
|
1526 { 0x0c, 0xd1f7 }, |
|
1527 { 0x1f, 0x0002 }, |
|
1528 { 0x06, 0x5461 }, |
|
1529 { 0x1f, 0x0002 }, |
|
1530 { 0x05, 0x6662 }, |
|
1531 { 0x1f, 0x0000 }, |
|
1532 { 0x14, 0x0060 }, |
|
1533 { 0x1f, 0x0000 }, |
|
1534 { 0x0d, 0xf8a0 }, |
|
1535 { 0x1f, 0x0005 }, |
|
1536 { 0x05, 0xffc2 } |
|
1537 }; |
|
1538 |
|
1539 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
1540 |
|
1541 if (mdio_read(ioaddr, 0x06) == 0xc400) { |
|
1542 struct phy_reg phy_reg_init_1[] = { |
|
1543 { 0x1f, 0x0005 }, |
|
1544 { 0x01, 0x0300 }, |
|
1545 { 0x1f, 0x0000 }, |
|
1546 { 0x11, 0x401c }, |
|
1547 { 0x16, 0x4100 }, |
|
1548 { 0x1f, 0x0005 }, |
|
1549 { 0x07, 0x0010 }, |
|
1550 { 0x05, 0x83dc }, |
|
1551 { 0x06, 0x087d }, |
|
1552 { 0x05, 0x8300 }, |
|
1553 { 0x06, 0x0101 }, |
|
1554 { 0x06, 0x05f8 }, |
|
1555 { 0x06, 0xf9fa }, |
|
1556 { 0x06, 0xfbef }, |
|
1557 { 0x06, 0x79e2 }, |
|
1558 { 0x06, 0x835f }, |
|
1559 { 0x06, 0xe0f8 }, |
|
1560 { 0x06, 0x9ae1 }, |
|
1561 { 0x06, 0xf89b }, |
|
1562 { 0x06, 0xef31 }, |
|
1563 { 0x06, 0x3b65 }, |
|
1564 { 0x06, 0xaa07 }, |
|
1565 { 0x06, 0x81e4 }, |
|
1566 { 0x06, 0xf89a }, |
|
1567 { 0x06, 0xe5f8 }, |
|
1568 { 0x06, 0x9baf }, |
|
1569 { 0x06, 0x06ae }, |
|
1570 { 0x05, 0x83dc }, |
|
1571 { 0x06, 0x8300 }, |
|
1572 }; |
|
1573 |
|
1574 rtl_phy_write(ioaddr, phy_reg_init_1, |
|
1575 ARRAY_SIZE(phy_reg_init_1)); |
|
1576 } |
|
1577 |
|
1578 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1579 } |
|
1580 |
|
1581 static void rtl8102e_hw_phy_config(void __iomem *ioaddr) |
|
1582 { |
|
1583 struct phy_reg phy_reg_init[] = { |
|
1584 { 0x1f, 0x0003 }, |
|
1585 { 0x08, 0x441d }, |
|
1586 { 0x01, 0x9100 }, |
|
1587 { 0x1f, 0x0000 } |
|
1588 }; |
|
1589 |
|
1590 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1591 mdio_patch(ioaddr, 0x11, 1 << 12); |
|
1592 mdio_patch(ioaddr, 0x19, 1 << 13); |
|
1593 |
|
1594 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1595 } |
|
1596 |
|
1597 static void rtl_hw_phy_config(struct net_device *dev) |
|
1598 { |
|
1599 struct rtl8169_private *tp = netdev_priv(dev); |
|
1600 void __iomem *ioaddr = tp->mmio_addr; |
|
1601 |
|
1602 rtl8169_print_mac_version(tp); |
|
1603 |
|
1604 switch (tp->mac_version) { |
|
1605 case RTL_GIGA_MAC_VER_01: |
|
1606 break; |
|
1607 case RTL_GIGA_MAC_VER_02: |
|
1608 case RTL_GIGA_MAC_VER_03: |
|
1609 rtl8169s_hw_phy_config(ioaddr); |
|
1610 break; |
|
1611 case RTL_GIGA_MAC_VER_04: |
|
1612 rtl8169sb_hw_phy_config(ioaddr); |
|
1613 break; |
|
1614 case RTL_GIGA_MAC_VER_07: |
|
1615 case RTL_GIGA_MAC_VER_08: |
|
1616 case RTL_GIGA_MAC_VER_09: |
|
1617 rtl8102e_hw_phy_config(ioaddr); |
|
1618 break; |
|
1619 case RTL_GIGA_MAC_VER_11: |
|
1620 rtl8168bb_hw_phy_config(ioaddr); |
|
1621 break; |
|
1622 case RTL_GIGA_MAC_VER_12: |
|
1623 rtl8168bef_hw_phy_config(ioaddr); |
|
1624 break; |
|
1625 case RTL_GIGA_MAC_VER_17: |
|
1626 rtl8168bef_hw_phy_config(ioaddr); |
|
1627 break; |
|
1628 case RTL_GIGA_MAC_VER_18: |
|
1629 rtl8168cp_1_hw_phy_config(ioaddr); |
|
1630 break; |
|
1631 case RTL_GIGA_MAC_VER_19: |
|
1632 rtl8168c_1_hw_phy_config(ioaddr); |
|
1633 break; |
|
1634 case RTL_GIGA_MAC_VER_20: |
|
1635 rtl8168c_2_hw_phy_config(ioaddr); |
|
1636 break; |
|
1637 case RTL_GIGA_MAC_VER_21: |
|
1638 rtl8168c_3_hw_phy_config(ioaddr); |
|
1639 break; |
|
1640 case RTL_GIGA_MAC_VER_22: |
|
1641 rtl8168c_4_hw_phy_config(ioaddr); |
|
1642 break; |
|
1643 case RTL_GIGA_MAC_VER_23: |
|
1644 case RTL_GIGA_MAC_VER_24: |
|
1645 rtl8168cp_2_hw_phy_config(ioaddr); |
|
1646 break; |
|
1647 case RTL_GIGA_MAC_VER_25: |
|
1648 rtl8168d_hw_phy_config(ioaddr); |
|
1649 break; |
|
1650 |
|
1651 default: |
|
1652 break; |
|
1653 } |
|
1654 } |
|
1655 |
|
1656 static void rtl8169_phy_timer(unsigned long __opaque) |
|
1657 { |
|
1658 struct net_device *dev = (struct net_device *)__opaque; |
|
1659 struct rtl8169_private *tp = netdev_priv(dev); |
|
1660 struct timer_list *timer = &tp->timer; |
|
1661 void __iomem *ioaddr = tp->mmio_addr; |
|
1662 unsigned long timeout = RTL8169_PHY_TIMEOUT; |
|
1663 |
|
1664 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
|
1665 |
|
1666 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
1667 return; |
|
1668 |
|
1669 spin_lock_irq(&tp->lock); |
|
1670 |
|
1671 if (tp->phy_reset_pending(ioaddr)) { |
|
1672 /* |
|
1673 * A busy loop could burn quite a few cycles on nowadays CPU. |
|
1674 * Let's delay the execution of the timer for a few ticks. |
|
1675 */ |
|
1676 timeout = HZ/10; |
|
1677 goto out_mod_timer; |
|
1678 } |
|
1679 |
|
1680 if (tp->link_ok(ioaddr)) |
|
1681 goto out_unlock; |
|
1682 |
|
1683 if (netif_msg_link(tp)) |
|
1684 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); |
|
1685 |
|
1686 tp->phy_reset_enable(ioaddr); |
|
1687 |
|
1688 out_mod_timer: |
|
1689 mod_timer(timer, jiffies + timeout); |
|
1690 out_unlock: |
|
1691 spin_unlock_irq(&tp->lock); |
|
1692 } |
|
1693 |
|
1694 static inline void rtl8169_delete_timer(struct net_device *dev) |
|
1695 { |
|
1696 struct rtl8169_private *tp = netdev_priv(dev); |
|
1697 struct timer_list *timer = &tp->timer; |
|
1698 |
|
1699 if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
1700 return; |
|
1701 |
|
1702 del_timer_sync(timer); |
|
1703 } |
|
1704 |
|
1705 static inline void rtl8169_request_timer(struct net_device *dev) |
|
1706 { |
|
1707 struct rtl8169_private *tp = netdev_priv(dev); |
|
1708 struct timer_list *timer = &tp->timer; |
|
1709 |
|
1710 if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
1711 return; |
|
1712 |
|
1713 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
1714 } |
|
1715 |
|
1716 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
1717 /* |
|
1718 * Polling 'interrupt' - used by things like netconsole to send skbs |
|
1719 * without having to re-enable interrupts. It's not called while |
|
1720 * the interrupt routine is executing. |
|
1721 */ |
|
1722 static void rtl8169_netpoll(struct net_device *dev) |
|
1723 { |
|
1724 struct rtl8169_private *tp = netdev_priv(dev); |
|
1725 struct pci_dev *pdev = tp->pci_dev; |
|
1726 |
|
1727 disable_irq(pdev->irq); |
|
1728 rtl8169_interrupt(pdev->irq, dev); |
|
1729 enable_irq(pdev->irq); |
|
1730 } |
|
1731 #endif |
|
1732 |
|
1733 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
|
1734 void __iomem *ioaddr) |
|
1735 { |
|
1736 iounmap(ioaddr); |
|
1737 pci_release_regions(pdev); |
|
1738 pci_disable_device(pdev); |
|
1739 free_netdev(dev); |
|
1740 } |
|
1741 |
|
1742 static void rtl8169_phy_reset(struct net_device *dev, |
|
1743 struct rtl8169_private *tp) |
|
1744 { |
|
1745 void __iomem *ioaddr = tp->mmio_addr; |
|
1746 unsigned int i; |
|
1747 |
|
1748 tp->phy_reset_enable(ioaddr); |
|
1749 for (i = 0; i < 100; i++) { |
|
1750 if (!tp->phy_reset_pending(ioaddr)) |
|
1751 return; |
|
1752 msleep(1); |
|
1753 } |
|
1754 if (netif_msg_link(tp)) |
|
1755 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); |
|
1756 } |
|
1757 |
|
1758 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
|
1759 { |
|
1760 void __iomem *ioaddr = tp->mmio_addr; |
|
1761 |
|
1762 rtl_hw_phy_config(dev); |
|
1763 |
|
1764 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
|
1765 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
1766 RTL_W8(0x82, 0x01); |
|
1767 } |
|
1768 |
|
1769 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
|
1770 |
|
1771 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
1772 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
|
1773 |
|
1774 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
|
1775 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
1776 RTL_W8(0x82, 0x01); |
|
1777 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
|
1778 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 |
|
1779 } |
|
1780 |
|
1781 rtl8169_phy_reset(dev, tp); |
|
1782 |
|
1783 /* |
|
1784 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet |
|
1785 * only 8101. Don't panic. |
|
1786 */ |
|
1787 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); |
|
1788 |
|
1789 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) |
|
1790 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); |
|
1791 } |
|
1792 |
|
1793 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
|
1794 { |
|
1795 void __iomem *ioaddr = tp->mmio_addr; |
|
1796 u32 high; |
|
1797 u32 low; |
|
1798 |
|
1799 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); |
|
1800 high = addr[4] | (addr[5] << 8); |
|
1801 |
|
1802 spin_lock_irq(&tp->lock); |
|
1803 |
|
1804 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1805 RTL_W32(MAC0, low); |
|
1806 RTL_W32(MAC4, high); |
|
1807 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1808 |
|
1809 spin_unlock_irq(&tp->lock); |
|
1810 } |
|
1811 |
|
1812 static int rtl_set_mac_address(struct net_device *dev, void *p) |
|
1813 { |
|
1814 struct rtl8169_private *tp = netdev_priv(dev); |
|
1815 struct sockaddr *addr = p; |
|
1816 |
|
1817 if (!is_valid_ether_addr(addr->sa_data)) |
|
1818 return -EADDRNOTAVAIL; |
|
1819 |
|
1820 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
1821 |
|
1822 rtl_rar_set(tp, dev->dev_addr); |
|
1823 |
|
1824 return 0; |
|
1825 } |
|
1826 |
|
1827 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
|
1828 { |
|
1829 struct rtl8169_private *tp = netdev_priv(dev); |
|
1830 struct mii_ioctl_data *data = if_mii(ifr); |
|
1831 |
|
1832 if (!netif_running(dev)) |
|
1833 return -ENODEV; |
|
1834 |
|
1835 switch (cmd) { |
|
1836 case SIOCGMIIPHY: |
|
1837 data->phy_id = 32; /* Internal PHY */ |
|
1838 return 0; |
|
1839 |
|
1840 case SIOCGMIIREG: |
|
1841 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); |
|
1842 return 0; |
|
1843 |
|
1844 case SIOCSMIIREG: |
|
1845 if (!capable(CAP_NET_ADMIN)) |
|
1846 return -EPERM; |
|
1847 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); |
|
1848 return 0; |
|
1849 } |
|
1850 return -EOPNOTSUPP; |
|
1851 } |
|
1852 |
|
1853 static const struct rtl_cfg_info { |
|
1854 void (*hw_start)(struct net_device *); |
|
1855 unsigned int region; |
|
1856 unsigned int align; |
|
1857 u16 intr_event; |
|
1858 u16 napi_event; |
|
1859 unsigned features; |
|
1860 } rtl_cfg_infos [] = { |
|
1861 [RTL_CFG_0] = { |
|
1862 .hw_start = rtl_hw_start_8169, |
|
1863 .region = 1, |
|
1864 .align = 0, |
|
1865 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
1866 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
1867 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
1868 .features = RTL_FEATURE_GMII |
|
1869 }, |
|
1870 [RTL_CFG_1] = { |
|
1871 .hw_start = rtl_hw_start_8168, |
|
1872 .region = 2, |
|
1873 .align = 8, |
|
1874 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
1875 TxErr | TxOK | RxOK | RxErr, |
|
1876 .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
|
1877 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI |
|
1878 }, |
|
1879 [RTL_CFG_2] = { |
|
1880 .hw_start = rtl_hw_start_8101, |
|
1881 .region = 2, |
|
1882 .align = 8, |
|
1883 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | |
|
1884 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
1885 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
1886 .features = RTL_FEATURE_MSI |
|
1887 } |
|
1888 }; |
|
1889 |
|
1890 /* Cfg9346_Unlock assumed. */ |
|
1891 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, |
|
1892 const struct rtl_cfg_info *cfg) |
|
1893 { |
|
1894 unsigned msi = 0; |
|
1895 u8 cfg2; |
|
1896 |
|
1897 cfg2 = RTL_R8(Config2) & ~MSIEnable; |
|
1898 if (cfg->features & RTL_FEATURE_MSI) { |
|
1899 if (pci_enable_msi(pdev)) { |
|
1900 dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); |
|
1901 } else { |
|
1902 cfg2 |= MSIEnable; |
|
1903 msi = RTL_FEATURE_MSI; |
|
1904 } |
|
1905 } |
|
1906 RTL_W8(Config2, cfg2); |
|
1907 return msi; |
|
1908 } |
|
1909 |
|
1910 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
|
1911 { |
|
1912 if (tp->features & RTL_FEATURE_MSI) { |
|
1913 pci_disable_msi(pdev); |
|
1914 tp->features &= ~RTL_FEATURE_MSI; |
|
1915 } |
|
1916 } |
|
1917 |
|
1918 static int __devinit |
|
1919 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
1920 { |
|
1921 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
|
1922 const unsigned int region = cfg->region; |
|
1923 struct rtl8169_private *tp; |
|
1924 struct mii_if_info *mii; |
|
1925 struct net_device *dev; |
|
1926 void __iomem *ioaddr; |
|
1927 unsigned int i; |
|
1928 int rc; |
|
1929 |
|
1930 if (netif_msg_drv(&debug)) { |
|
1931 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", |
|
1932 MODULENAME, RTL8169_VERSION); |
|
1933 } |
|
1934 |
|
1935 dev = alloc_etherdev(sizeof (*tp)); |
|
1936 if (!dev) { |
|
1937 if (netif_msg_drv(&debug)) |
|
1938 dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
|
1939 rc = -ENOMEM; |
|
1940 goto out; |
|
1941 } |
|
1942 |
|
1943 SET_NETDEV_DEV(dev, &pdev->dev); |
|
1944 tp = netdev_priv(dev); |
|
1945 tp->dev = dev; |
|
1946 tp->pci_dev = pdev; |
|
1947 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
|
1948 |
|
1949 mii = &tp->mii; |
|
1950 mii->dev = dev; |
|
1951 mii->mdio_read = rtl_mdio_read; |
|
1952 mii->mdio_write = rtl_mdio_write; |
|
1953 mii->phy_id_mask = 0x1f; |
|
1954 mii->reg_num_mask = 0x1f; |
|
1955 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); |
|
1956 |
|
1957 /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
1958 rc = pci_enable_device(pdev); |
|
1959 if (rc < 0) { |
|
1960 if (netif_msg_probe(tp)) |
|
1961 dev_err(&pdev->dev, "enable failure\n"); |
|
1962 goto err_out_free_dev_1; |
|
1963 } |
|
1964 |
|
1965 rc = pci_set_mwi(pdev); |
|
1966 if (rc < 0) |
|
1967 goto err_out_disable_2; |
|
1968 |
|
1969 /* make sure PCI base addr 1 is MMIO */ |
|
1970 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
|
1971 if (netif_msg_probe(tp)) { |
|
1972 dev_err(&pdev->dev, |
|
1973 "region #%d not an MMIO resource, aborting\n", |
|
1974 region); |
|
1975 } |
|
1976 rc = -ENODEV; |
|
1977 goto err_out_mwi_3; |
|
1978 } |
|
1979 |
|
1980 /* check for weird/broken PCI region reporting */ |
|
1981 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
|
1982 if (netif_msg_probe(tp)) { |
|
1983 dev_err(&pdev->dev, |
|
1984 "Invalid PCI region size(s), aborting\n"); |
|
1985 } |
|
1986 rc = -ENODEV; |
|
1987 goto err_out_mwi_3; |
|
1988 } |
|
1989 |
|
1990 rc = pci_request_regions(pdev, MODULENAME); |
|
1991 if (rc < 0) { |
|
1992 if (netif_msg_probe(tp)) |
|
1993 dev_err(&pdev->dev, "could not request regions.\n"); |
|
1994 goto err_out_mwi_3; |
|
1995 } |
|
1996 |
|
1997 tp->cp_cmd = PCIMulRW | RxChkSum; |
|
1998 |
|
1999 if ((sizeof(dma_addr_t) > 4) && |
|
2000 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) { |
|
2001 tp->cp_cmd |= PCIDAC; |
|
2002 dev->features |= NETIF_F_HIGHDMA; |
|
2003 } else { |
|
2004 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
|
2005 if (rc < 0) { |
|
2006 if (netif_msg_probe(tp)) { |
|
2007 dev_err(&pdev->dev, |
|
2008 "DMA configuration failed.\n"); |
|
2009 } |
|
2010 goto err_out_free_res_4; |
|
2011 } |
|
2012 } |
|
2013 |
|
2014 pci_set_master(pdev); |
|
2015 |
|
2016 /* ioremap MMIO region */ |
|
2017 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
|
2018 if (!ioaddr) { |
|
2019 if (netif_msg_probe(tp)) |
|
2020 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
|
2021 rc = -EIO; |
|
2022 goto err_out_free_res_4; |
|
2023 } |
|
2024 |
|
2025 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
|
2026 if (!tp->pcie_cap && netif_msg_probe(tp)) |
|
2027 dev_info(&pdev->dev, "no PCI Express capability\n"); |
|
2028 |
|
2029 RTL_W16(IntrMask, 0x0000); |
|
2030 |
|
2031 /* Soft reset the chip. */ |
|
2032 RTL_W8(ChipCmd, CmdReset); |
|
2033 |
|
2034 /* Check that the chip has finished the reset. */ |
|
2035 for (i = 0; i < 100; i++) { |
|
2036 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
2037 break; |
|
2038 msleep_interruptible(1); |
|
2039 } |
|
2040 |
|
2041 RTL_W16(IntrStatus, 0xffff); |
|
2042 |
|
2043 /* Identify chip attached to board */ |
|
2044 rtl8169_get_mac_version(tp, ioaddr); |
|
2045 |
|
2046 rtl8169_print_mac_version(tp); |
|
2047 |
|
2048 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { |
|
2049 if (tp->mac_version == rtl_chip_info[i].mac_version) |
|
2050 break; |
|
2051 } |
|
2052 if (i == ARRAY_SIZE(rtl_chip_info)) { |
|
2053 /* Unknown chip: assume array element #0, original RTL-8169 */ |
|
2054 if (netif_msg_probe(tp)) { |
|
2055 dev_printk(KERN_DEBUG, &pdev->dev, |
|
2056 "unknown chip version, assuming %s\n", |
|
2057 rtl_chip_info[0].name); |
|
2058 } |
|
2059 i = 0; |
|
2060 } |
|
2061 tp->chipset = i; |
|
2062 |
|
2063 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2064 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); |
|
2065 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); |
|
2066 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
|
2067 tp->features |= RTL_FEATURE_WOL; |
|
2068 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) |
|
2069 tp->features |= RTL_FEATURE_WOL; |
|
2070 tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
|
2071 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2072 |
|
2073 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && |
|
2074 (RTL_R8(PHYstatus) & TBI_Enable)) { |
|
2075 tp->set_speed = rtl8169_set_speed_tbi; |
|
2076 tp->get_settings = rtl8169_gset_tbi; |
|
2077 tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
|
2078 tp->phy_reset_pending = rtl8169_tbi_reset_pending; |
|
2079 tp->link_ok = rtl8169_tbi_link_ok; |
|
2080 |
|
2081 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
|
2082 } else { |
|
2083 tp->set_speed = rtl8169_set_speed_xmii; |
|
2084 tp->get_settings = rtl8169_gset_xmii; |
|
2085 tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
|
2086 tp->phy_reset_pending = rtl8169_xmii_reset_pending; |
|
2087 tp->link_ok = rtl8169_xmii_link_ok; |
|
2088 |
|
2089 dev->do_ioctl = rtl8169_ioctl; |
|
2090 } |
|
2091 |
|
2092 spin_lock_init(&tp->lock); |
|
2093 |
|
2094 tp->mmio_addr = ioaddr; |
|
2095 |
|
2096 /* Get MAC address */ |
|
2097 for (i = 0; i < MAC_ADDR_LEN; i++) |
|
2098 dev->dev_addr[i] = RTL_R8(MAC0 + i); |
|
2099 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
2100 |
|
2101 dev->open = rtl8169_open; |
|
2102 dev->hard_start_xmit = rtl8169_start_xmit; |
|
2103 dev->get_stats = rtl8169_get_stats; |
|
2104 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
|
2105 dev->stop = rtl8169_close; |
|
2106 dev->tx_timeout = rtl8169_tx_timeout; |
|
2107 dev->set_multicast_list = rtl_set_rx_mode; |
|
2108 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
|
2109 dev->irq = pdev->irq; |
|
2110 dev->base_addr = (unsigned long) ioaddr; |
|
2111 dev->change_mtu = rtl8169_change_mtu; |
|
2112 dev->set_mac_address = rtl_set_mac_address; |
|
2113 |
|
2114 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
|
2115 |
|
2116 #ifdef CONFIG_R8169_VLAN |
|
2117 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
2118 dev->vlan_rx_register = rtl8169_vlan_rx_register; |
|
2119 #endif |
|
2120 |
|
2121 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
2122 dev->poll_controller = rtl8169_netpoll; |
|
2123 #endif |
|
2124 |
|
2125 tp->intr_mask = 0xffff; |
|
2126 tp->align = cfg->align; |
|
2127 tp->hw_start = cfg->hw_start; |
|
2128 tp->intr_event = cfg->intr_event; |
|
2129 tp->napi_event = cfg->napi_event; |
|
2130 |
|
2131 init_timer(&tp->timer); |
|
2132 tp->timer.data = (unsigned long) dev; |
|
2133 tp->timer.function = rtl8169_phy_timer; |
|
2134 |
|
2135 rc = register_netdev(dev); |
|
2136 if (rc < 0) |
|
2137 goto err_out_msi_5; |
|
2138 |
|
2139 pci_set_drvdata(pdev, dev); |
|
2140 |
|
2141 if (netif_msg_probe(tp)) { |
|
2142 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff; |
|
2143 |
|
2144 printk(KERN_INFO "%s: %s at 0x%lx, " |
|
2145 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " |
|
2146 "XID %08x IRQ %d\n", |
|
2147 dev->name, |
|
2148 rtl_chip_info[tp->chipset].name, |
|
2149 dev->base_addr, |
|
2150 dev->dev_addr[0], dev->dev_addr[1], |
|
2151 dev->dev_addr[2], dev->dev_addr[3], |
|
2152 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq); |
|
2153 } |
|
2154 |
|
2155 rtl8169_init_phy(dev, tp); |
|
2156 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
|
2157 |
|
2158 out: |
|
2159 return rc; |
|
2160 |
|
2161 err_out_msi_5: |
|
2162 rtl_disable_msi(pdev, tp); |
|
2163 iounmap(ioaddr); |
|
2164 err_out_free_res_4: |
|
2165 pci_release_regions(pdev); |
|
2166 err_out_mwi_3: |
|
2167 pci_clear_mwi(pdev); |
|
2168 err_out_disable_2: |
|
2169 pci_disable_device(pdev); |
|
2170 err_out_free_dev_1: |
|
2171 free_netdev(dev); |
|
2172 goto out; |
|
2173 } |
|
2174 |
|
2175 static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
|
2176 { |
|
2177 struct net_device *dev = pci_get_drvdata(pdev); |
|
2178 struct rtl8169_private *tp = netdev_priv(dev); |
|
2179 |
|
2180 flush_scheduled_work(); |
|
2181 |
|
2182 unregister_netdev(dev); |
|
2183 rtl_disable_msi(pdev, tp); |
|
2184 rtl8169_release_board(pdev, dev, tp->mmio_addr); |
|
2185 pci_set_drvdata(pdev, NULL); |
|
2186 } |
|
2187 |
|
2188 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, |
|
2189 struct net_device *dev) |
|
2190 { |
|
2191 unsigned int mtu = dev->mtu; |
|
2192 |
|
2193 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE; |
|
2194 } |
|
2195 |
|
2196 static int rtl8169_open(struct net_device *dev) |
|
2197 { |
|
2198 struct rtl8169_private *tp = netdev_priv(dev); |
|
2199 struct pci_dev *pdev = tp->pci_dev; |
|
2200 int retval = -ENOMEM; |
|
2201 |
|
2202 |
|
2203 rtl8169_set_rxbufsize(tp, dev); |
|
2204 |
|
2205 /* |
|
2206 * Rx and Tx desscriptors needs 256 bytes alignment. |
|
2207 * pci_alloc_consistent provides more. |
|
2208 */ |
|
2209 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, |
|
2210 &tp->TxPhyAddr); |
|
2211 if (!tp->TxDescArray) |
|
2212 goto out; |
|
2213 |
|
2214 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, |
|
2215 &tp->RxPhyAddr); |
|
2216 if (!tp->RxDescArray) |
|
2217 goto err_free_tx_0; |
|
2218 |
|
2219 retval = rtl8169_init_ring(dev); |
|
2220 if (retval < 0) |
|
2221 goto err_free_rx_1; |
|
2222 |
|
2223 INIT_DELAYED_WORK(&tp->task, NULL); |
|
2224 |
|
2225 smp_mb(); |
|
2226 |
|
2227 retval = request_irq(dev->irq, rtl8169_interrupt, |
|
2228 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
|
2229 dev->name, dev); |
|
2230 if (retval < 0) |
|
2231 goto err_release_ring_2; |
|
2232 |
|
2233 napi_enable(&tp->napi); |
|
2234 |
|
2235 rtl_hw_start(dev); |
|
2236 |
|
2237 rtl8169_request_timer(dev); |
|
2238 |
|
2239 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
2240 out: |
|
2241 return retval; |
|
2242 |
|
2243 err_release_ring_2: |
|
2244 rtl8169_rx_clear(tp); |
|
2245 err_free_rx_1: |
|
2246 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
2247 tp->RxPhyAddr); |
|
2248 err_free_tx_0: |
|
2249 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
2250 tp->TxPhyAddr); |
|
2251 goto out; |
|
2252 } |
|
2253 |
|
2254 static void rtl8169_hw_reset(void __iomem *ioaddr) |
|
2255 { |
|
2256 /* Disable interrupts */ |
|
2257 rtl8169_irq_mask_and_ack(ioaddr); |
|
2258 |
|
2259 /* Reset the chipset */ |
|
2260 RTL_W8(ChipCmd, CmdReset); |
|
2261 |
|
2262 /* PCI commit */ |
|
2263 RTL_R8(ChipCmd); |
|
2264 } |
|
2265 |
|
2266 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
|
2267 { |
|
2268 void __iomem *ioaddr = tp->mmio_addr; |
|
2269 u32 cfg = rtl8169_rx_config; |
|
2270 |
|
2271 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
2272 RTL_W32(RxConfig, cfg); |
|
2273 |
|
2274 /* Set DMA burst size and Interframe Gap Time */ |
|
2275 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
2276 (InterFrameGap << TxInterFrameGapShift)); |
|
2277 } |
|
2278 |
|
2279 static void rtl_hw_start(struct net_device *dev) |
|
2280 { |
|
2281 struct rtl8169_private *tp = netdev_priv(dev); |
|
2282 void __iomem *ioaddr = tp->mmio_addr; |
|
2283 unsigned int i; |
|
2284 |
|
2285 /* Soft reset the chip. */ |
|
2286 RTL_W8(ChipCmd, CmdReset); |
|
2287 |
|
2288 /* Check that the chip has finished the reset. */ |
|
2289 for (i = 0; i < 100; i++) { |
|
2290 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
2291 break; |
|
2292 msleep_interruptible(1); |
|
2293 } |
|
2294 |
|
2295 tp->hw_start(dev); |
|
2296 |
|
2297 netif_start_queue(dev); |
|
2298 } |
|
2299 |
|
2300 |
|
2301 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
|
2302 void __iomem *ioaddr) |
|
2303 { |
|
2304 /* |
|
2305 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh |
|
2306 * register to be written before TxDescAddrLow to work. |
|
2307 * Switching from MMIO to I/O access fixes the issue as well. |
|
2308 */ |
|
2309 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
|
2310 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK); |
|
2311 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
|
2312 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK); |
|
2313 } |
|
2314 |
|
2315 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) |
|
2316 { |
|
2317 u16 cmd; |
|
2318 |
|
2319 cmd = RTL_R16(CPlusCmd); |
|
2320 RTL_W16(CPlusCmd, cmd); |
|
2321 return cmd; |
|
2322 } |
|
2323 |
|
2324 static void rtl_set_rx_max_size(void __iomem *ioaddr) |
|
2325 { |
|
2326 /* Low hurts. Let's disable the filtering. */ |
|
2327 RTL_W16(RxMaxSize, 16383); |
|
2328 } |
|
2329 |
|
2330 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
|
2331 { |
|
2332 struct { |
|
2333 u32 mac_version; |
|
2334 u32 clk; |
|
2335 u32 val; |
|
2336 } cfg2_info [] = { |
|
2337 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd |
|
2338 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, |
|
2339 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe |
|
2340 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } |
|
2341 }, *p = cfg2_info; |
|
2342 unsigned int i; |
|
2343 u32 clk; |
|
2344 |
|
2345 clk = RTL_R8(Config2) & PCI_Clock_66MHz; |
|
2346 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
|
2347 if ((p->mac_version == mac_version) && (p->clk == clk)) { |
|
2348 RTL_W32(0x7c, p->val); |
|
2349 break; |
|
2350 } |
|
2351 } |
|
2352 } |
|
2353 |
|
2354 static void rtl_hw_start_8169(struct net_device *dev) |
|
2355 { |
|
2356 struct rtl8169_private *tp = netdev_priv(dev); |
|
2357 void __iomem *ioaddr = tp->mmio_addr; |
|
2358 struct pci_dev *pdev = tp->pci_dev; |
|
2359 |
|
2360 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
|
2361 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); |
|
2362 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); |
|
2363 } |
|
2364 |
|
2365 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2366 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
2367 (tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
2368 (tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
2369 (tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
2370 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2371 |
|
2372 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2373 |
|
2374 rtl_set_rx_max_size(ioaddr); |
|
2375 |
|
2376 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
2377 (tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
2378 (tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
2379 (tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
2380 rtl_set_rx_tx_config_registers(tp); |
|
2381 |
|
2382 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
2383 |
|
2384 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
2385 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { |
|
2386 dprintk("Set MAC Reg C+CR Offset 0xE0. " |
|
2387 "Bit-3 and bit-14 MUST be 1\n"); |
|
2388 tp->cp_cmd |= (1 << 14); |
|
2389 } |
|
2390 |
|
2391 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2392 |
|
2393 rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
|
2394 |
|
2395 /* |
|
2396 * Undocumented corner. Supposedly: |
|
2397 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
2398 */ |
|
2399 RTL_W16(IntrMitigate, 0x0000); |
|
2400 |
|
2401 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2402 |
|
2403 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
|
2404 (tp->mac_version != RTL_GIGA_MAC_VER_02) && |
|
2405 (tp->mac_version != RTL_GIGA_MAC_VER_03) && |
|
2406 (tp->mac_version != RTL_GIGA_MAC_VER_04)) { |
|
2407 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2408 rtl_set_rx_tx_config_registers(tp); |
|
2409 } |
|
2410 |
|
2411 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2412 |
|
2413 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
|
2414 RTL_R8(IntrMask); |
|
2415 |
|
2416 RTL_W32(RxMissed, 0); |
|
2417 |
|
2418 rtl_set_rx_mode(dev); |
|
2419 |
|
2420 /* no early-rx interrupts */ |
|
2421 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
2422 |
|
2423 /* Enable all known interrupts by setting the interrupt mask. */ |
|
2424 RTL_W16(IntrMask, tp->intr_event); |
|
2425 } |
|
2426 |
|
2427 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
|
2428 { |
|
2429 struct net_device *dev = pci_get_drvdata(pdev); |
|
2430 struct rtl8169_private *tp = netdev_priv(dev); |
|
2431 int cap = tp->pcie_cap; |
|
2432 |
|
2433 if (cap) { |
|
2434 u16 ctl; |
|
2435 |
|
2436 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
|
2437 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; |
|
2438 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); |
|
2439 } |
|
2440 } |
|
2441 |
|
2442 static void rtl_csi_access_enable(void __iomem *ioaddr) |
|
2443 { |
|
2444 u32 csi; |
|
2445 |
|
2446 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; |
|
2447 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); |
|
2448 } |
|
2449 |
|
2450 struct ephy_info { |
|
2451 unsigned int offset; |
|
2452 u16 mask; |
|
2453 u16 bits; |
|
2454 }; |
|
2455 |
|
2456 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len) |
|
2457 { |
|
2458 u16 w; |
|
2459 |
|
2460 while (len-- > 0) { |
|
2461 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; |
|
2462 rtl_ephy_write(ioaddr, e->offset, w); |
|
2463 e++; |
|
2464 } |
|
2465 } |
|
2466 |
|
2467 static void rtl_disable_clock_request(struct pci_dev *pdev) |
|
2468 { |
|
2469 struct net_device *dev = pci_get_drvdata(pdev); |
|
2470 struct rtl8169_private *tp = netdev_priv(dev); |
|
2471 int cap = tp->pcie_cap; |
|
2472 |
|
2473 if (cap) { |
|
2474 u16 ctl; |
|
2475 |
|
2476 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
2477 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; |
|
2478 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
2479 } |
|
2480 } |
|
2481 |
|
2482 #define R8168_CPCMD_QUIRK_MASK (\ |
|
2483 EnableBist | \ |
|
2484 Mac_dbgo_oe | \ |
|
2485 Force_half_dup | \ |
|
2486 Force_rxflow_en | \ |
|
2487 Force_txflow_en | \ |
|
2488 Cxpl_dbg_sel | \ |
|
2489 ASF | \ |
|
2490 PktCntrDisable | \ |
|
2491 Mac_dbgo_sel) |
|
2492 |
|
2493 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2494 { |
|
2495 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
2496 |
|
2497 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
2498 |
|
2499 rtl_tx_performance_tweak(pdev, |
|
2500 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
2501 } |
|
2502 |
|
2503 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2504 { |
|
2505 rtl_hw_start_8168bb(ioaddr, pdev); |
|
2506 |
|
2507 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2508 |
|
2509 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
2510 } |
|
2511 |
|
2512 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2513 { |
|
2514 RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
|
2515 |
|
2516 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
2517 |
|
2518 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
2519 |
|
2520 rtl_disable_clock_request(pdev); |
|
2521 |
|
2522 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
2523 } |
|
2524 |
|
2525 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2526 { |
|
2527 static struct ephy_info e_info_8168cp[] = { |
|
2528 { 0x01, 0, 0x0001 }, |
|
2529 { 0x02, 0x0800, 0x1000 }, |
|
2530 { 0x03, 0, 0x0042 }, |
|
2531 { 0x06, 0x0080, 0x0000 }, |
|
2532 { 0x07, 0, 0x2000 } |
|
2533 }; |
|
2534 |
|
2535 rtl_csi_access_enable(ioaddr); |
|
2536 |
|
2537 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
|
2538 |
|
2539 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
2540 } |
|
2541 |
|
2542 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2543 { |
|
2544 rtl_csi_access_enable(ioaddr); |
|
2545 |
|
2546 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
2547 |
|
2548 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
2549 |
|
2550 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
2551 } |
|
2552 |
|
2553 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2554 { |
|
2555 rtl_csi_access_enable(ioaddr); |
|
2556 |
|
2557 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
2558 |
|
2559 /* Magic. */ |
|
2560 RTL_W8(DBG_REG, 0x20); |
|
2561 |
|
2562 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2563 |
|
2564 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
2565 |
|
2566 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
2567 } |
|
2568 |
|
2569 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2570 { |
|
2571 static struct ephy_info e_info_8168c_1[] = { |
|
2572 { 0x02, 0x0800, 0x1000 }, |
|
2573 { 0x03, 0, 0x0002 }, |
|
2574 { 0x06, 0x0080, 0x0000 } |
|
2575 }; |
|
2576 |
|
2577 rtl_csi_access_enable(ioaddr); |
|
2578 |
|
2579 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); |
|
2580 |
|
2581 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
|
2582 |
|
2583 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
2584 } |
|
2585 |
|
2586 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2587 { |
|
2588 static struct ephy_info e_info_8168c_2[] = { |
|
2589 { 0x01, 0, 0x0001 }, |
|
2590 { 0x03, 0x0400, 0x0220 } |
|
2591 }; |
|
2592 |
|
2593 rtl_csi_access_enable(ioaddr); |
|
2594 |
|
2595 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
|
2596 |
|
2597 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
2598 } |
|
2599 |
|
2600 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2601 { |
|
2602 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
2603 } |
|
2604 |
|
2605 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2606 { |
|
2607 rtl_csi_access_enable(ioaddr); |
|
2608 |
|
2609 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
2610 } |
|
2611 |
|
2612 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2613 { |
|
2614 rtl_csi_access_enable(ioaddr); |
|
2615 |
|
2616 rtl_disable_clock_request(pdev); |
|
2617 |
|
2618 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2619 |
|
2620 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
2621 |
|
2622 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
2623 } |
|
2624 |
|
2625 static void rtl_hw_start_8168(struct net_device *dev) |
|
2626 { |
|
2627 struct rtl8169_private *tp = netdev_priv(dev); |
|
2628 void __iomem *ioaddr = tp->mmio_addr; |
|
2629 struct pci_dev *pdev = tp->pci_dev; |
|
2630 |
|
2631 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2632 |
|
2633 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2634 |
|
2635 rtl_set_rx_max_size(ioaddr); |
|
2636 |
|
2637 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
|
2638 |
|
2639 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2640 |
|
2641 RTL_W16(IntrMitigate, 0x5151); |
|
2642 |
|
2643 /* Work around for RxFIFO overflow. */ |
|
2644 if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
|
2645 tp->intr_event |= RxFIFOOver | PCSTimeout; |
|
2646 tp->intr_event &= ~RxOverflow; |
|
2647 } |
|
2648 |
|
2649 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2650 |
|
2651 rtl_set_rx_mode(dev); |
|
2652 |
|
2653 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
2654 (InterFrameGap << TxInterFrameGapShift)); |
|
2655 |
|
2656 RTL_R8(IntrMask); |
|
2657 |
|
2658 switch (tp->mac_version) { |
|
2659 case RTL_GIGA_MAC_VER_11: |
|
2660 rtl_hw_start_8168bb(ioaddr, pdev); |
|
2661 break; |
|
2662 |
|
2663 case RTL_GIGA_MAC_VER_12: |
|
2664 case RTL_GIGA_MAC_VER_17: |
|
2665 rtl_hw_start_8168bef(ioaddr, pdev); |
|
2666 break; |
|
2667 |
|
2668 case RTL_GIGA_MAC_VER_18: |
|
2669 rtl_hw_start_8168cp_1(ioaddr, pdev); |
|
2670 break; |
|
2671 |
|
2672 case RTL_GIGA_MAC_VER_19: |
|
2673 rtl_hw_start_8168c_1(ioaddr, pdev); |
|
2674 break; |
|
2675 |
|
2676 case RTL_GIGA_MAC_VER_20: |
|
2677 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
2678 break; |
|
2679 |
|
2680 case RTL_GIGA_MAC_VER_21: |
|
2681 rtl_hw_start_8168c_3(ioaddr, pdev); |
|
2682 break; |
|
2683 |
|
2684 case RTL_GIGA_MAC_VER_22: |
|
2685 rtl_hw_start_8168c_4(ioaddr, pdev); |
|
2686 break; |
|
2687 |
|
2688 case RTL_GIGA_MAC_VER_23: |
|
2689 rtl_hw_start_8168cp_2(ioaddr, pdev); |
|
2690 break; |
|
2691 |
|
2692 case RTL_GIGA_MAC_VER_24: |
|
2693 rtl_hw_start_8168cp_3(ioaddr, pdev); |
|
2694 break; |
|
2695 |
|
2696 case RTL_GIGA_MAC_VER_25: |
|
2697 rtl_hw_start_8168d(ioaddr, pdev); |
|
2698 break; |
|
2699 |
|
2700 default: |
|
2701 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", |
|
2702 dev->name, tp->mac_version); |
|
2703 break; |
|
2704 } |
|
2705 |
|
2706 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2707 |
|
2708 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2709 |
|
2710 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
2711 |
|
2712 RTL_W16(IntrMask, tp->intr_event); |
|
2713 } |
|
2714 |
|
2715 #define R810X_CPCMD_QUIRK_MASK (\ |
|
2716 EnableBist | \ |
|
2717 Mac_dbgo_oe | \ |
|
2718 Force_half_dup | \ |
|
2719 Force_half_dup | \ |
|
2720 Force_txflow_en | \ |
|
2721 Cxpl_dbg_sel | \ |
|
2722 ASF | \ |
|
2723 PktCntrDisable | \ |
|
2724 PCIDAC | \ |
|
2725 PCIMulRW) |
|
2726 |
|
2727 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2728 { |
|
2729 static struct ephy_info e_info_8102e_1[] = { |
|
2730 { 0x01, 0, 0x6e65 }, |
|
2731 { 0x02, 0, 0x091f }, |
|
2732 { 0x03, 0, 0xc2f9 }, |
|
2733 { 0x06, 0, 0xafb5 }, |
|
2734 { 0x07, 0, 0x0e00 }, |
|
2735 { 0x19, 0, 0xec80 }, |
|
2736 { 0x01, 0, 0x2e65 }, |
|
2737 { 0x01, 0, 0x6e65 } |
|
2738 }; |
|
2739 u8 cfg1; |
|
2740 |
|
2741 rtl_csi_access_enable(ioaddr); |
|
2742 |
|
2743 RTL_W8(DBG_REG, FIX_NAK_1); |
|
2744 |
|
2745 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
2746 |
|
2747 RTL_W8(Config1, |
|
2748 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); |
|
2749 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
2750 |
|
2751 cfg1 = RTL_R8(Config1); |
|
2752 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) |
|
2753 RTL_W8(Config1, cfg1 & ~LEDS0); |
|
2754 |
|
2755 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); |
|
2756 |
|
2757 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
|
2758 } |
|
2759 |
|
2760 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2761 { |
|
2762 rtl_csi_access_enable(ioaddr); |
|
2763 |
|
2764 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
2765 |
|
2766 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); |
|
2767 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
2768 |
|
2769 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); |
|
2770 } |
|
2771 |
|
2772 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
2773 { |
|
2774 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
2775 |
|
2776 rtl_ephy_write(ioaddr, 0x03, 0xc2f9); |
|
2777 } |
|
2778 |
|
2779 static void rtl_hw_start_8101(struct net_device *dev) |
|
2780 { |
|
2781 struct rtl8169_private *tp = netdev_priv(dev); |
|
2782 void __iomem *ioaddr = tp->mmio_addr; |
|
2783 struct pci_dev *pdev = tp->pci_dev; |
|
2784 |
|
2785 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
2786 (tp->mac_version == RTL_GIGA_MAC_VER_16)) { |
|
2787 int cap = tp->pcie_cap; |
|
2788 |
|
2789 if (cap) { |
|
2790 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, |
|
2791 PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
2792 } |
|
2793 } |
|
2794 |
|
2795 switch (tp->mac_version) { |
|
2796 case RTL_GIGA_MAC_VER_07: |
|
2797 rtl_hw_start_8102e_1(ioaddr, pdev); |
|
2798 break; |
|
2799 |
|
2800 case RTL_GIGA_MAC_VER_08: |
|
2801 rtl_hw_start_8102e_3(ioaddr, pdev); |
|
2802 break; |
|
2803 |
|
2804 case RTL_GIGA_MAC_VER_09: |
|
2805 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
2806 break; |
|
2807 } |
|
2808 |
|
2809 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2810 |
|
2811 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2812 |
|
2813 rtl_set_rx_max_size(ioaddr); |
|
2814 |
|
2815 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
2816 |
|
2817 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2818 |
|
2819 RTL_W16(IntrMitigate, 0x0000); |
|
2820 |
|
2821 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2822 |
|
2823 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2824 rtl_set_rx_tx_config_registers(tp); |
|
2825 |
|
2826 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2827 |
|
2828 RTL_R8(IntrMask); |
|
2829 |
|
2830 rtl_set_rx_mode(dev); |
|
2831 |
|
2832 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2833 |
|
2834 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
|
2835 |
|
2836 RTL_W16(IntrMask, tp->intr_event); |
|
2837 } |
|
2838 |
|
2839 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
|
2840 { |
|
2841 struct rtl8169_private *tp = netdev_priv(dev); |
|
2842 int ret = 0; |
|
2843 |
|
2844 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) |
|
2845 return -EINVAL; |
|
2846 |
|
2847 dev->mtu = new_mtu; |
|
2848 |
|
2849 if (!netif_running(dev)) |
|
2850 goto out; |
|
2851 |
|
2852 rtl8169_down(dev); |
|
2853 |
|
2854 rtl8169_set_rxbufsize(tp, dev); |
|
2855 |
|
2856 ret = rtl8169_init_ring(dev); |
|
2857 if (ret < 0) |
|
2858 goto out; |
|
2859 |
|
2860 napi_enable(&tp->napi); |
|
2861 |
|
2862 rtl_hw_start(dev); |
|
2863 |
|
2864 rtl8169_request_timer(dev); |
|
2865 |
|
2866 out: |
|
2867 return ret; |
|
2868 } |
|
2869 |
|
2870 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) |
|
2871 { |
|
2872 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
|
2873 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
|
2874 } |
|
2875 |
|
2876 static void rtl8169_free_rx_skb(struct rtl8169_private *tp, |
|
2877 struct sk_buff **sk_buff, struct RxDesc *desc) |
|
2878 { |
|
2879 struct pci_dev *pdev = tp->pci_dev; |
|
2880 |
|
2881 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, |
|
2882 PCI_DMA_FROMDEVICE); |
|
2883 dev_kfree_skb(*sk_buff); |
|
2884 *sk_buff = NULL; |
|
2885 rtl8169_make_unusable_by_asic(desc); |
|
2886 } |
|
2887 |
|
2888 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) |
|
2889 { |
|
2890 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; |
|
2891 |
|
2892 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
|
2893 } |
|
2894 |
|
2895 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, |
|
2896 u32 rx_buf_sz) |
|
2897 { |
|
2898 desc->addr = cpu_to_le64(mapping); |
|
2899 wmb(); |
|
2900 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
2901 } |
|
2902 |
|
2903 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, |
|
2904 struct net_device *dev, |
|
2905 struct RxDesc *desc, int rx_buf_sz, |
|
2906 unsigned int align) |
|
2907 { |
|
2908 struct sk_buff *skb; |
|
2909 dma_addr_t mapping; |
|
2910 unsigned int pad; |
|
2911 |
|
2912 pad = align ? align : NET_IP_ALIGN; |
|
2913 |
|
2914 skb = netdev_alloc_skb(dev, rx_buf_sz + pad); |
|
2915 if (!skb) |
|
2916 goto err_out; |
|
2917 |
|
2918 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); |
|
2919 |
|
2920 mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
|
2921 PCI_DMA_FROMDEVICE); |
|
2922 |
|
2923 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); |
|
2924 out: |
|
2925 return skb; |
|
2926 |
|
2927 err_out: |
|
2928 rtl8169_make_unusable_by_asic(desc); |
|
2929 goto out; |
|
2930 } |
|
2931 |
|
2932 static void rtl8169_rx_clear(struct rtl8169_private *tp) |
|
2933 { |
|
2934 unsigned int i; |
|
2935 |
|
2936 for (i = 0; i < NUM_RX_DESC; i++) { |
|
2937 if (tp->Rx_skbuff[i]) { |
|
2938 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, |
|
2939 tp->RxDescArray + i); |
|
2940 } |
|
2941 } |
|
2942 } |
|
2943 |
|
2944 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, |
|
2945 u32 start, u32 end) |
|
2946 { |
|
2947 u32 cur; |
|
2948 |
|
2949 for (cur = start; end - cur != 0; cur++) { |
|
2950 struct sk_buff *skb; |
|
2951 unsigned int i = cur % NUM_RX_DESC; |
|
2952 |
|
2953 WARN_ON((s32)(end - cur) < 0); |
|
2954 |
|
2955 if (tp->Rx_skbuff[i]) |
|
2956 continue; |
|
2957 |
|
2958 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, |
|
2959 tp->RxDescArray + i, |
|
2960 tp->rx_buf_sz, tp->align); |
|
2961 if (!skb) |
|
2962 break; |
|
2963 |
|
2964 tp->Rx_skbuff[i] = skb; |
|
2965 } |
|
2966 return cur - start; |
|
2967 } |
|
2968 |
|
2969 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
|
2970 { |
|
2971 desc->opts1 |= cpu_to_le32(RingEnd); |
|
2972 } |
|
2973 |
|
2974 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
|
2975 { |
|
2976 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; |
|
2977 } |
|
2978 |
|
2979 static int rtl8169_init_ring(struct net_device *dev) |
|
2980 { |
|
2981 struct rtl8169_private *tp = netdev_priv(dev); |
|
2982 |
|
2983 rtl8169_init_ring_indexes(tp); |
|
2984 |
|
2985 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); |
|
2986 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); |
|
2987 |
|
2988 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) |
|
2989 goto err_out; |
|
2990 |
|
2991 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
|
2992 |
|
2993 return 0; |
|
2994 |
|
2995 err_out: |
|
2996 rtl8169_rx_clear(tp); |
|
2997 return -ENOMEM; |
|
2998 } |
|
2999 |
|
3000 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, |
|
3001 struct TxDesc *desc) |
|
3002 { |
|
3003 unsigned int len = tx_skb->len; |
|
3004 |
|
3005 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); |
|
3006 desc->opts1 = 0x00; |
|
3007 desc->opts2 = 0x00; |
|
3008 desc->addr = 0x00; |
|
3009 tx_skb->len = 0; |
|
3010 } |
|
3011 |
|
3012 static void rtl8169_tx_clear(struct rtl8169_private *tp) |
|
3013 { |
|
3014 unsigned int i; |
|
3015 |
|
3016 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { |
|
3017 unsigned int entry = i % NUM_TX_DESC; |
|
3018 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
3019 unsigned int len = tx_skb->len; |
|
3020 |
|
3021 if (len) { |
|
3022 struct sk_buff *skb = tx_skb->skb; |
|
3023 |
|
3024 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, |
|
3025 tp->TxDescArray + entry); |
|
3026 if (skb) { |
|
3027 dev_kfree_skb(skb); |
|
3028 tx_skb->skb = NULL; |
|
3029 } |
|
3030 tp->dev->stats.tx_dropped++; |
|
3031 } |
|
3032 } |
|
3033 tp->cur_tx = tp->dirty_tx = 0; |
|
3034 } |
|
3035 |
|
3036 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
|
3037 { |
|
3038 struct rtl8169_private *tp = netdev_priv(dev); |
|
3039 |
|
3040 PREPARE_DELAYED_WORK(&tp->task, task); |
|
3041 schedule_delayed_work(&tp->task, 4); |
|
3042 } |
|
3043 |
|
3044 static void rtl8169_wait_for_quiescence(struct net_device *dev) |
|
3045 { |
|
3046 struct rtl8169_private *tp = netdev_priv(dev); |
|
3047 void __iomem *ioaddr = tp->mmio_addr; |
|
3048 |
|
3049 synchronize_irq(dev->irq); |
|
3050 |
|
3051 /* Wait for any pending NAPI task to complete */ |
|
3052 napi_disable(&tp->napi); |
|
3053 |
|
3054 rtl8169_irq_mask_and_ack(ioaddr); |
|
3055 |
|
3056 tp->intr_mask = 0xffff; |
|
3057 RTL_W16(IntrMask, tp->intr_event); |
|
3058 napi_enable(&tp->napi); |
|
3059 } |
|
3060 |
|
3061 static void rtl8169_reinit_task(struct work_struct *work) |
|
3062 { |
|
3063 struct rtl8169_private *tp = |
|
3064 container_of(work, struct rtl8169_private, task.work); |
|
3065 struct net_device *dev = tp->dev; |
|
3066 int ret; |
|
3067 |
|
3068 rtnl_lock(); |
|
3069 |
|
3070 if (!netif_running(dev)) |
|
3071 goto out_unlock; |
|
3072 |
|
3073 rtl8169_wait_for_quiescence(dev); |
|
3074 rtl8169_close(dev); |
|
3075 |
|
3076 ret = rtl8169_open(dev); |
|
3077 if (unlikely(ret < 0)) { |
|
3078 if (net_ratelimit() && netif_msg_drv(tp)) { |
|
3079 printk(KERN_ERR PFX "%s: reinit failure (status = %d)." |
|
3080 " Rescheduling.\n", dev->name, ret); |
|
3081 } |
|
3082 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
3083 } |
|
3084 |
|
3085 out_unlock: |
|
3086 rtnl_unlock(); |
|
3087 } |
|
3088 |
|
3089 static void rtl8169_reset_task(struct work_struct *work) |
|
3090 { |
|
3091 struct rtl8169_private *tp = |
|
3092 container_of(work, struct rtl8169_private, task.work); |
|
3093 struct net_device *dev = tp->dev; |
|
3094 |
|
3095 rtnl_lock(); |
|
3096 |
|
3097 if (!netif_running(dev)) |
|
3098 goto out_unlock; |
|
3099 |
|
3100 rtl8169_wait_for_quiescence(dev); |
|
3101 |
|
3102 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
|
3103 rtl8169_tx_clear(tp); |
|
3104 |
|
3105 if (tp->dirty_rx == tp->cur_rx) { |
|
3106 rtl8169_init_ring_indexes(tp); |
|
3107 rtl_hw_start(dev); |
|
3108 netif_wake_queue(dev); |
|
3109 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
3110 } else { |
|
3111 if (net_ratelimit() && netif_msg_intr(tp)) { |
|
3112 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n", |
|
3113 dev->name); |
|
3114 } |
|
3115 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
3116 } |
|
3117 |
|
3118 out_unlock: |
|
3119 rtnl_unlock(); |
|
3120 } |
|
3121 |
|
3122 static void rtl8169_tx_timeout(struct net_device *dev) |
|
3123 { |
|
3124 struct rtl8169_private *tp = netdev_priv(dev); |
|
3125 |
|
3126 rtl8169_hw_reset(tp->mmio_addr); |
|
3127 |
|
3128 /* Let's wait a bit while any (async) irq lands on */ |
|
3129 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
3130 } |
|
3131 |
|
3132 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
|
3133 u32 opts1) |
|
3134 { |
|
3135 struct skb_shared_info *info = skb_shinfo(skb); |
|
3136 unsigned int cur_frag, entry; |
|
3137 struct TxDesc * uninitialized_var(txd); |
|
3138 |
|
3139 entry = tp->cur_tx; |
|
3140 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { |
|
3141 skb_frag_t *frag = info->frags + cur_frag; |
|
3142 dma_addr_t mapping; |
|
3143 u32 status, len; |
|
3144 void *addr; |
|
3145 |
|
3146 entry = (entry + 1) % NUM_TX_DESC; |
|
3147 |
|
3148 txd = tp->TxDescArray + entry; |
|
3149 len = frag->size; |
|
3150 addr = ((void *) page_address(frag->page)) + frag->page_offset; |
|
3151 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); |
|
3152 |
|
3153 /* anti gcc 2.95.3 bugware (sic) */ |
|
3154 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
3155 |
|
3156 txd->opts1 = cpu_to_le32(status); |
|
3157 txd->addr = cpu_to_le64(mapping); |
|
3158 |
|
3159 tp->tx_skb[entry].len = len; |
|
3160 } |
|
3161 |
|
3162 if (cur_frag) { |
|
3163 tp->tx_skb[entry].skb = skb; |
|
3164 txd->opts1 |= cpu_to_le32(LastFrag); |
|
3165 } |
|
3166 |
|
3167 return cur_frag; |
|
3168 } |
|
3169 |
|
3170 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) |
|
3171 { |
|
3172 if (dev->features & NETIF_F_TSO) { |
|
3173 u32 mss = skb_shinfo(skb)->gso_size; |
|
3174 |
|
3175 if (mss) |
|
3176 return LargeSend | ((mss & MSSMask) << MSSShift); |
|
3177 } |
|
3178 if (skb->ip_summed == CHECKSUM_PARTIAL) { |
|
3179 const struct iphdr *ip = ip_hdr(skb); |
|
3180 |
|
3181 if (ip->protocol == IPPROTO_TCP) |
|
3182 return IPCS | TCPCS; |
|
3183 else if (ip->protocol == IPPROTO_UDP) |
|
3184 return IPCS | UDPCS; |
|
3185 WARN_ON(1); /* we need a WARN() */ |
|
3186 } |
|
3187 return 0; |
|
3188 } |
|
3189 |
|
3190 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) |
|
3191 { |
|
3192 struct rtl8169_private *tp = netdev_priv(dev); |
|
3193 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; |
|
3194 struct TxDesc *txd = tp->TxDescArray + entry; |
|
3195 void __iomem *ioaddr = tp->mmio_addr; |
|
3196 dma_addr_t mapping; |
|
3197 u32 status, len; |
|
3198 u32 opts1; |
|
3199 int ret = NETDEV_TX_OK; |
|
3200 |
|
3201 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
|
3202 if (netif_msg_drv(tp)) { |
|
3203 printk(KERN_ERR |
|
3204 "%s: BUG! Tx Ring full when queue awake!\n", |
|
3205 dev->name); |
|
3206 } |
|
3207 goto err_stop; |
|
3208 } |
|
3209 |
|
3210 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) |
|
3211 goto err_stop; |
|
3212 |
|
3213 opts1 = DescOwn | rtl8169_tso_csum(skb, dev); |
|
3214 |
|
3215 frags = rtl8169_xmit_frags(tp, skb, opts1); |
|
3216 if (frags) { |
|
3217 len = skb_headlen(skb); |
|
3218 opts1 |= FirstFrag; |
|
3219 } else { |
|
3220 len = skb->len; |
|
3221 |
|
3222 if (unlikely(len < ETH_ZLEN)) { |
|
3223 if (skb_padto(skb, ETH_ZLEN)) |
|
3224 goto err_update_stats; |
|
3225 len = ETH_ZLEN; |
|
3226 } |
|
3227 |
|
3228 opts1 |= FirstFrag | LastFrag; |
|
3229 tp->tx_skb[entry].skb = skb; |
|
3230 } |
|
3231 |
|
3232 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); |
|
3233 |
|
3234 tp->tx_skb[entry].len = len; |
|
3235 txd->addr = cpu_to_le64(mapping); |
|
3236 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
|
3237 |
|
3238 wmb(); |
|
3239 |
|
3240 /* anti gcc 2.95.3 bugware (sic) */ |
|
3241 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
3242 txd->opts1 = cpu_to_le32(status); |
|
3243 |
|
3244 dev->trans_start = jiffies; |
|
3245 |
|
3246 tp->cur_tx += frags + 1; |
|
3247 |
|
3248 smp_wmb(); |
|
3249 |
|
3250 RTL_W8(TxPoll, NPQ); /* set polling bit */ |
|
3251 |
|
3252 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { |
|
3253 netif_stop_queue(dev); |
|
3254 smp_rmb(); |
|
3255 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) |
|
3256 netif_wake_queue(dev); |
|
3257 } |
|
3258 |
|
3259 out: |
|
3260 return ret; |
|
3261 |
|
3262 err_stop: |
|
3263 netif_stop_queue(dev); |
|
3264 ret = NETDEV_TX_BUSY; |
|
3265 err_update_stats: |
|
3266 dev->stats.tx_dropped++; |
|
3267 goto out; |
|
3268 } |
|
3269 |
|
3270 static void rtl8169_pcierr_interrupt(struct net_device *dev) |
|
3271 { |
|
3272 struct rtl8169_private *tp = netdev_priv(dev); |
|
3273 struct pci_dev *pdev = tp->pci_dev; |
|
3274 void __iomem *ioaddr = tp->mmio_addr; |
|
3275 u16 pci_status, pci_cmd; |
|
3276 |
|
3277 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
|
3278 pci_read_config_word(pdev, PCI_STATUS, &pci_status); |
|
3279 |
|
3280 if (netif_msg_intr(tp)) { |
|
3281 printk(KERN_ERR |
|
3282 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", |
|
3283 dev->name, pci_cmd, pci_status); |
|
3284 } |
|
3285 |
|
3286 /* |
|
3287 * The recovery sequence below admits a very elaborated explanation: |
|
3288 * - it seems to work; |
|
3289 * - I did not see what else could be done; |
|
3290 * - it makes iop3xx happy. |
|
3291 * |
|
3292 * Feel free to adjust to your needs. |
|
3293 */ |
|
3294 if (pdev->broken_parity_status) |
|
3295 pci_cmd &= ~PCI_COMMAND_PARITY; |
|
3296 else |
|
3297 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
|
3298 |
|
3299 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
|
3300 |
|
3301 pci_write_config_word(pdev, PCI_STATUS, |
|
3302 pci_status & (PCI_STATUS_DETECTED_PARITY | |
|
3303 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | |
|
3304 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); |
|
3305 |
|
3306 /* The infamous DAC f*ckup only happens at boot time */ |
|
3307 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { |
|
3308 if (netif_msg_intr(tp)) |
|
3309 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); |
|
3310 tp->cp_cmd &= ~PCIDAC; |
|
3311 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
3312 dev->features &= ~NETIF_F_HIGHDMA; |
|
3313 } |
|
3314 |
|
3315 rtl8169_hw_reset(ioaddr); |
|
3316 |
|
3317 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
3318 } |
|
3319 |
|
3320 static void rtl8169_tx_interrupt(struct net_device *dev, |
|
3321 struct rtl8169_private *tp, |
|
3322 void __iomem *ioaddr) |
|
3323 { |
|
3324 unsigned int dirty_tx, tx_left; |
|
3325 |
|
3326 dirty_tx = tp->dirty_tx; |
|
3327 smp_rmb(); |
|
3328 tx_left = tp->cur_tx - dirty_tx; |
|
3329 |
|
3330 while (tx_left > 0) { |
|
3331 unsigned int entry = dirty_tx % NUM_TX_DESC; |
|
3332 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
3333 u32 len = tx_skb->len; |
|
3334 u32 status; |
|
3335 |
|
3336 rmb(); |
|
3337 status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
|
3338 if (status & DescOwn) |
|
3339 break; |
|
3340 |
|
3341 dev->stats.tx_bytes += len; |
|
3342 dev->stats.tx_packets++; |
|
3343 |
|
3344 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); |
|
3345 |
|
3346 if (status & LastFrag) { |
|
3347 dev_kfree_skb_irq(tx_skb->skb); |
|
3348 tx_skb->skb = NULL; |
|
3349 } |
|
3350 dirty_tx++; |
|
3351 tx_left--; |
|
3352 } |
|
3353 |
|
3354 if (tp->dirty_tx != dirty_tx) { |
|
3355 tp->dirty_tx = dirty_tx; |
|
3356 smp_wmb(); |
|
3357 if (netif_queue_stopped(dev) && |
|
3358 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { |
|
3359 netif_wake_queue(dev); |
|
3360 } |
|
3361 /* |
|
3362 * 8168 hack: TxPoll requests are lost when the Tx packets are |
|
3363 * too close. Let's kick an extra TxPoll request when a burst |
|
3364 * of start_xmit activity is detected (if it is not detected, |
|
3365 * it is slow enough). -- FR |
|
3366 */ |
|
3367 smp_rmb(); |
|
3368 if (tp->cur_tx != dirty_tx) |
|
3369 RTL_W8(TxPoll, NPQ); |
|
3370 } |
|
3371 } |
|
3372 |
|
3373 static inline int rtl8169_fragmented_frame(u32 status) |
|
3374 { |
|
3375 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); |
|
3376 } |
|
3377 |
|
3378 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) |
|
3379 { |
|
3380 u32 opts1 = le32_to_cpu(desc->opts1); |
|
3381 u32 status = opts1 & RxProtoMask; |
|
3382 |
|
3383 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || |
|
3384 ((status == RxProtoUDP) && !(opts1 & UDPFail)) || |
|
3385 ((status == RxProtoIP) && !(opts1 & IPFail))) |
|
3386 skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
3387 else |
|
3388 skb->ip_summed = CHECKSUM_NONE; |
|
3389 } |
|
3390 |
|
3391 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, |
|
3392 struct rtl8169_private *tp, int pkt_size, |
|
3393 dma_addr_t addr) |
|
3394 { |
|
3395 struct sk_buff *skb; |
|
3396 bool done = false; |
|
3397 |
|
3398 if (pkt_size >= rx_copybreak) |
|
3399 goto out; |
|
3400 |
|
3401 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN); |
|
3402 if (!skb) |
|
3403 goto out; |
|
3404 |
|
3405 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size, |
|
3406 PCI_DMA_FROMDEVICE); |
|
3407 skb_reserve(skb, NET_IP_ALIGN); |
|
3408 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size); |
|
3409 *sk_buff = skb; |
|
3410 done = true; |
|
3411 out: |
|
3412 return done; |
|
3413 } |
|
3414 |
|
3415 static int rtl8169_rx_interrupt(struct net_device *dev, |
|
3416 struct rtl8169_private *tp, |
|
3417 void __iomem *ioaddr, u32 budget) |
|
3418 { |
|
3419 unsigned int cur_rx, rx_left; |
|
3420 unsigned int delta, count; |
|
3421 |
|
3422 cur_rx = tp->cur_rx; |
|
3423 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; |
|
3424 rx_left = min(rx_left, budget); |
|
3425 |
|
3426 for (; rx_left > 0; rx_left--, cur_rx++) { |
|
3427 unsigned int entry = cur_rx % NUM_RX_DESC; |
|
3428 struct RxDesc *desc = tp->RxDescArray + entry; |
|
3429 u32 status; |
|
3430 |
|
3431 rmb(); |
|
3432 status = le32_to_cpu(desc->opts1); |
|
3433 |
|
3434 if (status & DescOwn) |
|
3435 break; |
|
3436 if (unlikely(status & RxRES)) { |
|
3437 if (netif_msg_rx_err(tp)) { |
|
3438 printk(KERN_INFO |
|
3439 "%s: Rx ERROR. status = %08x\n", |
|
3440 dev->name, status); |
|
3441 } |
|
3442 dev->stats.rx_errors++; |
|
3443 if (status & (RxRWT | RxRUNT)) |
|
3444 dev->stats.rx_length_errors++; |
|
3445 if (status & RxCRC) |
|
3446 dev->stats.rx_crc_errors++; |
|
3447 if (status & RxFOVF) { |
|
3448 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
3449 dev->stats.rx_fifo_errors++; |
|
3450 } |
|
3451 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
3452 } else { |
|
3453 struct sk_buff *skb = tp->Rx_skbuff[entry]; |
|
3454 dma_addr_t addr = le64_to_cpu(desc->addr); |
|
3455 int pkt_size = (status & 0x00001FFF) - 4; |
|
3456 struct pci_dev *pdev = tp->pci_dev; |
|
3457 |
|
3458 /* |
|
3459 * The driver does not support incoming fragmented |
|
3460 * frames. They are seen as a symptom of over-mtu |
|
3461 * sized frames. |
|
3462 */ |
|
3463 if (unlikely(rtl8169_fragmented_frame(status))) { |
|
3464 dev->stats.rx_dropped++; |
|
3465 dev->stats.rx_length_errors++; |
|
3466 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
3467 continue; |
|
3468 } |
|
3469 |
|
3470 rtl8169_rx_csum(skb, desc); |
|
3471 |
|
3472 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) { |
|
3473 pci_dma_sync_single_for_device(pdev, addr, |
|
3474 pkt_size, PCI_DMA_FROMDEVICE); |
|
3475 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
3476 } else { |
|
3477 pci_unmap_single(pdev, addr, tp->rx_buf_sz, |
|
3478 PCI_DMA_FROMDEVICE); |
|
3479 tp->Rx_skbuff[entry] = NULL; |
|
3480 } |
|
3481 |
|
3482 skb_put(skb, pkt_size); |
|
3483 skb->protocol = eth_type_trans(skb, dev); |
|
3484 |
|
3485 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) |
|
3486 netif_receive_skb(skb); |
|
3487 |
|
3488 dev->last_rx = jiffies; |
|
3489 dev->stats.rx_bytes += pkt_size; |
|
3490 dev->stats.rx_packets++; |
|
3491 } |
|
3492 |
|
3493 /* Work around for AMD plateform. */ |
|
3494 if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
|
3495 (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
|
3496 desc->opts2 = 0; |
|
3497 cur_rx++; |
|
3498 } |
|
3499 } |
|
3500 |
|
3501 count = cur_rx - tp->cur_rx; |
|
3502 tp->cur_rx = cur_rx; |
|
3503 |
|
3504 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); |
|
3505 if (!delta && count && netif_msg_intr(tp)) |
|
3506 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); |
|
3507 tp->dirty_rx += delta; |
|
3508 |
|
3509 /* |
|
3510 * FIXME: until there is periodic timer to try and refill the ring, |
|
3511 * a temporary shortage may definitely kill the Rx process. |
|
3512 * - disable the asic to try and avoid an overflow and kick it again |
|
3513 * after refill ? |
|
3514 * - how do others driver handle this condition (Uh oh...). |
|
3515 */ |
|
3516 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) |
|
3517 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); |
|
3518 |
|
3519 return count; |
|
3520 } |
|
3521 |
|
3522 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
|
3523 { |
|
3524 struct net_device *dev = dev_instance; |
|
3525 struct rtl8169_private *tp = netdev_priv(dev); |
|
3526 void __iomem *ioaddr = tp->mmio_addr; |
|
3527 int handled = 0; |
|
3528 int status; |
|
3529 |
|
3530 status = RTL_R16(IntrStatus); |
|
3531 |
|
3532 /* hotplug/major error/no more work/shared irq */ |
|
3533 if ((status == 0xffff) || !status) |
|
3534 goto out; |
|
3535 |
|
3536 handled = 1; |
|
3537 |
|
3538 if (unlikely(!netif_running(dev))) { |
|
3539 rtl8169_asic_down(ioaddr); |
|
3540 goto out; |
|
3541 } |
|
3542 |
|
3543 status &= tp->intr_mask; |
|
3544 RTL_W16(IntrStatus, |
|
3545 (status & RxFIFOOver) ? (status | RxOverflow) : status); |
|
3546 |
|
3547 if (!(status & tp->intr_event)) |
|
3548 goto out; |
|
3549 |
|
3550 /* Work around for rx fifo overflow */ |
|
3551 if (unlikely(status & RxFIFOOver) && |
|
3552 (tp->mac_version == RTL_GIGA_MAC_VER_11)) { |
|
3553 netif_stop_queue(dev); |
|
3554 rtl8169_tx_timeout(dev); |
|
3555 goto out; |
|
3556 } |
|
3557 |
|
3558 if (unlikely(status & SYSErr)) { |
|
3559 rtl8169_pcierr_interrupt(dev); |
|
3560 goto out; |
|
3561 } |
|
3562 |
|
3563 if (status & LinkChg) |
|
3564 rtl8169_check_link_status(dev, tp, ioaddr); |
|
3565 |
|
3566 if (status & tp->napi_event) { |
|
3567 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); |
|
3568 tp->intr_mask = ~tp->napi_event; |
|
3569 |
|
3570 if (likely(netif_rx_schedule_prep(dev, &tp->napi))) |
|
3571 __netif_rx_schedule(dev, &tp->napi); |
|
3572 else if (netif_msg_intr(tp)) { |
|
3573 printk(KERN_INFO "%s: interrupt %04x in poll\n", |
|
3574 dev->name, status); |
|
3575 } |
|
3576 } |
|
3577 out: |
|
3578 return IRQ_RETVAL(handled); |
|
3579 } |
|
3580 |
|
3581 static int rtl8169_poll(struct napi_struct *napi, int budget) |
|
3582 { |
|
3583 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
|
3584 struct net_device *dev = tp->dev; |
|
3585 void __iomem *ioaddr = tp->mmio_addr; |
|
3586 int work_done; |
|
3587 |
|
3588 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
|
3589 rtl8169_tx_interrupt(dev, tp, ioaddr); |
|
3590 |
|
3591 if (work_done < budget) { |
|
3592 netif_rx_complete(dev, napi); |
|
3593 tp->intr_mask = 0xffff; |
|
3594 /* |
|
3595 * 20040426: the barrier is not strictly required but the |
|
3596 * behavior of the irq handler could be less predictable |
|
3597 * without it. Btw, the lack of flush for the posted pci |
|
3598 * write is safe - FR |
|
3599 */ |
|
3600 smp_wmb(); |
|
3601 RTL_W16(IntrMask, tp->intr_event); |
|
3602 } |
|
3603 |
|
3604 return work_done; |
|
3605 } |
|
3606 |
|
3607 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
|
3608 { |
|
3609 struct rtl8169_private *tp = netdev_priv(dev); |
|
3610 |
|
3611 if (tp->mac_version > RTL_GIGA_MAC_VER_06) |
|
3612 return; |
|
3613 |
|
3614 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); |
|
3615 RTL_W32(RxMissed, 0); |
|
3616 } |
|
3617 |
|
3618 static void rtl8169_down(struct net_device *dev) |
|
3619 { |
|
3620 struct rtl8169_private *tp = netdev_priv(dev); |
|
3621 void __iomem *ioaddr = tp->mmio_addr; |
|
3622 unsigned int intrmask; |
|
3623 |
|
3624 rtl8169_delete_timer(dev); |
|
3625 |
|
3626 netif_stop_queue(dev); |
|
3627 |
|
3628 napi_disable(&tp->napi); |
|
3629 |
|
3630 core_down: |
|
3631 spin_lock_irq(&tp->lock); |
|
3632 |
|
3633 rtl8169_asic_down(ioaddr); |
|
3634 |
|
3635 rtl8169_rx_missed(dev, ioaddr); |
|
3636 |
|
3637 spin_unlock_irq(&tp->lock); |
|
3638 |
|
3639 synchronize_irq(dev->irq); |
|
3640 |
|
3641 /* Give a racing hard_start_xmit a few cycles to complete. */ |
|
3642 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
|
3643 |
|
3644 /* |
|
3645 * And now for the 50k$ question: are IRQ disabled or not ? |
|
3646 * |
|
3647 * Two paths lead here: |
|
3648 * 1) dev->close |
|
3649 * -> netif_running() is available to sync the current code and the |
|
3650 * IRQ handler. See rtl8169_interrupt for details. |
|
3651 * 2) dev->change_mtu |
|
3652 * -> rtl8169_poll can not be issued again and re-enable the |
|
3653 * interruptions. Let's simply issue the IRQ down sequence again. |
|
3654 * |
|
3655 * No loop if hotpluged or major error (0xffff). |
|
3656 */ |
|
3657 intrmask = RTL_R16(IntrMask); |
|
3658 if (intrmask && (intrmask != 0xffff)) |
|
3659 goto core_down; |
|
3660 |
|
3661 rtl8169_tx_clear(tp); |
|
3662 |
|
3663 rtl8169_rx_clear(tp); |
|
3664 } |
|
3665 |
|
3666 static int rtl8169_close(struct net_device *dev) |
|
3667 { |
|
3668 struct rtl8169_private *tp = netdev_priv(dev); |
|
3669 struct pci_dev *pdev = tp->pci_dev; |
|
3670 |
|
3671 rtl8169_down(dev); |
|
3672 |
|
3673 free_irq(dev->irq, dev); |
|
3674 |
|
3675 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
3676 tp->RxPhyAddr); |
|
3677 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
3678 tp->TxPhyAddr); |
|
3679 tp->TxDescArray = NULL; |
|
3680 tp->RxDescArray = NULL; |
|
3681 |
|
3682 return 0; |
|
3683 } |
|
3684 |
|
3685 static void rtl_set_rx_mode(struct net_device *dev) |
|
3686 { |
|
3687 struct rtl8169_private *tp = netdev_priv(dev); |
|
3688 void __iomem *ioaddr = tp->mmio_addr; |
|
3689 unsigned long flags; |
|
3690 u32 mc_filter[2]; /* Multicast hash filter */ |
|
3691 int rx_mode; |
|
3692 u32 tmp = 0; |
|
3693 |
|
3694 if (dev->flags & IFF_PROMISC) { |
|
3695 /* Unconditionally log net taps. */ |
|
3696 if (netif_msg_link(tp)) { |
|
3697 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", |
|
3698 dev->name); |
|
3699 } |
|
3700 rx_mode = |
|
3701 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
3702 AcceptAllPhys; |
|
3703 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
3704 } else if ((dev->mc_count > multicast_filter_limit) |
|
3705 || (dev->flags & IFF_ALLMULTI)) { |
|
3706 /* Too many to filter perfectly -- accept all multicasts. */ |
|
3707 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
3708 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
3709 } else { |
|
3710 struct dev_mc_list *mclist; |
|
3711 unsigned int i; |
|
3712 |
|
3713 rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
3714 mc_filter[1] = mc_filter[0] = 0; |
|
3715 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; |
|
3716 i++, mclist = mclist->next) { |
|
3717 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; |
|
3718 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
3719 rx_mode |= AcceptMulticast; |
|
3720 } |
|
3721 } |
|
3722 |
|
3723 spin_lock_irqsave(&tp->lock, flags); |
|
3724 |
|
3725 tmp = rtl8169_rx_config | rx_mode | |
|
3726 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
3727 |
|
3728 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
|
3729 u32 data = mc_filter[0]; |
|
3730 |
|
3731 mc_filter[0] = swab32(mc_filter[1]); |
|
3732 mc_filter[1] = swab32(data); |
|
3733 } |
|
3734 |
|
3735 RTL_W32(MAR0 + 0, mc_filter[0]); |
|
3736 RTL_W32(MAR0 + 4, mc_filter[1]); |
|
3737 |
|
3738 RTL_W32(RxConfig, tmp); |
|
3739 |
|
3740 spin_unlock_irqrestore(&tp->lock, flags); |
|
3741 } |
|
3742 |
|
3743 /** |
|
3744 * rtl8169_get_stats - Get rtl8169 read/write statistics |
|
3745 * @dev: The Ethernet Device to get statistics for |
|
3746 * |
|
3747 * Get TX/RX statistics for rtl8169 |
|
3748 */ |
|
3749 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) |
|
3750 { |
|
3751 struct rtl8169_private *tp = netdev_priv(dev); |
|
3752 void __iomem *ioaddr = tp->mmio_addr; |
|
3753 unsigned long flags; |
|
3754 |
|
3755 if (netif_running(dev)) { |
|
3756 spin_lock_irqsave(&tp->lock, flags); |
|
3757 rtl8169_rx_missed(dev, ioaddr); |
|
3758 spin_unlock_irqrestore(&tp->lock, flags); |
|
3759 } |
|
3760 |
|
3761 return &dev->stats; |
|
3762 } |
|
3763 |
|
3764 #ifdef CONFIG_PM |
|
3765 |
|
3766 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state) |
|
3767 { |
|
3768 struct net_device *dev = pci_get_drvdata(pdev); |
|
3769 struct rtl8169_private *tp = netdev_priv(dev); |
|
3770 void __iomem *ioaddr = tp->mmio_addr; |
|
3771 |
|
3772 if (!netif_running(dev)) |
|
3773 goto out_pci_suspend; |
|
3774 |
|
3775 netif_device_detach(dev); |
|
3776 netif_stop_queue(dev); |
|
3777 |
|
3778 spin_lock_irq(&tp->lock); |
|
3779 |
|
3780 rtl8169_asic_down(ioaddr); |
|
3781 |
|
3782 rtl8169_rx_missed(dev, ioaddr); |
|
3783 |
|
3784 spin_unlock_irq(&tp->lock); |
|
3785 |
|
3786 out_pci_suspend: |
|
3787 pci_save_state(pdev); |
|
3788 pci_enable_wake(pdev, pci_choose_state(pdev, state), |
|
3789 (tp->features & RTL_FEATURE_WOL) ? 1 : 0); |
|
3790 pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
|
3791 |
|
3792 return 0; |
|
3793 } |
|
3794 |
|
3795 static int rtl8169_resume(struct pci_dev *pdev) |
|
3796 { |
|
3797 struct net_device *dev = pci_get_drvdata(pdev); |
|
3798 |
|
3799 pci_set_power_state(pdev, PCI_D0); |
|
3800 pci_restore_state(pdev); |
|
3801 pci_enable_wake(pdev, PCI_D0, 0); |
|
3802 |
|
3803 if (!netif_running(dev)) |
|
3804 goto out; |
|
3805 |
|
3806 netif_device_attach(dev); |
|
3807 |
|
3808 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
3809 out: |
|
3810 return 0; |
|
3811 } |
|
3812 |
|
3813 static void rtl_shutdown(struct pci_dev *pdev) |
|
3814 { |
|
3815 rtl8169_suspend(pdev, PMSG_SUSPEND); |
|
3816 } |
|
3817 |
|
3818 #endif /* CONFIG_PM */ |
|
3819 |
|
3820 static struct pci_driver rtl8169_pci_driver = { |
|
3821 .name = MODULENAME, |
|
3822 .id_table = rtl8169_pci_tbl, |
|
3823 .probe = rtl8169_init_one, |
|
3824 .remove = __devexit_p(rtl8169_remove_one), |
|
3825 #ifdef CONFIG_PM |
|
3826 .suspend = rtl8169_suspend, |
|
3827 .resume = rtl8169_resume, |
|
3828 .shutdown = rtl_shutdown, |
|
3829 #endif |
|
3830 }; |
|
3831 |
|
3832 static int __init rtl8169_init_module(void) |
|
3833 { |
|
3834 return pci_register_driver(&rtl8169_pci_driver); |
|
3835 } |
|
3836 |
|
3837 static void __exit rtl8169_cleanup_module(void) |
|
3838 { |
|
3839 pci_unregister_driver(&rtl8169_pci_driver); |
|
3840 } |
|
3841 |
|
3842 module_init(rtl8169_init_module); |
|
3843 module_exit(rtl8169_cleanup_module); |